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soc/intel/apollolake: Allow USB2 eye pattern configuration in devicetree

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This code allows people to override the usb2 eye pattern
UPD settings for boards.

BUG=chrome-os-partner:61031
BRANCH=None
TEST=Usb2 function ok and make sure fsp upd is overridden

Change-Id: I5fab620a29aba196edf1f24ffe6a1695de1e523e
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/18060
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kane Chen
2017-01-11 12:53:58 +08:00
committed by Aaron Durbin
parent e7056a82e0
commit 9d490daf8d
3 changed files with 70 additions and 0 deletions
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32
src/soc/intel/apollolake/chip.c
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@@ -436,6 +436,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
{
FSP_S_CONFIG *silconfig = &silupd->FspsConfig;
static struct soc_intel_apollolake_config *cfg;
uint8_t port;
/* Load VBT before devicetree-specific config. */
silconfig->GraphicsConfigPtr = (uintptr_t)vbt;
@@ -491,6 +492,37 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
/* Bios config lockdown Audio clk and power gate */
silconfig->BiosCfgLockDown = cfg->hdaudio_bios_config_lockdown;
/* USB2 eye diagram settings per port */
for (port = 0; port < APOLLOLAKE_USB2_PORT_MAX; port++) {
if (cfg->usb2eye[port].Usb20PerPortTxPeHalf != 0)
silconfig->PortUsb20PerPortTxPeHalf[port] =
cfg->usb2eye[port].Usb20PerPortTxPeHalf;
if (cfg->usb2eye[port].Usb20PerPortPeTxiSet != 0)
silconfig->PortUsb20PerPortPeTxiSet[port] =
cfg->usb2eye[port].Usb20PerPortPeTxiSet;
if (cfg->usb2eye[port].Usb20PerPortTxiSet != 0)
silconfig->PortUsb20PerPortTxiSet[port] =
cfg->usb2eye[port].Usb20PerPortTxiSet;
if (cfg->usb2eye[port].Usb20HsSkewSel != 0)
silconfig->PortUsb20HsSkewSel[port] =
cfg->usb2eye[port].Usb20HsSkewSel;
if (cfg->usb2eye[port].Usb20IUsbTxEmphasisEn != 0)
silconfig->PortUsb20IUsbTxEmphasisEn[port] =
cfg->usb2eye[port].Usb20IUsbTxEmphasisEn;
if (cfg->usb2eye[port].Usb20PerPortRXISet != 0)
silconfig->PortUsb20PerPortRXISet[port] =
cfg->usb2eye[port].Usb20PerPortRXISet;
if (cfg->usb2eye[port].Usb20HsNpreDrvSel != 0)
silconfig->PortUsb20HsNpreDrvSel[port] =
cfg->usb2eye[port].Usb20HsNpreDrvSel;
}
}
struct chip_operations soc_intel_apollolake_ops = {