soc/intel/tigerlake: Update GPIO config

GPIOs are divided into different communities. Each community
consists of one or more GPIO groups. We need to configure the
groups from coreboot so that they are mapped properly.
GPIO communities should be properly configured in GPIO_CFG and
MISCCFG registers. GPP_* defines in gpio_soc_defs.h are configured
in GPIO_CFG register while the PMC_GPP_* in pmc.h are used to
configure the MISCCFG registers.

BUG=b:144680462
BRANCH=none
TEST=Build and boot tigerlake rvp board. Verified that after
     setting the gpe from devicetree the GPP_EN register for
     that community gets updated setting that specific bit.
     From the iotools i checked that GPE_EN register for that
     community is updated with that specific bit set to 1.

Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I585100375feee39b5a9105bdf6d9f5ca3a5bb2fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>

src/soc/intel/tigerlake/gpio.c

@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2019 Intel Corp.
+ * Copyright (C) 2020 Intel Corp.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -194,18 +194,18 @@ const struct pad_community *soc_gpio_get_community(size_t *num_communities)
 const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num)
 {
 	static const struct pmc_to_gpio_route routes[] = {
-		{ PMC_GPP_G, GPP_G },
 		{ PMC_GPP_B, GPP_B },
+		{ PMC_GPP_T, GPP_T },
 		{ PMC_GPP_A, GPP_A },
+		{ PMC_GPP_R, GPP_R },
+		{ PMC_GPD, GPD },
+		{ PMC_GPP_S, GPP_S },
 		{ PMC_GPP_H, GPP_H },
 		{ PMC_GPP_D, GPP_D },
+		{ PMC_GPP_U, GPP_U },
 		{ PMC_GPP_F, GPP_F },
-		{ PMC_GPD, GPD },
 		{ PMC_GPP_C, GPP_C },
 		{ PMC_GPP_E, GPP_E },
-		{ PMC_GPP_R, GPP_R },
-		{ PMC_GPP_S, GPP_S }
-
 	};
 	*num = ARRAY_SIZE(routes);
 	return routes;

src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h

@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2018 Intel Corporation.
+ * Copyright (C) 2020 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -21,18 +21,18 @@
  * The GPIO groups are accessed through register blocks called
  * communities.
  */
-#define GPP_G			0x0
+#define GPP_B			0x0
-#define GPP_B			0x1
+#define GPP_T			0x1
 #define GPP_A			0x2
 #define GPP_R			0x3
-#define GPP_S			0x4
+#define GPD			0x4
-#define GPD			0x5
+#define GPP_S			0x5
 #define GPP_H			0x6
 #define GPP_D			0x7
-#define GPP_F			0x8
+#define GPP_U			0x8
-#define GPP_VGPIO		0x9
+#define GPP_F			0xA
-#define GPP_C			0xA
+#define GPP_C			0xB
-#define GPP_E			0xB
+#define GPP_E			0xC
 
 #define GPIO_NUM_GROUPS		11
 #define GPIO_MAX_NUM_PER_GROUP	24

src/soc/intel/tigerlake/include/soc/pmc.h

@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2018 Intel Corporation.
+ * Copyright (C) 2020 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -115,17 +115,18 @@
 #define  GPE0_DWX_MASK			0xf
 #define  GPE0_DW_SHIFT(x)		(4*(x))
 
-#define  PMC_GPP_G			0x0
+#define  PMC_GPP_B			0x0
-#define  PMC_GPP_B			0x1
+#define  PMC_GPP_T			0x1
 #define  PMC_GPP_A			0x2
 #define  PMC_GPP_R			0x3
-#define  PMC_GPP_S			0x4
+#define  PMC_GPD			0x4
-#define  PMC_GPD			0x5
+#define  PMC_GPP_S			0x5
 #define  PMC_GPP_H			0x6
 #define  PMC_GPP_D			0x7
-#define  PMC_GPP_F			0x8
+#define  PMC_GPP_U			0x8
-#define  PMC_GPP_C			0xA
+#define  PMC_GPP_F			0xA
-#define  PMC_GPP_E			0xB
+#define  PMC_GPP_C			0xB
+#define  PMC_GPP_E			0xC
 
 #define GBLRST_CAUSE0			0x1924
 #define   GBLRST_CAUSE0_THERMTRIP	(1 << 5)