diff --git a/src/mainboard/system76/galp5/Kconfig b/src/mainboard/system76/galp5/Kconfig new file mode 100644 index 0000000000..46e59a35be --- /dev/null +++ b/src/mainboard/system76/galp5/Kconfig @@ -0,0 +1,78 @@ +if BOARD_SYSTEM76_GALP5 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select DRIVERS_I2C_HID + select DRIVERS_SYSTEM76_DGPU + select EC_SYSTEM76_EC + select EC_SYSTEM76_EC_BAT_THRESHOLDS + select EC_SYSTEM76_EC_DGPU + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_SMI_HANDLER + select INTEL_GMA_HAVE_VBT + select INTEL_LPSS_UART_FOR_CONSOLE + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM2 + select NO_UART_ON_SUPERIO + select PCIEXP_HOTPLUG + select SOC_INTEL_TIGERLAKE + select SOC_INTEL_COMMON_BLOCK_HDA + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SPD_READ_BY_WORD + select SYSTEM_TYPE_LAPTOP + select TPM_RDRESP_NEED_DELAY + select USE_LEGACY_8254_TIMER # Fix failure to boot GRUB + +config MAINBOARD_DIR + string + default "system76/galp5" + +config MAINBOARD_PART_NUMBER + string + default "galp5" + +config MAINBOARD_SMBIOS_PRODUCT_NAME + string + default "Galago Pro" + +config MAINBOARD_VERSION + string + default "galp5" + +#TODO: subsystem IDs + +config CBFS_SIZE + hex + default 0xA00000 + +config CONSOLE_POST + bool + default y + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config UART_FOR_CONSOLE + int + default 2 + +config MAX_CPUS + int + default 8 + +config DIMM_MAX + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 + +config POST_DEVICE + bool + default n + +endif diff --git a/src/mainboard/system76/galp5/Kconfig.name b/src/mainboard/system76/galp5/Kconfig.name new file mode 100644 index 0000000000..663f6503ee --- /dev/null +++ b/src/mainboard/system76/galp5/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_SYSTEM76_GALP5 + bool "galp5" diff --git a/src/mainboard/system76/galp5/Makefile.inc b/src/mainboard/system76/galp5/Makefile.inc new file mode 100644 index 0000000000..c15a0141f1 --- /dev/null +++ b/src/mainboard/system76/galp5/Makefile.inc @@ -0,0 +1,3 @@ +bootblock-y += bootblock.c +ramstage-y += ramstage.c +ramstage-y += hda_verb.c diff --git a/src/mainboard/system76/galp5/acpi/backlight.asl b/src/mainboard/system76/galp5/acpi/backlight.asl new file mode 100644 index 0000000000..12aaab6e4f --- /dev/null +++ b/src/mainboard/system76/galp5/acpi/backlight.asl @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +Scope (GFX0) { + Name (BRIG, Package (22) { + 40, /* default AC */ + 40, /* default Battery */ + 5, + 10, + 15, + 20, + 25, + 30, + 35, + 40, + 45, + 50, + 55, + 60, + 65, + 70, + 75, + 80, + 85, + 90, + 95, + 100 + }) +} diff --git a/src/mainboard/system76/galp5/acpi/gpe.asl b/src/mainboard/system76/galp5/acpi/gpe.asl new file mode 100644 index 0000000000..bc19e05169 --- /dev/null +++ b/src/mainboard/system76/galp5/acpi/gpe.asl @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +// GPP_K6 SCI +Method (_L06, 0, Serialized) { + Debug = Concatenate("GPE _L06: ", ToHexString(\_SB.PCI0.LPCB.EC0.WFNO)) + If (\_SB.PCI0.LPCB.EC0.ECOK) { + If (\_SB.PCI0.LPCB.EC0.WFNO == One) { + Notify(\_SB.LID0, 0x80) + } + } +} diff --git a/src/mainboard/system76/galp5/acpi/mainboard.asl b/src/mainboard/system76/galp5/acpi/mainboard.asl new file mode 100644 index 0000000000..eb1a57f1c7 --- /dev/null +++ b/src/mainboard/system76/galp5/acpi/mainboard.asl @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "../gpio.h" +#include + +#define EC_GPE_SCI 0x03 /* GPP_K3 */ +#define EC_GPE_SWI 0x06 /* GPP_K6 */ +#include + +Scope (\_SB) { + #include "sleep.asl" + Scope (PCI0) { + #include "backlight.asl" + } +} + +Scope (\_GPE) { + #include "gpe.asl" +} diff --git a/src/mainboard/system76/galp5/acpi/sleep.asl b/src/mainboard/system76/galp5/acpi/sleep.asl new file mode 100644 index 0000000000..cd8ffefa38 --- /dev/null +++ b/src/mainboard/system76/galp5/acpi/sleep.asl @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Method called from _PTS prior to enter sleep state */ +Method (MPTS, 1) { + \_SB.PCI0.LPCB.EC0.PTS (Arg0) + + // Turn DGPU on before sleeping + \_SB.PCI0.PEGP.DEV0._ON() +} + +/* Method called from _WAK prior to wakeup */ +Method (MWAK, 1) { + \_SB.PCI0.LPCB.EC0.WAK (Arg0) +} diff --git a/src/mainboard/system76/galp5/board_info.txt b/src/mainboard/system76/galp5/board_info.txt new file mode 100644 index 0000000000..8170b4afa2 --- /dev/null +++ b/src/mainboard/system76/galp5/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: System76 +Board name: galp5 +Category: laptop +Release year: 2020 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/system76/galp5/bootblock.c b/src/mainboard/system76/galp5/bootblock.c new file mode 100644 index 0000000000..44489dfa6d --- /dev/null +++ b/src/mainboard/system76/galp5/bootblock.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include "gpio.h" +#include + +void bootblock_mainboard_init(void) { + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); + dgpu_power_enable(1); +} diff --git a/src/mainboard/system76/galp5/data.vbt b/src/mainboard/system76/galp5/data.vbt new file mode 100644 index 0000000000..55a753d896 Binary files /dev/null and b/src/mainboard/system76/galp5/data.vbt differ diff --git a/src/mainboard/system76/galp5/devicetree.cb b/src/mainboard/system76/galp5/devicetree.cb new file mode 100644 index 0000000000..c0827caf5f --- /dev/null +++ b/src/mainboard/system76/galp5/devicetree.cb @@ -0,0 +1,299 @@ +chip soc/intel/tigerlake + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + // Touchpad I2C bus + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 80, + .fall_time_ns = 110, + }, + }" + +# ACPI (soc/intel/tigerlake/acpi.c) + # Disable DPTF + register "dptf_enable" = "0" + + # Enable Enhanced Intel SpeedStep + register "eist_enable" = "1" + + # Disable s0ix + register "s0ix_enable" = "0" + +# CPU (soc/intel/tigerlake/cpu.c) + # Power limits + register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ + // /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw + .tdp_pl1_override = 15, + // /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw + .tdp_pl2_override = 60, + }" + register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ + // /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw + .tdp_pl1_override = 15, + // /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw + .tdp_pl2_override = 60, + }" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + +# Finalize (soc/intel/tigerlake/finalize.c) + # PM Timer Enabled + register "PmTimerDisabled" = "0" + +# FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c) + # Enable C6 DRAM + register "enable_c6dram" = "1" + + # High Definition Audio + register "PchHdaAudioLinkHdaEnable" = "1" + + # System Agent dynamic frequency support + register "SaGv" = "SaGv_Disabled" + + #TODO: TCSS USB3 + register "TcssXhciEn" = "1" + +# FSP Silicon (soc/intel/tigerlake/fsp_params.c) + # Enable DPTF device + register "Device4Enable" = "1" + + #TODO: Hybrid storage mode + register "HybridStorageMode" = "1" + + # I2C channels + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad I2C bus + [PchSerialIoIndexI2C1] = PchSerialIoPci, // TODO: USB-PD? + [PchSerialIoIndexI2C2] = PchSerialIoPci, // TODO: Pantone ROM + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + }" + + # SPI channels + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI3] = PchSerialIoDisabled, + }" + + #TODO: GSpiCsMode and GSpiCsState ? + + # UART channels + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoDisabled, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoPci, // Debug console + }" + + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB Type-A Port 1 TODO + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB Type-C Port 2 TODO + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB Type-A Port 3 TODO + register "usb2_ports[3]" = "USB2_PORT_EMPTY" + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint + register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB Type-C Port 4 TODO + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Camera + register "usb2_ports[7]" = "USB2_PORT_EMPTY" + register "usb2_ports[8]" = "USB2_PORT_EMPTY" + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB Type-A Port 1 TODO + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB Type-C Port 2 TODO + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB Type-A Port 3 TODO + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB Type-C Port 4 TODO + + # PCIe root ports: + # PCIe 4 x4 - SSD1 + # 5 x4 - DGPU + # 9 x1 - CARD + # 10 x1 - GLAN + # 11 x1 - WLAN + + # PCIe clocks: + # 0 - SSD1 + # 1 - WLAN + # 2 - DGPU + # 3 - CARD + # 4 - GLAN + + #TODO: how to set up PCIE4? + register "PcieClkSrcClkReq[0]" = "0" + + # PCIe root port #5 x4, Clock 2 (NVIDIA GPU) + register "PcieRpEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" + register "PcieClkSrcUsage[2]" = "4" + register "PcieClkSrcClkReq[2]" = "2" + + # PCIe root port #9 x1, Clock 3 (Card Reader) + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieClkSrcUsage[3]" = "8" + register "PcieClkSrcClkReq[3]" = "3" + + # PCIe root port #10 x1, Clock 4 (GLAN) + register "PcieRpEnable[9]" = "1" + register "PcieRpLtrEnable[9]" = "1" + register "PcieClkSrcUsage[4]" = "9" + register "PcieClkSrcClkReq[4]" = "4" + + # PCIe root port #11 x1, Clock 1 (WLAN) + register "PcieRpEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "1" + register "PcieClkSrcUsage[1]" = "10" + register "PcieClkSrcClkReq[1]" = "1" + + # Thermal + # rdmsr --bitfield 31:24 --decimal 0x1A2 + register "tcc_offset" = "13" + +# Graphics (soc/intel/tigerlake/graphics.c) +#TODO register "gfx" = "GMA_STATIC_DISPLAYS(0)" + +# LPC (soc/intel/tigerlake/lpc.c) + # LPC configuration from lspci -s 1f.0 -xxx + # Address 0x84: Decode 0x80 - 0x8F (Port 80) + register "gen1_dec" = "0x000c0081" + # Address 0x88: Decode 0x68 - 0x6F (PMC) + register "gen2_dec" = "0x00040069" + # Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command) + register "gen3_dec" = "0x00fc0E01" + # Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug) + register "gen4_dec" = "0x00fc0F01" + +# PMC (soc/intel/tigerlake/pmc.c) + # TODO: Disable deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "0" + +# PM Util (soc/intel/tigerlake/pmutil.c) + # GPE configuration + # sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG) + register "pmc_gpe0_dw0" = "PMC_GPP_A" + register "pmc_gpe0_dw1" = "PMC_GPP_R" + register "pmc_gpe0_dw2" = "PMC_GPD" + +# SMI Handler (soc/intel/tigerlake/smihandler.c) + # Disable HECI + register "HeciEnabled" = "0" + + +# Actual device tree + device cpu_cluster 0 on + device lapic 0 on end + end + + #TODO: Adjustments + device domain 0 on + #From EDS(575683) + device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y + device pci 02.0 on end # Graphics + device pci 04.0 on end # DPTF 0x9A03 + device pci 05.0 off end # IPU 0x9A19 + device pci 06.0 on end # PEG60 0x9A09 + device pci 07.0 on end # TBT_PCIe0 0x9A23 + device pci 07.1 on end # TBT_PCIe1 0x9A25 + device pci 07.2 on end # TBT_PCIe2 0x9A27 + device pci 07.3 on end # TBT_PCIe3 0x9A29 + device pci 08.0 off end # GNA 0x9A11 + device pci 09.0 off end # NPK 0x9A33 + device pci 0a.0 on end # Crash-log SRAM 0x9A0D + device pci 0d.0 on end # USB xHCI 0x9A13 + device pci 0d.1 off end # USB xDCI (OTG) 0x9A15 + device pci 0d.2 on end # TBT DMA0 0x9A1B + device pci 0d.3 off end # TBT DMA1 0x9A1D + device pci 0e.0 off end # VMD 0x9A0B + + # From PCH EDS(576591) + device pci 10.2 on end # CNVi: BT 0xA0F5 - A0F7 + device pci 10.6 off end # THC0 0xA0D0 + device pci 10.7 off end # THC1 0xA0D1 + device pci 12.0 off end # SensorHUB 0xA0FC + device pci 12.6 off end # GSPI2 0x34FB + device pci 13.0 off end # GSPI3 0xA0FD + device pci 14.0 on end # USB3.1 xHCI 0xA0ED + device pci 14.1 off end # USB3.1 xDCI 0xA0EE + device pci 14.2 on end # Shared RAM 0xA0EF + chip drivers/intel/wifi + register "wake" = "GPE0_PME_B0" + device pci 14.3 on end # CNVi: WiFi 0xA0F0 - A0F3 + end + + device pci 15.0 on # I2C0 0xA0E8 + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""TODO Touchpad"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 38 on end + end + end # I2C0 + device pci 15.1 on end # I2C1 0xA0E9 + device pci 15.2 on end # I2C2 0xA0EA + device pci 15.3 off end # I2C3 0xA0EB + device pci 16.0 off end # HECI1 0xA0E0 + device pci 16.1 off end # HECI2 0xA0E1 + device pci 16.2 off end # CSME 0xA0E2 + device pci 16.3 off end # CSME 0xA0E3 + device pci 16.4 off end # HECI3 0xA0E4 + device pci 16.5 off end # HECI4 0xA0E5 + device pci 17.0 off end # SATA 0xA0D3 + device pci 19.0 off end # I2C4 0xA0C5 + device pci 19.1 off end # I2C5 0xA0C6 + device pci 19.2 on end # UART2 0xA0C7 + device pci 1c.0 on end # RP1 0xA0B8 + device pci 1c.1 off end # RP2 0xA0B9 + device pci 1c.2 on end # RP3 0xA0BA + device pci 1c.3 on end # RP4 0xA0BB + device pci 1c.4 off end # RP5 0xA0BC + device pci 1c.5 off end # RP6 0xA0BD + device pci 1c.6 off end # RP7 0xA0BE + device pci 1c.7 off end # RP8 0xA0BF + device pci 1d.0 on end # RP9 0xA0B0 + device pci 1d.1 off end # RP10 0xA0B1 + device pci 1d.2 on end # RP11 0xA0B2 + device pci 1d.3 off end # RP12 0xA0B3 + device pci 1e.0 off end # UART0 0xA0A8 + device pci 1e.1 off end # UART1 0xA0A9 + device pci 1e.2 off end # GSPI0 0xA0AA + device pci 1e.3 off end # GSPI1 0xA0AB + device pci 1f.0 on end # eSPI 0xA080 - A09F + device pci 1f.1 on end # P2SB 0xA0A0 + device pci 1f.2 hidden # PMC 0xA0A1 + # TODO: verify + # The pmc_mux chip driver is a placeholder for the + # PMC.MUX device in the ACPI hierarchy. + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "2" + register "usb3_port_number" = "2" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 0 on end + end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "6" + register "usb3_port_number" = "4" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 1 on end + end + end + end + end # PMC + device pci 1f.3 on end # Intel HD audio 0xA0C8-A0CF + device pci 1f.4 on end # SMBus 0xA0A3 + device pci 1f.5 on end # SPI 0xA0A4 + device pci 1f.6 off end # GbE 0x15E1/0x15E2 + device pci 1f.7 off end # TH 0xA0A6 + end +end diff --git a/src/mainboard/system76/galp5/dsdt.asl b/src/mainboard/system76/galp5/dsdt.asl new file mode 100644 index 0000000000..2b847a71b3 --- /dev/null +++ b/src/mainboard/system76/galp5/dsdt.asl @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include + #include + #include + + Device (\_SB.PCI0) { + #include + #include + //TODO + #include + } + + #include + + Scope (\_SB.PCI0.LPCB) { + #include + } + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/system76/galp5/gpio.h b/src/mainboard/system76/galp5/gpio.h new file mode 100644 index 0000000000..e19b8fa863 --- /dev/null +++ b/src/mainboard/system76/galp5/gpio.h @@ -0,0 +1,223 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#define DGPU_RST_N GPP_U4 +#define DGPU_PWR_EN GPP_U5 +#define DGPU_GC6 GPP_D2 + +#ifndef __ACPI__ + +#include +#include + +/* Pad configuration in romstage. */ +static const struct pad_config early_gpio_table[] = { + PAD_CFG_TERM_GPO(GPP_U4, 0, NONE, DEEP), // DGPU_RST_N + PAD_CFG_TERM_GPO(GPP_U5, 0, NONE, DEEP), // DGPU_PWR_EN +}; + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { + PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), + PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), + PAD_CFG_GPI(GPD2, NONE, PWROK), + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + PAD_CFG_NF(GPD6, NONE, DEEP, NF1), + PAD_CFG_TERM_GPO(GPD7, 1, NONE, PWROK), + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), + PAD_CFG_TERM_GPO(GPD9, 0, NONE, PWROK), + PAD_CFG_NF(GPD10, UP_20K, DEEP, NF1), + PAD_CFG_GPI(GPD11, UP_20K, DEEP), + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + PAD_NC(GPP_A7, NONE), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF3), + PAD_NC(GPP_A10, NONE), + PAD_NC(GPP_A11, NONE), + PAD_NC(GPP_A12, NONE), + PAD_CFG_TERM_GPO(GPP_A13, 1, NONE, PLTRST), + PAD_NC(GPP_A14, NONE), + PAD_NC(GPP_A15, NONE), + PAD_NC(GPP_A16, NONE), + PAD_NC(GPP_A17, NONE), + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + PAD_NC(GPP_A19, NONE), + PAD_NC(GPP_A20, NONE), + PAD_NC(GPP_A21, NONE), + PAD_NC(GPP_A22, NONE), + PAD_CFG_TERM_GPO(GPP_A23, 0, NONE, PLTRST), + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + PAD_CFG_GPI(GPP_B2, UP_20K, DEEP), + _PAD_CFG_STRUCT(GPP_B3, 0x80800100, 0x0000), + PAD_NC(GPP_B4, NONE), + PAD_NC(GPP_B5, NONE), + PAD_NC(GPP_B6, NONE), + PAD_NC(GPP_B7, NONE), + PAD_CFG_TERM_GPO(GPP_B8, 1, NONE, DEEP), + PAD_NC(GPP_B9, NONE), + PAD_NC(GPP_B10, NONE), + PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + PAD_CFG_TERM_GPO(GPP_B14, 0, NONE, DEEP), + PAD_CFG_TERM_GPO(GPP_B15, 1, NONE, DEEP), + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_NC(GPP_B18, NONE), + PAD_NC(GPP_B19, NONE), + PAD_NC(GPP_B20, NONE), + PAD_NC(GPP_B21, NONE), + PAD_NC(GPP_B22, NONE), + PAD_CFG_TERM_GPO(GPP_B23, 0, NONE, DEEP), + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + PAD_NC(GPP_C2, NONE), + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + PAD_NC(GPP_C5, NONE), + PAD_CFG_NF(GPP_C6, NONE, PWROK, NF1), + PAD_CFG_NF(GPP_C7, NONE, PWROK, NF1), + PAD_NC(GPP_C8, NONE), + PAD_NC(GPP_C9, NONE), + PAD_NC(GPP_C10, NONE), + PAD_NC(GPP_C11, NONE), + PAD_NC(GPP_C12, NONE), + PAD_NC(GPP_C13, NONE), + _PAD_CFG_STRUCT(GPP_C14, 0x40100100, 0x3000), + PAD_NC(GPP_C15, NONE), + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + PAD_NC(GPP_C20, NONE), + PAD_NC(GPP_C21, NONE), + PAD_CFG_TERM_GPO(GPP_C22, 1, NONE, PLTRST), + _PAD_CFG_STRUCT(GPP_C23, 0x40880100, 0x0000), + PAD_CFG_GPI(GPP_D0, NONE, DEEP), + PAD_CFG_TERM_GPO(GPP_D1, 1, NONE, PLTRST), + PAD_CFG_GPI(GPP_D2, NONE, PLTRST), + PAD_CFG_GPI(GPP_D3, NONE, PLTRST), + PAD_NC(GPP_D4, NONE), + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + PAD_NC(GPP_D9, NONE), + PAD_NC(GPP_D10, NONE), + PAD_CFG_GPI(GPP_D11, DN_20K, DEEP), + PAD_CFG_GPI(GPP_D12, DN_20K, DEEP), + PAD_CFG_TERM_GPO(GPP_D13, 0, NONE, DEEP), + PAD_CFG_TERM_GPO(GPP_D14, 1, NONE, PLTRST), + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), + PAD_CFG_GPI(GPP_D17, DN_20K, DEEP), + PAD_CFG_GPI(GPP_D18, DN_20K, DEEP), + PAD_NC(GPP_D19, NONE), + PAD_NC(GPP_E0, NONE), + PAD_CFG_TERM_GPO(GPP_E1, 0, NONE, PLTRST), + _PAD_CFG_STRUCT(GPP_E2, 0x40880100, 0x0000), + PAD_CFG_GPI(GPP_E3, DN_20K, DEEP), + PAD_NC(GPP_E4, NONE), + PAD_NC(GPP_E5, NONE), + PAD_NC(GPP_E6, NONE), + _PAD_CFG_STRUCT(GPP_E7, 0x82840100, 0x0000), + PAD_NC(GPP_E8, NONE), + PAD_NC(GPP_E9, NONE), + PAD_NC(GPP_E10, NONE), + PAD_NC(GPP_E11, NONE), + PAD_NC(GPP_E12, NONE), + PAD_NC(GPP_E13, NONE), + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + PAD_NC(GPP_E15, NONE), + PAD_CFG_GPI(GPP_E16, DN_20K, DEEP), + PAD_NC(GPP_E17, NONE), + PAD_NC(GPP_E18, NATIVE), + PAD_NC(GPP_E19, NATIVE), + PAD_NC(GPP_E20, NONE), + PAD_NC(GPP_E21, NONE), + PAD_NC(GPP_E22, NONE), + PAD_NC(GPP_E23, NONE), + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), + PAD_NC(GPP_F4, NONE), + PAD_NC(GPP_F5, NONE), + PAD_NC(GPP_F6, NONE), + PAD_CFG_TERM_GPO(GPP_F7, 1, NONE, DEEP), + PAD_NC(GPP_F8, NONE), + PAD_CFG_TERM_GPO(GPP_F9, 1, NONE, DEEP), + PAD_NC(GPP_F10, NONE), + PAD_NC(GPP_F11, NONE), + PAD_NC(GPP_F12, NONE), + PAD_NC(GPP_F13, NONE), + PAD_NC(GPP_F14, NONE), + PAD_NC(GPP_F15, NONE), + PAD_NC(GPP_F16, NONE), + PAD_CFG_GPI(GPP_F17, NONE, PLTRST), + PAD_NC(GPP_F18, NONE), + PAD_NC(GPP_F19, NONE), + PAD_NC(GPP_F20, NONE), + PAD_CFG_GPI(GPP_F21, DN_20K, DEEP), + PAD_NC(GPP_F22, NONE), + PAD_NC(GPP_F23, NONE), + PAD_CFG_TERM_GPO(GPP_H0, 1, NONE, PLTRST), + PAD_NC(GPP_H1, NONE), + PAD_NC(GPP_H2, NONE), + PAD_CFG_GPI(GPP_H3, DN_20K, DEEP), + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + PAD_NC(GPP_H6, NONE), + PAD_NC(GPP_H7, NONE), + PAD_CFG_GPI(GPP_H8, DN_20K, DEEP), + PAD_CFG_GPI(GPP_H9, DN_20K, DEEP), + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), + PAD_NC(GPP_H11, NONE), + PAD_NC(GPP_H12, NONE), + PAD_NC(GPP_H13, NONE), + PAD_NC(GPP_H14, NONE), + PAD_NC(GPP_H15, NONE), + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + PAD_NC(GPP_H19, NONE), + PAD_NC(GPP_H20, NONE), + PAD_NC(GPP_H21, NONE), + PAD_NC(GPP_H22, NONE), + PAD_NC(GPP_H23, NONE), + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), + PAD_NC(GPP_R5, NONE), + PAD_NC(GPP_R6, NONE), + PAD_NC(GPP_R7, NONE), + PAD_NC(GPP_S0, NONE), + PAD_NC(GPP_S1, NONE), + PAD_NC(GPP_S2, NONE), + PAD_NC(GPP_S3, NONE), + PAD_NC(GPP_S4, NONE), + PAD_NC(GPP_S5, NONE), + PAD_NC(GPP_S6, NONE), + PAD_NC(GPP_S7, NONE), + PAD_NC(GPP_T2, NONE), + PAD_NC(GPP_T3, NONE), + PAD_CFG_TERM_GPO(GPP_U4, 1, NONE, PLTRST), + PAD_CFG_TERM_GPO(GPP_U5, 1, NONE, PLTRST), +}; + +#endif + +#endif diff --git a/src/mainboard/system76/galp5/hda_verb.c b/src/mainboard/system76/galp5/hda_verb.c new file mode 100644 index 0000000000..1f21ff77e7 --- /dev/null +++ b/src/mainboard/system76/galp5/hda_verb.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + /* Realtek, ALC293 */ + 0x10ec0293, /* Vendor ID */ + 0x15584018, /* Subsystem ID */ + 12, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x15584018), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x02211020), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x41748245), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/galp5/ramstage.c b/src/mainboard/system76/galp5/ramstage.c new file mode 100644 index 0000000000..f4b1839a4b --- /dev/null +++ b/src/mainboard/system76/galp5/ramstage.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) { + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + cnl_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/system76/galp5/romstage.c b/src/mainboard/system76/galp5/romstage.c new file mode 100644 index 0000000000..f428f0c327 --- /dev/null +++ b/src/mainboard/system76/galp5/romstage.c @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +//TODO: verify values +static const struct mb_ddr4_cfg board_cfg = { + .dq_map[0] = { + {0x0F, 0xF0}, {0x00, 0xF0}, {0x0F, 0xF0}, + //{0x0F, 0x00}, {0xFF, 0x00}, {0xFF, 0x00} + }, + .dq_map[1] = { + {0x33, 0xCC}, {0x00, 0xCC}, {0x33, 0xCC}, + //{0x33, 0x00}, {0xFF, 0x00}, {0xFF, 0x00} + }, + + .dqs_map[0] = {7, 6, 5, 4, 1, 0, 3, 2}, + .dqs_map[1] = {5, 4, 7, 6, 1, 0, 3, 2}, + + .dq_pins_interleaved = 1, + + .ect = 0, +}; + +static const struct spd_info spd = { + .topology = SODIMM, + .smbus_info[0] = { + .addr_dimm0 = 0xA0, + }, + .smbus_info[1] = { + .addr_dimm0 = 0xA4, + }, +}; + +void mainboard_memory_init_params(FSPM_UPD *mupd) { + //TODO: Allow memory clocks higher than 2933 MHz + mupd->FspmConfig.SaOcSupport = 1; + //TODO: Set primary display to internal graphics + mupd->FspmConfig.PrimaryDisplay = 0; + + //TODO: what is this for? + const bool half_populated = false; + + meminit_ddr4(&mupd->FspmConfig, &board_cfg, &spd, half_populated); +}