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sb/intel/common: Automatically generate ACPI PIRQ

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Based on change I2b5d68adabf0840162c6f295af8d10d8d3007a34
(sb/intel/common: Add function to automatically generate ACPI PIRQ).

This adds functionality to generate PIRQ ACPI tables automatically based
on the chipset registers.

Mapping of PCI interrupt pin to PIRQ is done by the chipset-specific
intel_common_map_pirq() function, an shared implementation of which is
provided for the bd82x6x, i82801, i89xx, ibexpeak and lynxpoint
chipsets.

Example generated _PRT:
    Scope (\_SB.PCI0)
    {
        Method (_PRT, 0, NotSerialized)  // _PRT: PCI Routing Table
        {
            If (PICM)
            {
                Return (Package (0x09)
                {
                    Package (0x04)
                    {
                        0x0002FFFF,
                        0x00000000,
                        0x00000000,
                        0x00000010
                    },

                    Package (0x04)
                    {
                        0x001BFFFF,
                        0x00000000,
                        0x00000000,
                        0x00000010
                    },

                    Package (0x04)
                    {
                        0x001CFFFF,
                        0x00000000,
                        0x00000000,
                        0x00000011
                    },

                    Package (0x04)
                    {
                        0x001CFFFF,
                        0x00000001,
                        0x00000000,
                        0x00000015
                    },

                    Package (0x04)
                    {
                        0x001CFFFF,
                        0x00000002,
                        0x00000000,
                        0x00000013
                    },

                    Package (0x04)
                    {
                        0x001DFFFF,
                        0x00000000,
                        0x00000000,
                        0x00000013
                    },

                    Package (0x04)
                    {
                        0x001FFFFF,
                        0x00000000,
                        0x00000000,
                        0x00000011
                    },

                    Package (0x04)
                    {
                        0x001FFFFF,
                        0x00000001,
                        0x00000000,
                        0x00000017
                    },

                    Package (0x04)
                    {
                        0x0004FFFF,
                        0x00000000,
                        0x00000000,
                        0x00000010
                    }
                })
            }
            Else
            {
                Return (Package (0x09)
                {
                    Package (0x04)
                    {
                        0x0002FFFF,
                        0x00000000,
                        \_SB.PCI0.LPCB.LNKA,
                        0x00000000
                    },

                    Package (0x04)
                    {
                        0x001BFFFF,
                        0x00000000,
                        \_SB.PCI0.LPCB.LNKA,
                        0x00000000
                    },

                    Package (0x04)
                    {
                        0x001CFFFF,
                        0x00000000,
                        \_SB.PCI0.LPCB.LNKB,
                        0x00000000
                    },

                    Package (0x04)
                    {
                        0x001CFFFF,
                        0x00000001,
                        \_SB.PCI0.LPCB.LNKF,
                        0x00000000
                    },

                    Package (0x04)
                    {
                        0x001CFFFF,
                        0x00000002,
                        \_SB.PCI0.LPCB.LNKD,
                        0x00000000
                    },

                    Package (0x04)
                    {
                        0x001DFFFF,
                        0x00000000,
                        \_SB.PCI0.LPCB.LNKD,
                        0x00000000
                    },

                    Package (0x04)
                    {
                        0x001FFFFF,
                        0x00000000,
                        \_SB.PCI0.LPCB.LNKB,
                        0x00000000
                    },

                    Package (0x04)
                    {
                        0x001FFFFF,
                        0x00000001,
                        \_SB.PCI0.LPCB.LNKH,
                        0x00000000
                    },

                    Package (0x04)
                    {
                        0x0004FFFF,
                        0x00000000,
                        \_SB.PCI0.LPCB.LNKA,
                        0x00000000
                    }
                })
            }
        }
    }

Change-Id: Ic6b8ce4a9db50211a9c26221ca10105c5a0829a0
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: https://review.coreboot.org/22810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Tobias Diedrich
2017-12-13 23:25:32 +01:00
committed by Martin Roth
parent fd305156cd
commit 9d8be5a857
6 changed files with 253 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
src/southbridge/intel/common/Kconfig
View File

@@ -12,6 +12,13 @@ config SOUTHBRIDGE_INTEL_COMMON_SPI
def_bool n
select SPI_FLASH
config SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN
def_bool n
config SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
def_bool n
select SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN
config HAVE_INTEL_CHIPSET_LOCKDOWN
def_bool n