sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/google/nissa/var/teliks: Add DP AUX BIAS connect

Browse Source 
Because one side is not displayed when using type-c projection, the
configuration of DP AUX BIAS to SOC direct connection is added.

BUG=b:352263941
TEST=DP function of MB and DB workable

Change-Id: Id89d02212cdad549d1c26ed51a8d5af0f4e757c6
Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83829
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
zengqinghong 2024-08-08 17:36:54 +08:00 committed by Felix Held
parent 933031b524
commit 9d968c93da
1 changed files with 20 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
src/mainboard/google/brya/variants/teliks/overridetree.cb
View File

@ -60,6 +60,26 @@ chip soc/intel/alderlake
# [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01515" register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01515"
# SOC Aux orientation override:
# This is a bitfield that corresponds to up to 4 TCSS ports.
# Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
# TcssAuxOri = 0100b
# Bit0 set to "0" indicates has retimer on USBC Port0, on the DB.
# Bit2 set to "1" indicates no retimer on USBC Port1, on the MB.
# Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the
# motherboard to USBC connector
register "tcss_aux_ori" = "5"
register "typec_aux_bias_pads[0]" = "{
.pad_auxp_dc = GPP_A19,
.pad_auxn_dc = GPP_A20
}"
register "typec_aux_bias_pads[1]" = "{
.pad_auxp_dc = GPP_E22,
.pad_auxn_dc = GPP_E23
}"
# FIVR configurations for teliks are disabled since the board doesn't have V1p05 and Vnn # FIVR configurations for teliks are disabled since the board doesn't have V1p05 and Vnn
# bypass rails implemented. # bypass rails implemented.
register "ext_fivr_settings" = "{ register "ext_fivr_settings" = "{