sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

AGESA_LEGACY: Apply final cleanup and file removals

Browse Source 
With no boards left using AGESA_LEGACY, wipe out remains
of that everywhere in the tree.

Change-Id: I0ddc1f400e56e42fe8a43b4766195e3a187dcea6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Kyösti Mälkki
2017-09-09 16:51:34 +03:00
committed by Martin Roth
parent 1758fd2a32
commit 9de8ab9ace
32 changed files with 12 additions and 918 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
src/northbridge/amd/agesa/Kconfig
View File

@@ -18,7 +18,6 @@ config NORTHBRIDGE_AMD_AGESA
default CPU_AMD_AGESA
select RELOCATABLE_RAMSTAGE if EARLY_CBMEM_INIT
select CBMEM_TOP_BACKUP
select LATE_CBMEM_INIT if AGESA_LEGACY_WRAPPER
if NORTHBRIDGE_AMD_AGESA

5
src/northbridge/amd/agesa/Makefile.inc
View File

@@ -21,9 +21,4 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15) += family15
subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN) += family15tn
subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB) += family16kb
ifeq ($(CONFIG_AGESA_LEGACY_WRAPPER), y)
romstage-y += agesawrapper.c
ramstage-y += agesawrapper.c
endif
endif

304
src/northbridge/amd/agesa/agesawrapper.c
View File

@@ -1,304 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011-2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <cbmem.h>
#include <stdint.h>
#include <string.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include "amdlib.h"
#include "heapManager.h"
static const struct OEM_HOOK *OemHook = &OemCustomize;
#if defined(__PRE_RAM__)
AGESA_STATUS agesawrapper_amdinitreset(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_RESET_PARAMS AmdResetParams;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
memset(&AmdResetParams, 0, sizeof(AMD_RESET_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
AmdParamStruct.AllocationMethod = ByHost;
AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
AmdParamStruct.NewStructPtr = &AmdResetParams;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct(&AmdParamStruct);
AmdResetParams.HtConfig.Depth = 0;
status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
AmdReleaseStruct(&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdinitearly(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct(&AmdParamStruct);
/* OEM Should Customize the defaults through this hook. */
AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr;
if (OemHook->InitEarly)
OemHook->InitEarly(AmdEarlyParamsPtr);
status = AmdInitEarly(AmdEarlyParamsPtr);
AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
AmdReleaseStruct(&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdinitpost(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_POST_PARAMS *PostParams;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct(&AmdParamStruct);
/* OEM Should Customize the defaults through this hook. */
PostParams = (AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr;
if (OemHook->InitPost)
OemHook->InitPost(PostParams);
status = AmdInitPost(PostParams);
AGESA_EVENTLOG(status, &PostParams->StdHeader);
backup_top_of_low_cacheable(PostParams->MemConfig.Sub4GCacheTop);
AmdReleaseStruct(&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdinitresume(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_RESUME_PARAMS *AmdResumeParamsPtr;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct(&AmdParamStruct);
AmdResumeParamsPtr = (AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr;
AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0;
AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0;
OemInitResume(&AmdResumeParamsPtr->S3DataBlock);
status = AmdInitResume(AmdResumeParamsPtr);
AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
AmdReleaseStruct(&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdinitenv(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_ENV_PARAMS *EnvParam;
/* Initialize heap space */
EmptyHeap();
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct(&AmdParamStruct);
EnvParam = (AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr;
status = AmdInitEnv(EnvParam);
AGESA_EVENTLOG(status, &EnvParam->StdHeader);
AmdReleaseStruct(&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amds3laterestore(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdInterfaceParams;
AMD_S3LATE_PARAMS AmdS3LateParams;
AMD_S3LATE_PARAMS *AmdS3LateParamsPtr;
memset(&AmdS3LateParams, 0, sizeof(AMD_S3LATE_PARAMS));
AmdInterfaceParams.StdHeader.ImageBasePtr = 0;
AmdInterfaceParams.AllocationMethod = ByHost;
AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE;
AmdInterfaceParams.NewStructPtr = &AmdS3LateParams;
AmdInterfaceParams.StdHeader.CalloutPtr = &GetBiosCallout;
AmdS3LateParamsPtr = &AmdS3LateParams;
AmdInterfaceParams.NewStructSize = sizeof(AMD_S3LATE_PARAMS);
AmdCreateStruct(&AmdInterfaceParams);
#if 0
/* TODO: What to do with NvStorage here? */
AmdS3LateParamsPtr->S3DataBlock.NvStorageSize = 0;
#endif
AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0;
OemS3LateRestore(&AmdS3LateParamsPtr->S3DataBlock);
status = AmdS3LateRestore(AmdS3LateParamsPtr);
AGESA_EVENTLOG(status, &AmdInterfaceParams.StdHeader);
ASSERT(status == AGESA_SUCCESS);
return status;
}
#else /* __PRE_RAM__ */
AGESA_STATUS agesawrapper_amdinitmid(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_MID_PARAMS *MidParam;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct(&AmdParamStruct);
/* OEM Should Customize the defaults through this hook. */
MidParam = (AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr;
if (OemHook->InitMid)
OemHook->InitMid(MidParam);
status = AmdInitMid(MidParam);
AGESA_EVENTLOG(status, &MidParam->StdHeader);
AmdReleaseStruct(&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdS3Save(void)
{
AGESA_STATUS status;
AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr;
AMD_INTERFACE_PARAMS AmdInterfaceParams;
memset(&AmdInterfaceParams, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdInterfaceParams.StdHeader.ImageBasePtr = 0;
AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
AmdInterfaceParams.StdHeader.CalloutPtr = &GetBiosCallout;
AmdInterfaceParams.AllocationMethod = PostMemDram;
AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE;
AmdInterfaceParams.StdHeader.AltImageBasePtr = 0;
AmdInterfaceParams.StdHeader.Func = 0;
AmdCreateStruct(&AmdInterfaceParams);
AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *) AmdInterfaceParams.NewStructPtr;
AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader;
status = AmdS3Save(AmdS3SaveParamsPtr);
AGESA_EVENTLOG(status, &AmdInterfaceParams.StdHeader);
ASSERT(status == AGESA_SUCCESS);
OemS3Save(&AmdS3SaveParamsPtr->S3DataBlock);
AmdReleaseStruct(&AmdInterfaceParams);
return status;
}
AGESA_STATUS agesawrapper_amdinitlate(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_LATE_PARAMS *AmdLateParams;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) || \
IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY16_KB)
AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
#endif
AmdCreateStruct(&AmdParamStruct);
AmdLateParams = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr;
status = AmdInitLate(AmdLateParams);
AGESA_EVENTLOG(status, &AmdLateParams->StdHeader);
ASSERT(status == AGESA_SUCCESS);
agesawrapper_setlateinitptr(AmdLateParams);
/* No AmdReleaseStruct(&AmdParamStruct), we need AmdLateParams later. */
return status;
}
#endif /* __PRE_RAM__ */

17
src/northbridge/amd/agesa/agesawrapper.h
View File

@@ -16,8 +16,7 @@
#ifndef _AGESAWRAPPER_H_
#define _AGESAWRAPPER_H_
#if IS_ENABLED(CONFIG_AGESA_LEGACY_WRAPPER) || \
IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER)
#if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER)
#include <stdint.h>
#include "Porting.h"
@@ -52,20 +51,6 @@ static inline int agesawrapper_amds3laterestore(void) { return -1; }
#endif
#if IS_ENABLED(CONFIG_AGESA_LEGACY_WRAPPER)
struct OEM_HOOK
{
/* romstage */
AGESA_STATUS (*InitEarly)(AMD_EARLY_PARAMS *);
AGESA_STATUS (*InitPost)(AMD_POST_PARAMS *);
/* ramstage */
AGESA_STATUS (*InitMid)(AMD_MID_PARAMS *);
};
extern const struct OEM_HOOK OemCustomize;
#endif
#if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER)
const void *agesawrapper_locate_module (const CHAR8 name[8]);

2
src/northbridge/amd/agesa/family12/Makefile.inc
View File

@@ -17,7 +17,5 @@ romstage-y += dimmSpd.c
ramstage-y += northbridge.c
ifneq ($(CONFIG_AGESA_LEGACY_WRAPPER), y)
romstage-y += state_machine.c
ramstage-y += state_machine.c
endif

22
src/northbridge/amd/agesa/family12/northbridge.c
View File

@@ -33,7 +33,6 @@
#include "sb_cimx.h"
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/agesa/agesa_helper.h>
@@ -597,26 +596,6 @@ static void domain_set_resources(device_t dev)
}
static void domain_enable_resources(device_t dev)
{
#if IS_ENABLED(CONFIG_AGESA_LEGACY_WRAPPER)
printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__);
/* Must be called after PCI enumeration and resource allocation */
#if IS_ENABLED(CONFIG_AMD_SB_CIMX)
sb_After_Pci_Init();
sb_Mid_Post_Init();
#endif
/* Enable MMIO on AMD CPU Address Map Controller */
amd_initcpuio();
agesawrapper_amdinitmid();
printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__);
#endif
}
/* Bus related code */
static void cpu_bus_init(device_t dev)
@@ -757,7 +736,6 @@ struct chip_operations northbridge_amd_agesa_family12_ops = {
static struct device_operations pci_domain_ops = {
.read_resources = domain_read_resources,
.set_resources = domain_set_resources,
.enable_resources = domain_enable_resources,
.init = DEVICE_NOOP,
.scan_bus = pci_domain_scan_bus,
};

2
src/northbridge/amd/agesa/family14/Makefile.inc
View File

@@ -17,7 +17,5 @@ romstage-y += dimmSpd.c
ramstage-y += northbridge.c
ifneq ($(CONFIG_AGESA_LEGACY_WRAPPER), y)
romstage-y += state_machine.c
ramstage-y += state_machine.c
endif

28
src/northbridge/amd/agesa/family14/northbridge.c
View File

@@ -31,7 +31,6 @@
#include <cpu/x86/lapic.h>
#include <cpu/amd/mtrr.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/agesa/agesa_helper.h>
@@ -580,32 +579,6 @@ static void domain_set_resources(device_t dev)
printk(BIOS_DEBUG, " adsr - leaving this lovely routine.\n");
}
static void domain_enable_resources(device_t dev)
{
#if IS_ENABLED(CONFIG_AGESA_LEGACY_WRAPPER)
/* Must be called after PCI enumeration and resource allocation */
printk(BIOS_DEBUG, "\nFam14h - %s\n", __func__);
#if IS_ENABLED(CONFIG_AMD_SB_CIMX)
if (!acpi_is_wakeup_s3()) {
sb_After_Pci_Init();
sb_Mid_Post_Init();
} else {
sb_After_Pci_Restore_Init();
}
#endif
if (!acpi_is_wakeup_s3()) {
/* Enable MMIO on AMD CPU Address Map Controller */
amd_initcpuio();
agesawrapper_amdinitmid();
}
printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n");
#endif
}
static const char *domain_acpi_name(const struct device *dev)
{
if (dev->path.type == DEVICE_PATH_DOMAIN)
@@ -786,7 +759,6 @@ struct chip_operations northbridge_amd_agesa_family14_ops = {
static struct device_operations pci_domain_ops = {
.read_resources = domain_read_resources,
.set_resources = domain_set_resources,
.enable_resources = domain_enable_resources,
.init = DEVICE_NOOP,
.scan_bus = pci_domain_scan_bus,
.acpi_name = domain_acpi_name,

2
src/northbridge/amd/agesa/family15/Makefile.inc
View File

@@ -17,7 +17,5 @@ romstage-y += dimmSpd.c
ramstage-y += northbridge.c
ifneq ($(CONFIG_AGESA_LEGACY_WRAPPER), y)
romstage-y += state_machine.c
ramstage-y += state_machine.c
endif

19
src/northbridge/amd/agesa/family15/northbridge.c
View File

@@ -36,7 +36,6 @@
#include <Options.h>
#include <Topology.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include "sb_cimx.h"
@@ -633,23 +632,6 @@ static void domain_read_resources(device_t dev)
pci_domain_read_resources(dev);
}
static void domain_enable_resources(device_t dev)
{
#if IS_ENABLED(CONFIG_AGESA_LEGACY_WRAPPER)
/* Must be called after PCI enumeration and resource allocation */
printk(BIOS_DEBUG, "\nFam15 - %s: AmdInitMid.\n", __func__);
#if IS_ENABLED(CONFIG_AMD_SB_CIMX)
sb_After_Pci_Init();
#endif
/* Enable MMIO on AMD CPU Address Map Controller */
amd_initcpuio();
agesawrapper_amdinitmid();
printk(BIOS_DEBUG, " Fam15 - leaving %s.\n", __func__);
#endif
}
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
struct hw_mem_hole_info {
unsigned hole_startk;
@@ -810,7 +792,6 @@ static void f15_pci_domain_scan_bus(device_t dev)
static struct device_operations pci_domain_ops = {
.read_resources = domain_read_resources,
.set_resources = domain_set_resources,
.enable_resources = domain_enable_resources,
.init = DEVICE_NOOP,
.scan_bus = f15_pci_domain_scan_bus,
.ops_pci_bus = pci_bus_default_ops,

2
src/northbridge/amd/agesa/family15tn/Makefile.inc
View File

@@ -18,7 +18,5 @@ romstage-y += dimmSpd.c
ramstage-y += iommu.c
ramstage-y += northbridge.c
ifneq ($(CONFIG_AGESA_LEGACY_WRAPPER), y)
romstage-y += state_machine.c
ramstage-y += state_machine.c
endif

19
src/northbridge/amd/agesa/family15tn/northbridge.c
View File

@@ -37,7 +37,6 @@
#include <Options.h>
#include <Topology.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/agesa/agesa_helper.h>
@@ -629,23 +628,6 @@ static void domain_read_resources(struct device *dev)
pci_domain_read_resources(dev);
}
static void domain_enable_resources(device_t dev)
{
#if IS_ENABLED(CONFIG_AGESA_LEGACY_WRAPPER)
if (acpi_is_wakeup_s3())
agesawrapper_fchs3laterestore();
/* Must be called after PCI enumeration and resource allocation */
if (!acpi_is_wakeup_s3()) {
/* Enable MMIO on AMD CPU Address Map Controller */
amd_initcpuio();
agesawrapper_amdinitmid();
}
printk(BIOS_DEBUG, " ader - leaving %s.\n", __func__);
#endif
}
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
struct hw_mem_hole_info {
unsigned hole_startk;
@@ -800,7 +782,6 @@ static void domain_set_resources(struct device *dev)
static struct device_operations pci_domain_ops = {
.read_resources = domain_read_resources,
.set_resources = domain_set_resources,
.enable_resources = domain_enable_resources,
.init = DEVICE_NOOP,
.scan_bus = pci_domain_scan_bus,
.ops_pci_bus = pci_bus_default_ops,

2
src/northbridge/amd/agesa/family16kb/Makefile.inc
View File

@@ -17,7 +17,5 @@ romstage-y += dimmSpd.c
ramstage-y += northbridge.c
ifneq ($(CONFIG_AGESA_LEGACY_WRAPPER), y)
romstage-y += state_machine.c
ramstage-y += state_machine.c
endif

19
src/northbridge/amd/agesa/family16kb/northbridge.c
View File

@@ -36,7 +36,6 @@
#include <Options.h>
#include <Topology.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/agesa/agesa_helper.h>
@@ -644,23 +643,6 @@ static void domain_read_resources(device_t dev)
pci_domain_read_resources(dev);
}
static void domain_enable_resources(device_t dev)
{
#if IS_ENABLED(CONFIG_AGESA_LEGACY_WRAPPER)
if (acpi_is_wakeup_s3())
agesawrapper_fchs3laterestore();
/* Must be called after PCI enumeration and resource allocation */
if (!acpi_is_wakeup_s3()) {
/* Enable MMIO on AMD CPU Address Map Controller */
amd_initcpuio();
agesawrapper_amdinitmid();
}
printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n");
#endif
}
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
struct hw_mem_hole_info {
unsigned hole_startk;
@@ -816,7 +798,6 @@ static void domain_set_resources(device_t dev)
static struct device_operations pci_domain_ops = {
.read_resources = domain_read_resources,
.set_resources = domain_set_resources,
.enable_resources = domain_enable_resources,
.init = DEVICE_NOOP,
.scan_bus = pci_domain_scan_bus,
.ops_pci_bus = pci_bus_default_ops,

3
src/northbridge/amd/agesa/state_machine.h
View File

@@ -20,8 +20,7 @@
#include <AGESA.h>
#include <AMD.h>
#define HAS_LEGACY_WRAPPER (IS_ENABLED(CONFIG_AGESA_LEGACY_WRAPPER) || \
IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER))
#define HAS_LEGACY_WRAPPER IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER)
/* eventlog */
const char *agesa_struct_name(int state);