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soc/intel/icelake: Add support to enable/disable USB charging in s3/S5

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Change-Id: I0559b8a546f7a67759377c7f51b2faa2280aa797
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/29793
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Aamir Bohra
2018-11-22 16:26:18 +05:30
committed by Subrata Banik
parent a6634f1f78
commit 9df0440c6c
1 changed files with 26 additions and 0 deletions
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26
src/soc/intel/icelake/acpi/globalnvs.asl
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@@ -48,8 +48,34 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
U2WE, 16, // 0x2b - 0x2c USB2 Wake Enable Bitmap
U3WE, 16, // 0x2d - 0x2e USB3 Wake Enable Bitmap
UIOR, 8, // 0x2f - UART debug controller init on S3 resume
S5U0, 8, // 0x30 - Enable USB in S5
S3U0, 8, // 0x31 - Enable USB in S3
/* ChromeOS specific */
Offset (0x100),
#include <vendorcode/google/chromeos/acpi/gnvs.asl>
}
/* Set flag to enable USB charging in S3 */
Method (S3UE)
{
Store (One, \S3U0)
}
/* Set flag to disable USB charging in S3 */
Method (S3UD)
{
Store (Zero, \S3U0)
}
/* Set flag to enable USB charging in S5 */
Method (S5UE)
{
Store (One, \S5U0)
}
/* Set flag to disable USB charging in S5 */
Method (S5UD)
{
Store (Zero, \S5U0)
}