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soc/intel/apollolake: Rename ACPI Base Address and Size Macro

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Rename these two Macros to help use Common Code -
ACPI_PMIO_BASE --> ACPI_BASE_ADDRESS
ACPI_PMIO_SIZE --> ACPI_BASE_SIZE

Change-Id: I21125b7206c241692cfdf1cdb10b8b3dee62b24a
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20038
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Barnali Sarkar
2017-06-05 20:01:14 +05:30
committed by Aaron Durbin
parent f004f66ca7
commit 9e55ff6a87
9 changed files with 58 additions and 58 deletions
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4
src/soc/intel/apollolake/bootblock/bootblock.c
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@@ -56,7 +56,7 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
/* Decode the ACPI I/O port range for early firmware verification.*/
dev = PCH_DEV_PMC;
pci_write_config16(dev, PCI_BASE_ADDRESS_4, ACPI_PMIO_BASE);
pci_write_config16(dev, PCI_BASE_ADDRESS_4, ACPI_BASE_ADDRESS);
pci_write_config16(dev, PCI_COMMAND,
PCI_COMMAND_IO | PCI_COMMAND_MASTER);
@@ -75,7 +75,7 @@ static void enable_pmcbar(void)
pci_write_config32(pmc, PCI_BASE_ADDRESS_1, 0); /* 64-bit BAR */
pci_write_config32(pmc, PCI_BASE_ADDRESS_2, PMC_BAR1);
pci_write_config32(pmc, PCI_BASE_ADDRESS_3, 0); /* 64-bit BAR */
pci_write_config16(pmc, PCI_BASE_ADDRESS_4, ACPI_PMIO_BASE);
pci_write_config16(pmc, PCI_BASE_ADDRESS_4, ACPI_BASE_ADDRESS);
pci_write_config16(pmc, PCI_COMMAND,
PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER);