intel car: Remove guard on XIP_ROM_SIZE

These guards have been removed starting with model_206ax.

Change-Id: Id63034ec4080e37eee2c120aa1f1ef604db5b203
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15758
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

src/cpu/intel/car/cache_as_ram.inc

@@ -225,8 +225,6 @@ clear_fixed_var_mtrr_out:
 	simplemask CacheSize, 0
 	wrmsr
 
-#if CONFIG_XIP_ROM_SIZE
-
 	/*
 	 * Enable write base caching so we can do execute in place (XIP)
 	 * on the flash ROM.
@@ -246,7 +244,6 @@ clear_fixed_var_mtrr_out:
 	movl	$0x0000000f, %edx
 	movl	$(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
 	wrmsr
-#endif /* CONFIG_XIP_ROM_SIZE */
 
 	/* Enable cache. */
 	movl	%cr0, %eax

src/cpu/intel/car/cache_as_ram_ht.inc

@@ -302,7 +302,6 @@ no_msr_11e:
 
 	post_code(0x2d)
 
-#if CONFIG_XIP_ROM_SIZE
 	/* Enable cache for our code in Flash because we do XIP here */
 	movl	$MTRR_PHYS_BASE(1), %ecx
 	xorl	%edx, %edx
@@ -319,7 +318,6 @@ no_msr_11e:
 	rdmsr
 	movl	$(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
 	wrmsr
-#endif /* CONFIG_XIP_ROM_SIZE */
 
 	/* Enable cache. */
 	movl	%cr0, %eax

src/cpu/intel/model_6ex/cache_as_ram.inc

@@ -96,7 +96,6 @@ clear_mtrrs:
 	orl	$CR0_CacheDisable, %eax
 	movl	%eax, %cr0
 
-#if CONFIG_XIP_ROM_SIZE
 	/* Enable cache for our code in Flash because we do XIP here */
 	movl	$MTRR_PHYS_BASE(1), %ecx
 	xorl	%edx, %edx
@@ -113,7 +112,6 @@ clear_mtrrs:
 	movl	$CPU_PHYSMASK_HI, %edx
 	movl	$(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
 	wrmsr
-#endif /* CONFIG_XIP_ROM_SIZE */
 
 	/* Enable cache. */
 	movl	%cr0, %eax