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Intel CPUs: execute microcode update only once per core

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Early HT-enabled CPUs do not serialize microcode updates within a core.
Solve this by running microcode updates on the thread with the smallest
lapic ID of a core only.

Also set MTRRs once per core only.

Change-Id: I6a3cc9ecec2d8e0caed29605a9b19ec35a817620
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1142
Tested-by: build bot (Jenkins)
Reviewed-by: Sven Schnelle <svens@stackframe.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Kyösti Mälkki
2012-06-27 16:14:49 +03:00
committed by Sven Schnelle
parent ac6e3172ff
commit 9ed1456eff
5 changed files with 46 additions and 12 deletions
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21
src/cpu/intel/hyperthreading/intel_sibling.c
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@ -14,6 +14,27 @@
static int first_time = 1;
static int disable_siblings = !CONFIG_LOGICAL_CPUS;
/* Return true if running thread does not have the smallest lapic ID
* within a CPU core.
*/
int intel_ht_sibling(void)
{
unsigned int core_ids, apic_ids, threads;
apic_ids = 1;
if (cpuid_eax(0) >= 1)
apic_ids = (cpuid_ebx(1) >> 16) & 0xff;
if (apic_ids < 1)
apic_ids = 1;
core_ids = 1;
if (cpuid_eax(0) >= 4)
core_ids += (cpuid_eax(4) >> 26) & 0x3f;
threads = (apic_ids / core_ids);
return !!(lapicid() & (threads-1));
}
void intel_sibling_init(device_t cpu)
{
unsigned i, siblings;