Intel CPUs: execute microcode update only once per core

Early HT-enabled CPUs do not serialize microcode updates within a core.
Solve this by running microcode updates on the thread with the smallest
lapic ID of a core only.

Also set MTRRs once per core only.

Change-Id: I6a3cc9ecec2d8e0caed29605a9b19ec35a817620
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1142
Tested-by: build bot (Jenkins)
Reviewed-by: Sven Schnelle <svens@stackframe.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/cpu/intel/model_f4x/model_f4x_init.c

@@ -39,11 +39,15 @@ static void model_f4x_init(device_t cpu)
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs();
-	x86_mtrr_check();
 
-	/* Update the microcode */
-	intel_update_microcode(microcode_updates);
+	if (!intel_ht_sibling()) {
+		/* MTRRs are shared between threads */
+		x86_setup_mtrrs();
+		x86_mtrr_check();
+
+		/* Update the microcode */
+		intel_update_microcode(microcode_updates);
+	}
 
 	/* Enable the local cpu apics */
 	setup_lapic();