nb/intel/sandybridge/romstage: Read fuse bits for max MEM Clk

Instead of hardcoding the maximum supported DDR frequency to
800Mhz (DDR3-1600), read the fuse bits that encode this information.

Test system:
 * Intel IvyBridge
 * Gigabyte GA-B75M-D3H

Change-Id: I515a2695a490f16aeb946bfaf3a1e860c607cba9
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13487
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

src/include/device/dram/ddr3.h

@@ -33,8 +33,10 @@
  * These values are in 1/256 ns units.
  * @{
  */
+#define TCK_1333MHZ     192
+#define TCK_1200MHZ     212
 #define TCK_1066MHZ     240
-#define TCK_933MHZ	275
+#define TCK_933MHZ      275
 #define TCK_800MHZ      320
 #define TCK_666MHZ      384
 #define TCK_533MHZ      480