vendorcode/intel/fsp: Add Raptor Lake FSP headers for FSP v3257_00_40
The headers added are generated as per FSP v3257_00_40. In the future, when Alder Lake and Raptor Lake fsp align, Raptor Lake fsp headers can be deleted and Raptor Lake soc will also use headers from alderlake/ folder. BUG=b:238791453 BRANCH=firmware-brya-14505.B TEST=none Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: If8fd6700f0afed7e2bd5d73a95407dbfd3e88abd Reviewed-on: https://review.coreboot.org/c/coreboot/+/65803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This commit is contained in:
Bora Guvendik
Felix Held
parent
8f296038e5
commit
9f45f06e0e
@ -1105,7 +1105,43 @@ typedef struct {
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/** Offset 0x02A2 - Reserved
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/** Offset 0x02A2 - Reserved
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**/
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**/
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UINT8 Reserved10[111];
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UINT8 Reserved10;
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/** Offset 0x02A3 - Reserved
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**/
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UINT8 Reserved11;
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/** Offset 0x02A4 - Reserved
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**/
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UINT16 Reserved12;
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/** Offset 0x02A6 - Reserved
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**/
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UINT16 Reserved13;
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/** Offset 0x02A8 - Reserved
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**/
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UINT8 Reserved14[4];
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/** Offset 0x02AC - Reserved
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**/
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UINT8 Reserved15;
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/** Offset 0x02AD - Reserved
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**/
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UINT8 Reserved16;
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/** Offset 0x02AE - Reserved
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**/
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UINT8 Reserved17;
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/** Offset 0x02AF - Reserved
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**/
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UINT8 Reserved18;
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/** Offset 0x02B0 - Reserved
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**/
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UINT8 Reserved19[97];
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/** Offset 0x0311 - Enable Gt CLOS
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/** Offset 0x0311 - Enable Gt CLOS
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0(Default)=Disable, 1=Enable
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0(Default)=Disable, 1=Enable
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@ -1275,7 +1311,51 @@ typedef struct {
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/** Offset 0x037B - Reserved
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/** Offset 0x037B - Reserved
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**/
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**/
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UINT8 Reserved11[54];
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UINT8 Reserved20[8];
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/** Offset 0x0383 - Reserved
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**/
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UINT8 Reserved21[8];
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/** Offset 0x038B - Reserved
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**/
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UINT8 Reserved22;
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/** Offset 0x038C - Reserved
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**/
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UINT8 Reserved23;
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/** Offset 0x038D - Reserved
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**/
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UINT8 Reserved24;
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/** Offset 0x038E - Reserved
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**/
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UINT8 Reserved25[8];
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/** Offset 0x0396 - Reserved
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**/
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UINT8 Reserved26;
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/** Offset 0x0397 - Reserved
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**/
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UINT8 Reserved27;
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/** Offset 0x0398 - Reserved
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**/
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UINT8 Reserved28[8];
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/** Offset 0x03A0 - Reserved
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**/
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UINT8 Reserved29[8];
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/** Offset 0x03A8 - Reserved
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**/
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UINT8 Reserved30;
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/** Offset 0x03A9 - Reserved
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**/
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UINT8 Reserved31[8];
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/** Offset 0x03B1 - DMI ASPM Control Configuration:{Combo
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/** Offset 0x03B1 - DMI ASPM Control Configuration:{Combo
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Set ASPM Control configuration
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Set ASPM Control configuration
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@ -1432,7 +1512,7 @@ typedef struct {
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/** Offset 0x03CD - Reserved
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/** Offset 0x03CD - Reserved
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**/
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**/
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UINT8 Reserved12;
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UINT8 Reserved32;
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/** Offset 0x03CE - Ring Downbin
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/** Offset 0x03CE - Ring Downbin
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Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always
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Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always
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@ -1455,7 +1535,7 @@ typedef struct {
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/** Offset 0x03D1 - Reserved
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/** Offset 0x03D1 - Reserved
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**/
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**/
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UINT8 Reserved13;
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UINT8 Reserved33;
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/** Offset 0x03D2 - Ring voltage override
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/** Offset 0x03D2 - Ring voltage override
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The ring voltage override which is applied to the entire range of cpu ring frequencies.
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The ring voltage override which is applied to the entire range of cpu ring frequencies.
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@ -1501,7 +1581,47 @@ typedef struct {
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/** Offset 0x03DC - Reserved
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/** Offset 0x03DC - Reserved
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**/
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**/
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UINT8 Reserved14[24];
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UINT8 Reserved34;
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/** Offset 0x03DD - Reserved
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**/
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UINT8 Reserved35;
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/** Offset 0x03DE - Reserved
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**/
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UINT16 Reserved36;
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/** Offset 0x03E0 - Reserved
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**/
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UINT16 Reserved37;
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/** Offset 0x03E2 - Reserved
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**/
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UINT16 Reserved38;
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/** Offset 0x03E4 - Reserved
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**/
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UINT16 Reserved39[4];
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/** Offset 0x03EC - Reserved
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**/
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UINT8 Reserved40[4];
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/** Offset 0x03F0 - Reserved
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**/
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UINT8 Reserved41;
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/** Offset 0x03F1 - Reserved
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**/
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UINT8 Reserved42;
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/** Offset 0x03F2 - Reserved
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**/
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UINT8 Reserved43;
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/** Offset 0x03F3 - Reserved
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**/
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UINT8 Reserved44;
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/** Offset 0x03F4 - Core VF Point Offset Mode
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/** Offset 0x03F4 - Core VF Point Offset Mode
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Selects Core Voltage & Frequency Offset mode between Legacy and Selection modes.
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Selects Core Voltage & Frequency Offset mode between Legacy and Selection modes.
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@ -1513,7 +1633,7 @@ typedef struct {
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/** Offset 0x03F5 - Reserved
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/** Offset 0x03F5 - Reserved
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**/
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**/
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UINT8 Reserved15;
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UINT8 Reserved45[1];
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/** Offset 0x03F6 - Core VF Point Offset
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/** Offset 0x03F6 - Core VF Point Offset
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Array used to specifies the Core Voltage Offset applied to the each selected VF
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Array used to specifies the Core Voltage Offset applied to the each selected VF
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@ -1540,7 +1660,15 @@ typedef struct {
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/** Offset 0x0433 - Reserved
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/** Offset 0x0433 - Reserved
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**/
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**/
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UINT8 Reserved16[25];
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UINT8 Reserved46;
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/** Offset 0x0434 - Reserved
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**/
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UINT16 Reserved47[8];
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/** Offset 0x0444 - Reserved
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**/
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UINT8 Reserved48[8];
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/** Offset 0x044C - Per Core Max Ratio override
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/** Offset 0x044C - Per Core Max Ratio override
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Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new
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Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new
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@ -1556,7 +1684,11 @@ typedef struct {
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/** Offset 0x0455 - Reserved
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/** Offset 0x0455 - Reserved
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**/
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**/
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UINT8 Reserved17[5];
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UINT8 Reserved49[4];
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/** Offset 0x0459 - Reserved
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**/
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UINT8 Reserved50;
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/** Offset 0x045A - Pvd Ratio Threshold
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/** Offset 0x045A - Pvd Ratio Threshold
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Select PVD Ratio Threshold Value from Range 1 to 40. 0 - Auto/Default.
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Select PVD Ratio Threshold Value from Range 1 to 40. 0 - Auto/Default.
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@ -1578,7 +1710,23 @@ typedef struct {
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/** Offset 0x045D - Reserved
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/** Offset 0x045D - Reserved
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**/
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**/
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UINT8 Reserved18[62];
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UINT8 Reserved51;
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/** Offset 0x045E - Reserved
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**/
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UINT16 Reserved52[15];
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/** Offset 0x047C - Reserved
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**/
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UINT8 Reserved53[15];
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/** Offset 0x048B - Reserved
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**/
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UINT8 Reserved54[15];
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/** Offset 0x049A - Reserved
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**/
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UINT8 Reserved55;
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/** Offset 0x049B - BCLK Frequency Source
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/** Offset 0x049B - BCLK Frequency Source
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Clock source of BCLK OC frequency, <b>1:CPU BCLK</b>, 2:PCH BCLK, 3:External CLK
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Clock source of BCLK OC frequency, <b>1:CPU BCLK</b>, 2:PCH BCLK, 3:External CLK
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/** Offset 0x049D - Reserved
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/** Offset 0x049D - Reserved
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**/
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**/
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UINT8 Reserved19[3];
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UINT8 Reserved56[3];
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/** Offset 0x04A0 - CPU BCLK OC Frequency
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/** Offset 0x04A0 - CPU BCLK OC Frequency
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CPU BCLK OC Frequency in 10KHz units increasing. Value 9800 (10KHz) = 98MHz <b>0
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CPU BCLK OC Frequency in 10KHz units increasing. Value 9800 (10KHz) = 98MHz <b>0
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/** Offset 0x04A4 - Reserved
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/** Offset 0x04A4 - Reserved
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**/
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**/
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UINT8 Reserved20[40];
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UINT32 Reserved57;
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/** Offset 0x04A8 - Reserved
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**/
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UINT32 Reserved58;
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/** Offset 0x04AC - Reserved
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UINT8 Reserved59;
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/** Offset 0x04AD - Reserved
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**/
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UINT8 Reserved60;
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/** Offset 0x04AE - Reserved
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**/
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UINT8 Reserved61;
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/** Offset 0x04AF - Reserved
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**/
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UINT8 Reserved62;
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/** Offset 0x04B0 - Reserved
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**/
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UINT16 Reserved63;
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/** Offset 0x04B2 - Reserved
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**/
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UINT8 Reserved64;
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/** Offset 0x04B3 - Reserved
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**/
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UINT8 Reserved65;
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/** Offset 0x04B4 - Reserved
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**/
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UINT16 Reserved66;
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/** Offset 0x04B6 - Reserved
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UINT8 Reserved67;
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/** Offset 0x04B7 - Reserved
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UINT8 Reserved68;
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/** Offset 0x04B8 - Reserved
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**/
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UINT8 Reserved69;
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/** Offset 0x04B9 - Reserved
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**/
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UINT8 Reserved70;
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/** Offset 0x04BA - Reserved
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**/
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UINT8 Reserved71;
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/** Offset 0x04BB - Reserved
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**/
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UINT8 Reserved72;
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/** Offset 0x04BC - Reserved
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UINT8 Reserved73;
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/** Offset 0x04BD - Reserved
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**/
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UINT8 Reserved74[3];
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/** Offset 0x04C0 - Reserved
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**/
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UINT32 Reserved75;
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/** Offset 0x04C4 - Reserved
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**/
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UINT8 Reserved76;
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/** Offset 0x04C5 - Reserved
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**/
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UINT8 Reserved77;
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/** Offset 0x04C6 - Reserved
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**/
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UINT8 Reserved78[6];
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/** Offset 0x04CC - BiosGuard
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/** Offset 0x04CC - BiosGuard
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Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable
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Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable
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/** Offset 0x04CF - Reserved
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/** Offset 0x04CF - Reserved
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**/
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**/
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UINT8 Reserved21;
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UINT8 Reserved79;
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/** Offset 0x04D0 - PrmrrSize
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/** Offset 0x04D0 - PrmrrSize
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Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable
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Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable
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/** Offset 0x0509 - Reserved
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/** Offset 0x0509 - Reserved
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**/
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**/
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UINT8 Reserved22[32];
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UINT8 Reserved80[32];
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/** Offset 0x0529 - Enable PCH HSIO PCIE Rx Set Ctle
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/** Offset 0x0529 - Enable PCH HSIO PCIE Rx Set Ctle
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Enable PCH PCIe Gen 3 Set CTLE Value.
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Enable PCH PCIe Gen 3 Set CTLE Value.
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@ -1876,7 +2108,7 @@ typedef struct {
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/** Offset 0x0745 - Reserved
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/** Offset 0x0745 - Reserved
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**/
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**/
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UINT8 Reserved23;
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UINT8 Reserved81;
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/** Offset 0x0746 - SMBUS Base Address
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/** Offset 0x0746 - SMBUS Base Address
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SMBUS Base Address (IO space).
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SMBUS Base Address (IO space).
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@ -1897,7 +2129,7 @@ typedef struct {
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/** Offset 0x075B - Reserved
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/** Offset 0x075B - Reserved
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**/
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**/
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UINT8 Reserved24[14];
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UINT8 Reserved82[14];
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/** Offset 0x0769 - ClkReq-to-ClkSrc mapping
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/** Offset 0x0769 - ClkReq-to-ClkSrc mapping
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Number of ClkReq signal assigned to ClkSrc
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Number of ClkReq signal assigned to ClkSrc
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@ -1906,7 +2138,19 @@ typedef struct {
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/** Offset 0x077B - Reserved
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/** Offset 0x077B - Reserved
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**/
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**/
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UINT8 Reserved25[93];
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UINT8 Reserved83[14];
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/** Offset 0x0789 - Reserved
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**/
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UINT8 Reserved84[3];
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/** Offset 0x078C - Reserved
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**/
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UINT32 Reserved85[18];
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/** Offset 0x07D4 - Reserved
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**/
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UINT32 Reserved86;
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/** Offset 0x07D8 - Enable PCIE RP Mask
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/** Offset 0x07D8 - Enable PCIE RP Mask
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Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
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Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
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@ -1968,7 +2212,7 @@ typedef struct {
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/** Offset 0x07F5 - Reserved
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/** Offset 0x07F5 - Reserved
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**/
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**/
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UINT8 Reserved26[3];
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UINT8 Reserved87[3];
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/** Offset 0x07F8 - DMIC<N> Data Pin Muxing
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/** Offset 0x07F8 - DMIC<N> Data Pin Muxing
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Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_*
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Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_*
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@ -2030,7 +2274,7 @@ typedef struct {
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/** Offset 0x0811 - Reserved
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/** Offset 0x0811 - Reserved
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**/
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**/
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UINT8 Reserved27[3];
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UINT8 Reserved88[3];
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/** Offset 0x0814 - Serial Io Uart Debug BaudRate
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/** Offset 0x0814 - Serial Io Uart Debug BaudRate
|
||||||
Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600,
|
Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600,
|
||||||
@ -2058,7 +2302,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x081B - Reserved
|
/** Offset 0x081B - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved28;
|
UINT8 Reserved89;
|
||||||
|
|
||||||
/** Offset 0x081C - Serial Io Uart Debug Mmio Base
|
/** Offset 0x081C - Serial Io Uart Debug Mmio Base
|
||||||
Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode
|
Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode
|
||||||
@ -2378,7 +2622,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x0854 - Reserved
|
/** Offset 0x0854 - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved29;
|
UINT8 Reserved90;
|
||||||
|
|
||||||
/** Offset 0x0855 - Extern Therm Status
|
/** Offset 0x0855 - Extern Therm Status
|
||||||
Enables/Disable Extern Therm Status
|
Enables/Disable Extern Therm Status
|
||||||
@ -2418,7 +2662,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x085B - Reserved
|
/** Offset 0x085B - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved30;
|
UINT8 Reserved91;
|
||||||
|
|
||||||
/** Offset 0x085C - Exit On Failure (MRC)
|
/** Offset 0x085C - Exit On Failure (MRC)
|
||||||
Enables/Disable Exit On Failure (MRC)
|
Enables/Disable Exit On Failure (MRC)
|
||||||
@ -2524,7 +2768,11 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x086D - Reserved
|
/** Offset 0x086D - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved31[2];
|
UINT8 Reserved92;
|
||||||
|
|
||||||
|
/** Offset 0x086E - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved93;
|
||||||
|
|
||||||
/** Offset 0x086F - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP
|
/** Offset 0x086F - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP
|
||||||
Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP
|
Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP
|
||||||
@ -2583,7 +2831,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x087E - Reserved
|
/** Offset 0x087E - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved32;
|
UINT8 Reserved94;
|
||||||
|
|
||||||
/** Offset 0x087F - Idle Energy Mc0Ch0Dimm0
|
/** Offset 0x087F - Idle Energy Mc0Ch0Dimm0
|
||||||
Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
|
Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
|
||||||
@ -2793,7 +3041,11 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x08A8 - Reserved
|
/** Offset 0x08A8 - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved33[2];
|
UINT8 Reserved95;
|
||||||
|
|
||||||
|
/** Offset 0x08A9 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved96;
|
||||||
|
|
||||||
/** Offset 0x08AA - Rapl Power Floor Ch0
|
/** Offset 0x08AA - Rapl Power Floor Ch0
|
||||||
Power budget ,range[255;0],(0= 5.3W Def)
|
Power budget ,range[255;0],(0= 5.3W Def)
|
||||||
@ -2825,7 +3077,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x08AF - Reserved
|
/** Offset 0x08AF - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved34;
|
UINT8 Reserved97;
|
||||||
|
|
||||||
/** Offset 0x08B0 - User Manual Threshold
|
/** Offset 0x08B0 - User Manual Threshold
|
||||||
Disabled: Predefined threshold will be used.\n
|
Disabled: Predefined threshold will be used.\n
|
||||||
@ -2899,7 +3151,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x08BB - Reserved
|
/** Offset 0x08BB - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved35;
|
UINT8 Reserved98;
|
||||||
|
|
||||||
/** Offset 0x08BC - Post Code Output Port
|
/** Offset 0x08BC - Post Code Output Port
|
||||||
This option configures Post Code Output Port
|
This option configures Post Code Output Port
|
||||||
@ -2926,7 +3178,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x08C1 - Reserved
|
/** Offset 0x08C1 - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved36[3];
|
UINT8 Reserved99[3];
|
||||||
|
|
||||||
/** Offset 0x08C4 - BCLK RFI Frequency
|
/** Offset 0x08C4 - BCLK RFI Frequency
|
||||||
Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz <b>0 - No
|
Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz <b>0 - No
|
||||||
@ -2976,7 +3228,15 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x08DB - Reserved
|
/** Offset 0x08DB - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved37[3];
|
UINT8 Reserved100;
|
||||||
|
|
||||||
|
/** Offset 0x08DC - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved101;
|
||||||
|
|
||||||
|
/** Offset 0x08DD - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved102;
|
||||||
|
|
||||||
/** Offset 0x08DE - REFRESH_PANIC_WM
|
/** Offset 0x08DE - REFRESH_PANIC_WM
|
||||||
DEPRECATED
|
DEPRECATED
|
||||||
@ -3002,7 +3262,39 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x08E2 - Reserved
|
/** Offset 0x08E2 - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved38[9];
|
UINT8 Reserved103;
|
||||||
|
|
||||||
|
/** Offset 0x08E3 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved104;
|
||||||
|
|
||||||
|
/** Offset 0x08E4 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved105;
|
||||||
|
|
||||||
|
/** Offset 0x08E5 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved106;
|
||||||
|
|
||||||
|
/** Offset 0x08E6 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved107;
|
||||||
|
|
||||||
|
/** Offset 0x08E7 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved108;
|
||||||
|
|
||||||
|
/** Offset 0x08E8 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved109;
|
||||||
|
|
||||||
|
/** Offset 0x08E9 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved110;
|
||||||
|
|
||||||
|
/** Offset 0x08EA - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved111;
|
||||||
|
|
||||||
/** Offset 0x08EB - Skip external display device scanning
|
/** Offset 0x08EB - Skip external display device scanning
|
||||||
Enable: Do not scan for external display device, Disable (Default): Scan external
|
Enable: Do not scan for external display device, Disable (Default): Scan external
|
||||||
@ -3025,7 +3317,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x08EE - Reserved
|
/** Offset 0x08EE - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved39;
|
UINT8 Reserved112;
|
||||||
|
|
||||||
/** Offset 0x08EF - Panel Power Enable
|
/** Offset 0x08EF - Panel Power Enable
|
||||||
Control for enabling/disabling VDD force bit (Required only for early enabling of
|
Control for enabling/disabling VDD force bit (Required only for early enabling of
|
||||||
@ -3042,7 +3334,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x08F1 - Reserved
|
/** Offset 0x08F1 - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved40[3];
|
UINT8 Reserved113[3];
|
||||||
|
|
||||||
/** Offset 0x08F4 - PMR Size
|
/** Offset 0x08F4 - PMR Size
|
||||||
Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot
|
Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot
|
||||||
@ -3056,7 +3348,27 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x08F9 - Reserved
|
/** Offset 0x08F9 - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved41[95];
|
UINT8 Reserved114;
|
||||||
|
|
||||||
|
/** Offset 0x08FA - Reserved
|
||||||
|
**/
|
||||||
|
UINT16 Reserved115;
|
||||||
|
|
||||||
|
/** Offset 0x08FC - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved116;
|
||||||
|
|
||||||
|
/** Offset 0x08FD - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved117;
|
||||||
|
|
||||||
|
/** Offset 0x08FE - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved118[89];
|
||||||
|
|
||||||
|
/** Offset 0x0957 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved119;
|
||||||
|
|
||||||
/** Offset 0x0958 - TotalFlashSize
|
/** Offset 0x0958 - TotalFlashSize
|
||||||
Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable
|
Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable
|
||||||
@ -3072,7 +3384,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x095C - Reserved
|
/** Offset 0x095C - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved42[12];
|
UINT8 Reserved120[12];
|
||||||
|
|
||||||
/** Offset 0x0968 - Smbus dynamic power gating
|
/** Offset 0x0968 - Smbus dynamic power gating
|
||||||
Disable or Enable Smbus dynamic power gating.
|
Disable or Enable Smbus dynamic power gating.
|
||||||
@ -3138,7 +3450,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x0972 - Reserved
|
/** Offset 0x0972 - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved43[2];
|
UINT8 Reserved121[2];
|
||||||
|
|
||||||
/** Offset 0x0974 - Hybrid Graphics GPIO information for PEG 1
|
/** Offset 0x0974 - Hybrid Graphics GPIO information for PEG 1
|
||||||
Hybrid Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs
|
Hybrid Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs
|
||||||
@ -3175,7 +3487,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x0A97 - Reserved
|
/** Offset 0x0A97 - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved44;
|
UINT8 Reserved122;
|
||||||
|
|
||||||
/** Offset 0x0A98 - SerialIoUartDebugRxPinMux - FSPT
|
/** Offset 0x0A98 - SerialIoUartDebugRxPinMux - FSPT
|
||||||
Select RX pin muxing for SerialIo UART used for debug
|
Select RX pin muxing for SerialIo UART used for debug
|
||||||
@ -3201,7 +3513,183 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x0AA8 - Reserved
|
/** Offset 0x0AA8 - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved45[130];
|
UINT8 Reserved123;
|
||||||
|
|
||||||
|
/** Offset 0x0AA9 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved124;
|
||||||
|
|
||||||
|
/** Offset 0x0AAA - Reserved
|
||||||
|
**/
|
||||||
|
UINT16 Reserved125;
|
||||||
|
|
||||||
|
/** Offset 0x0AAC - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved126[4];
|
||||||
|
|
||||||
|
/** Offset 0x0AB0 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved127;
|
||||||
|
|
||||||
|
/** Offset 0x0AB1 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved128;
|
||||||
|
|
||||||
|
/** Offset 0x0AB2 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved129[6];
|
||||||
|
|
||||||
|
/** Offset 0x0AB8 - Reserved
|
||||||
|
**/
|
||||||
|
UINT64 Reserved130;
|
||||||
|
|
||||||
|
/** Offset 0x0AC0 - Reserved
|
||||||
|
**/
|
||||||
|
UINT64 Reserved131;
|
||||||
|
|
||||||
|
/** Offset 0x0AC8 - Reserved
|
||||||
|
**/
|
||||||
|
UINT32 Reserved132;
|
||||||
|
|
||||||
|
/** Offset 0x0ACC - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved133[8];
|
||||||
|
|
||||||
|
/** Offset 0x0AD4 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved134;
|
||||||
|
|
||||||
|
/** Offset 0x0AD5 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved135[3];
|
||||||
|
|
||||||
|
/** Offset 0x0AD8 - Reserved
|
||||||
|
**/
|
||||||
|
UINT32 Reserved136;
|
||||||
|
|
||||||
|
/** Offset 0x0ADC - Reserved
|
||||||
|
**/
|
||||||
|
UINT32 Reserved137;
|
||||||
|
|
||||||
|
/** Offset 0x0AE0 - Reserved
|
||||||
|
**/
|
||||||
|
UINT16 Reserved138;
|
||||||
|
|
||||||
|
/** Offset 0x0AE2 - Reserved
|
||||||
|
**/
|
||||||
|
UINT16 Reserved139;
|
||||||
|
|
||||||
|
/** Offset 0x0AE4 - Reserved
|
||||||
|
**/
|
||||||
|
UINT16 Reserved140;
|
||||||
|
|
||||||
|
/** Offset 0x0AE6 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved141;
|
||||||
|
|
||||||
|
/** Offset 0x0AE7 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved142;
|
||||||
|
|
||||||
|
/** Offset 0x0AE8 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved143;
|
||||||
|
|
||||||
|
/** Offset 0x0AE9 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved144;
|
||||||
|
|
||||||
|
/** Offset 0x0AEA - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved145;
|
||||||
|
|
||||||
|
/** Offset 0x0AEB - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved146[5];
|
||||||
|
|
||||||
|
/** Offset 0x0AF0 - Reserved
|
||||||
|
**/
|
||||||
|
UINT64 Reserved147;
|
||||||
|
|
||||||
|
/** Offset 0x0AF8 - Reserved
|
||||||
|
**/
|
||||||
|
UINT64 Reserved148;
|
||||||
|
|
||||||
|
/** Offset 0x0B00 - Reserved
|
||||||
|
**/
|
||||||
|
UINT32 Reserved149;
|
||||||
|
|
||||||
|
/** Offset 0x0B04 - Reserved
|
||||||
|
**/
|
||||||
|
UINT16 Reserved150;
|
||||||
|
|
||||||
|
/** Offset 0x0B06 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved151;
|
||||||
|
|
||||||
|
/** Offset 0x0B07 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved152;
|
||||||
|
|
||||||
|
/** Offset 0x0B08 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved153;
|
||||||
|
|
||||||
|
/** Offset 0x0B09 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved154;
|
||||||
|
|
||||||
|
/** Offset 0x0B0A - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved155;
|
||||||
|
|
||||||
|
/** Offset 0x0B0B - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved156;
|
||||||
|
|
||||||
|
/** Offset 0x0B0C - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved157;
|
||||||
|
|
||||||
|
/** Offset 0x0B0D - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved158;
|
||||||
|
|
||||||
|
/** Offset 0x0B0E - Reserved
|
||||||
|
**/
|
||||||
|
UINT16 Reserved159;
|
||||||
|
|
||||||
|
/** Offset 0x0B10 - Reserved
|
||||||
|
**/
|
||||||
|
UINT16 Reserved160;
|
||||||
|
|
||||||
|
/** Offset 0x0B12 - Reserved
|
||||||
|
**/
|
||||||
|
UINT16 Reserved161;
|
||||||
|
|
||||||
|
/** Offset 0x0B14 - Reserved
|
||||||
|
**/
|
||||||
|
UINT16 Reserved162;
|
||||||
|
|
||||||
|
/** Offset 0x0B16 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved163[8];
|
||||||
|
|
||||||
|
/** Offset 0x0B1E - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved164[8];
|
||||||
|
|
||||||
|
/** Offset 0x0B26 - Reserved
|
||||||
|
**/
|
||||||
|
UINT16 Reserved165;
|
||||||
|
|
||||||
|
/** Offset 0x0B28 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved166;
|
||||||
|
|
||||||
|
/** Offset 0x0B29 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved167;
|
||||||
|
|
||||||
/** Offset 0x0B2A - LP5 Bank Mode
|
/** Offset 0x0B2A - LP5 Bank Mode
|
||||||
LP5 Bank Mode. 0: Auto, 1: 8 Bank Mode, 2: 16 Bank Mode, 3: BG Mode, default is 0
|
LP5 Bank Mode. 0: Auto, 1: 8 Bank Mode, 2: 16 Bank Mode, 3: BG Mode, default is 0
|
||||||
@ -3211,7 +3699,19 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x0B2B - Reserved
|
/** Offset 0x0B2B - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved46[13];
|
UINT8 Reserved168;
|
||||||
|
|
||||||
|
/** Offset 0x0B2C - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved169;
|
||||||
|
|
||||||
|
/** Offset 0x0B2D - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved170[5];
|
||||||
|
|
||||||
|
/** Offset 0x0B32 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved171[6];
|
||||||
} FSP_M_CONFIG;
|
} FSP_M_CONFIG;
|
||||||
|
|
||||||
/** Fsp M UPD Configuration
|
/** Fsp M UPD Configuration
|
||||||
|
|||||||
@ -163,7 +163,11 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x0072 - Reserved
|
/** Offset 0x0072 - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved1[34];
|
UINT8 Reserved1[2];
|
||||||
|
|
||||||
|
/** Offset 0x0074 - Reserved
|
||||||
|
**/
|
||||||
|
UINT32 Reserved2[8];
|
||||||
|
|
||||||
/** Offset 0x0094 - Enable USB2 ports
|
/** Offset 0x0094 - Enable USB2 ports
|
||||||
Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for
|
Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for
|
||||||
@ -185,7 +189,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x00AF - Reserved
|
/** Offset 0x00AF - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved2;
|
UINT8 Reserved3;
|
||||||
|
|
||||||
/** Offset 0x00B0 - Address of PCH_DEVICE_INTERRUPT_CONFIG table.
|
/** Offset 0x00B0 - Address of PCH_DEVICE_INTERRUPT_CONFIG table.
|
||||||
The address of the table of PCH_DEVICE_INTERRUPT_CONFIG.
|
The address of the table of PCH_DEVICE_INTERRUPT_CONFIG.
|
||||||
@ -233,7 +237,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x00C2 - Reserved
|
/** Offset 0x00C2 - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved3[2];
|
UINT8 Reserved4[2];
|
||||||
|
|
||||||
/** Offset 0x00C4 - PCH HDA Verb Table Pointer
|
/** Offset 0x00C4 - PCH HDA Verb Table Pointer
|
||||||
Pointer to Array of pointers to Verb Table.
|
Pointer to Array of pointers to Verb Table.
|
||||||
@ -301,7 +305,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x010A - Reserved
|
/** Offset 0x010A - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved4[2];
|
UINT8 Reserved5[2];
|
||||||
|
|
||||||
/** Offset 0x010C - Default BaudRate for each Serial IO UART
|
/** Offset 0x010C - Default BaudRate for each Serial IO UART
|
||||||
Set default BaudRate Supported from 0 - default to 6000000
|
Set default BaudRate Supported from 0 - default to 6000000
|
||||||
@ -341,7 +345,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x0152 - Reserved
|
/** Offset 0x0152 - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved5[2];
|
UINT8 Reserved6[2];
|
||||||
|
|
||||||
/** Offset 0x0154 - SerialIoUartRtsPinMuxPolicy
|
/** Offset 0x0154 - SerialIoUartRtsPinMuxPolicy
|
||||||
Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
|
Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
|
||||||
@ -656,7 +660,15 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x038F - Reserved
|
/** Offset 0x038F - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved6[9];
|
UINT8 Reserved7;
|
||||||
|
|
||||||
|
/** Offset 0x0390 - Reserved
|
||||||
|
**/
|
||||||
|
UINT32 Reserved8;
|
||||||
|
|
||||||
|
/** Offset 0x0394 - Reserved
|
||||||
|
**/
|
||||||
|
UINT32 Reserved9;
|
||||||
|
|
||||||
/** Offset 0x0398 - PCIe PTM enable/disable
|
/** Offset 0x0398 - PCIe PTM enable/disable
|
||||||
Enable/disable Precision Time Measurement for PCIE Root Ports.
|
Enable/disable Precision Time Measurement for PCIE Root Ports.
|
||||||
@ -682,7 +694,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x03ED - Reserved
|
/** Offset 0x03ED - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved7[3];
|
UINT8 Reserved10[3];
|
||||||
|
|
||||||
/** Offset 0x03F0 - Power button debounce configuration
|
/** Offset 0x03F0 - Power button debounce configuration
|
||||||
Debounce time for PWRBTN in microseconds. For values not supported by HW, they will
|
Debounce time for PWRBTN in microseconds. For values not supported by HW, they will
|
||||||
@ -735,7 +747,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x03FD - Reserved
|
/** Offset 0x03FD - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved8;
|
UINT8 Reserved11;
|
||||||
|
|
||||||
/** Offset 0x03FE - External Vnn Voltage Value that will be used in S0ix/Sx states
|
/** Offset 0x03FE - External Vnn Voltage Value that will be used in S0ix/Sx states
|
||||||
Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...), Default is set to 420
|
Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...), Default is set to 420
|
||||||
@ -797,7 +809,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x040B - Reserved
|
/** Offset 0x040B - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved9;
|
UINT8 Reserved12;
|
||||||
|
|
||||||
/** Offset 0x040C - Pointer of ChipsetInit Binary
|
/** Offset 0x040C - Pointer of ChipsetInit Binary
|
||||||
ChipsetInit Binary Pointer.
|
ChipsetInit Binary Pointer.
|
||||||
@ -817,7 +829,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x0415 - Reserved
|
/** Offset 0x0415 - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved10;
|
UINT8 Reserved13;
|
||||||
|
|
||||||
/** Offset 0x0416 - External V1P05 Icc Max Value
|
/** Offset 0x0416 - External V1P05 Icc Max Value
|
||||||
Granularity of this setting is 1mA and maximal possible value is 500mA
|
Granularity of this setting is 1mA and maximal possible value is 500mA
|
||||||
@ -844,7 +856,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x041D - Reserved
|
/** Offset 0x041D - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved11[3];
|
UINT8 Reserved14[3];
|
||||||
|
|
||||||
/** Offset 0x0420 - Extended BIOS Direct Read Decode Range base
|
/** Offset 0x0420 - Extended BIOS Direct Read Decode Range base
|
||||||
Bits of 31:16 of a memory address that'll be a base for Extended BIOS Direct Read Decode.
|
Bits of 31:16 of a memory address that'll be a base for Extended BIOS Direct Read Decode.
|
||||||
@ -858,7 +870,19 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x0428 - Reserved
|
/** Offset 0x0428 - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved12[12];
|
UINT8 Reserved15;
|
||||||
|
|
||||||
|
/** Offset 0x0429 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved16[3];
|
||||||
|
|
||||||
|
/** Offset 0x042C - Reserved
|
||||||
|
**/
|
||||||
|
UINT32 Reserved17;
|
||||||
|
|
||||||
|
/** Offset 0x0430 - Reserved
|
||||||
|
**/
|
||||||
|
UINT32 Reserved18;
|
||||||
|
|
||||||
/** Offset 0x0434 - CNVi Configuration
|
/** Offset 0x0434 - CNVi Configuration
|
||||||
This option allows for automatic detection of Connectivity Solution. [Auto Detection]
|
This option allows for automatic detection of Connectivity Solution. [Auto Detection]
|
||||||
@ -869,7 +893,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x0435 - Reserved
|
/** Offset 0x0435 - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved13;
|
UINT8 Reserved19;
|
||||||
|
|
||||||
/** Offset 0x0436 - CNVi BT Core
|
/** Offset 0x0436 - CNVi BT Core
|
||||||
Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE
|
Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE
|
||||||
@ -987,7 +1011,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x0455 - Reserved
|
/** Offset 0x0455 - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved14;
|
UINT8 Reserved20;
|
||||||
|
|
||||||
/** Offset 0x0456 - OS Timer
|
/** Offset 0x0456 - OS Timer
|
||||||
16 bits Value, Set OS watchdog timer. Setting is invalid if AmtEnabled is 0.
|
16 bits Value, Set OS watchdog timer. Setting is invalid if AmtEnabled is 0.
|
||||||
@ -1023,7 +1047,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x04AF - Reserved
|
/** Offset 0x04AF - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved15;
|
UINT8 Reserved21[1];
|
||||||
|
|
||||||
/** Offset 0x04B0 - PCIE RP Detect Timeout Ms
|
/** Offset 0x04B0 - PCIE RP Detect Timeout Ms
|
||||||
The number of milliseconds within 0~65535 in reference code will wait for link to
|
The number of milliseconds within 0~65535 in reference code will wait for link to
|
||||||
@ -1134,7 +1158,19 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x0521 - Reserved
|
/** Offset 0x0521 - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved16[8];
|
UINT8 Reserved22;
|
||||||
|
|
||||||
|
/** Offset 0x0522 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved23;
|
||||||
|
|
||||||
|
/** Offset 0x0523 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved24[5];
|
||||||
|
|
||||||
|
/** Offset 0x0528 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved25;
|
||||||
|
|
||||||
/** Offset 0x0529 - Enable VMD controller
|
/** Offset 0x0529 - Enable VMD controller
|
||||||
Enable/disable to VMD controller.0: Disable; 1: Enable(Default)
|
Enable/disable to VMD controller.0: Disable; 1: Enable(Default)
|
||||||
@ -1193,7 +1229,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x058D - Reserved
|
/** Offset 0x058D - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved17[3];
|
UINT8 Reserved26[3];
|
||||||
|
|
||||||
/** Offset 0x0590 - VMD Variable
|
/** Offset 0x0590 - VMD Variable
|
||||||
VMD Variable Pointer.
|
VMD Variable Pointer.
|
||||||
@ -1217,7 +1253,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x05A0 - Reserved
|
/** Offset 0x05A0 - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved18;
|
UINT8 Reserved27;
|
||||||
|
|
||||||
/** Offset 0x05A1 - Enable/Disable PMC-PD Solution
|
/** Offset 0x05A1 - Enable/Disable PMC-PD Solution
|
||||||
This policy will enable/disable PMC-PD Solution vs EC-TCPC Solution
|
This policy will enable/disable PMC-PD Solution vs EC-TCPC Solution
|
||||||
@ -1272,7 +1308,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x05B1 - Reserved
|
/** Offset 0x05B1 - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved19;
|
UINT8 Reserved28[1];
|
||||||
|
|
||||||
/** Offset 0x05B2 - ITBT DMA LTR
|
/** Offset 0x05B2 - ITBT DMA LTR
|
||||||
TCSS DMA1, DMA2 LTR value
|
TCSS DMA1, DMA2 LTR value
|
||||||
@ -1281,7 +1317,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x05B6 - Reserved
|
/** Offset 0x05B6 - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved20;
|
UINT8 Reserved29;
|
||||||
|
|
||||||
/** Offset 0x05B7 - Enable/Disable PTM
|
/** Offset 0x05B7 - Enable/Disable PTM
|
||||||
This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports
|
This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports
|
||||||
@ -1306,7 +1342,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x05C7 - Reserved
|
/** Offset 0x05C7 - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved21;
|
UINT8 Reserved30[1];
|
||||||
|
|
||||||
/** Offset 0x05C8 - PCIE RP Snoop Latency Override Value
|
/** Offset 0x05C8 - PCIE RP Snoop Latency Override Value
|
||||||
Latency Tolerance Reporting, Snoop Latency Override Value.
|
Latency Tolerance Reporting, Snoop Latency Override Value.
|
||||||
@ -1358,7 +1394,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x05F3 - Reserved
|
/** Offset 0x05F3 - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved22;
|
UINT8 Reserved31[1];
|
||||||
|
|
||||||
/** Offset 0x05F4 - Imon slope correction
|
/** Offset 0x05F4 - Imon slope correction
|
||||||
PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values.
|
PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values.
|
||||||
@ -1385,7 +1421,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x0612 - Reserved
|
/** Offset 0x0612 - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved23[2];
|
UINT8 Reserved32[2];
|
||||||
|
|
||||||
/** Offset 0x0614 - Thermal Design Current time window
|
/** Offset 0x0614 - Thermal Design Current time window
|
||||||
PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds.
|
PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds.
|
||||||
@ -1434,7 +1470,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x063B - Reserved
|
/** Offset 0x063B - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved24;
|
UINT8 Reserved33[1];
|
||||||
|
|
||||||
/** Offset 0x063C - Thermal Design Current current limit
|
/** Offset 0x063C - Thermal Design Current current limit
|
||||||
PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units.
|
PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units.
|
||||||
@ -1503,7 +1539,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x0687 - Reserved
|
/** Offset 0x0687 - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved25;
|
UINT8 Reserved34;
|
||||||
|
|
||||||
/** Offset 0x0688 - CpuBistData
|
/** Offset 0x0688 - CpuBistData
|
||||||
Pointer CPU BIST Data
|
Pointer CPU BIST Data
|
||||||
@ -1540,7 +1576,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x0693 - Reserved
|
/** Offset 0x0693 - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved26;
|
UINT8 Reserved35[1];
|
||||||
|
|
||||||
/** Offset 0x0694 - VR Voltage Limit
|
/** Offset 0x0694 - VR Voltage Limit
|
||||||
PCODE MMIO Mailbox: Voltage Limit. Range is 0 - 7999mV
|
PCODE MMIO Mailbox: Voltage Limit. Range is 0 - 7999mV
|
||||||
@ -1555,7 +1591,39 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x06A0 - Reserved
|
/** Offset 0x06A0 - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved27[10];
|
UINT8 Reserved36;
|
||||||
|
|
||||||
|
/** Offset 0x06A1 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved37;
|
||||||
|
|
||||||
|
/** Offset 0x06A2 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved38;
|
||||||
|
|
||||||
|
/** Offset 0x06A3 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved39;
|
||||||
|
|
||||||
|
/** Offset 0x06A4 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved40;
|
||||||
|
|
||||||
|
/** Offset 0x06A5 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved41;
|
||||||
|
|
||||||
|
/** Offset 0x06A6 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved42;
|
||||||
|
|
||||||
|
/** Offset 0x06A7 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved43;
|
||||||
|
|
||||||
|
/** Offset 0x06A8 - Reserved
|
||||||
|
**/
|
||||||
|
UINT16 Reserved44;
|
||||||
|
|
||||||
/** Offset 0x06AA - FIVR RFI Spread Spectrum Enable or disable
|
/** Offset 0x06AA - FIVR RFI Spread Spectrum Enable or disable
|
||||||
Enable or Disable FIVR RFI Spread Spectrum. 0: Disable ; <b> 1: Enable </b>
|
Enable or Disable FIVR RFI Spread Spectrum. 0: Disable ; <b> 1: Enable </b>
|
||||||
@ -1564,7 +1632,15 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x06AB - Reserved
|
/** Offset 0x06AB - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved28[13];
|
UINT8 Reserved45[1];
|
||||||
|
|
||||||
|
/** Offset 0x06AC - Reserved
|
||||||
|
**/
|
||||||
|
UINT16 Reserved46[5];
|
||||||
|
|
||||||
|
/** Offset 0x06B6 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved47[2];
|
||||||
|
|
||||||
/** Offset 0x06B8 - PpinSupport to view Protected Processor Inventory Number
|
/** Offset 0x06B8 - PpinSupport to view Protected Processor Inventory Number
|
||||||
Enable or Disable or Auto (Based on End of Manufacturing flag. Disabled if this
|
Enable or Disable or Auto (Based on End of Manufacturing flag. Disabled if this
|
||||||
@ -1587,7 +1663,11 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x06BC - Reserved
|
/** Offset 0x06BC - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved29[2];
|
UINT8 Reserved48;
|
||||||
|
|
||||||
|
/** Offset 0x06BD - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved49;
|
||||||
|
|
||||||
/** Offset 0x06BE - Min Voltage for C8
|
/** Offset 0x06BE - Min Voltage for C8
|
||||||
PCODE MMIO Mailbox: Minimum voltage for C8. Valid if EnableMinVoltageOverride =
|
PCODE MMIO Mailbox: Minimum voltage for C8. Valid if EnableMinVoltageOverride =
|
||||||
@ -1621,7 +1701,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x06C9 - Reserved
|
/** Offset 0x06C9 - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved30;
|
UINT8 Reserved50;
|
||||||
|
|
||||||
/** Offset 0x06CA - CPU VR Power Delivery Design
|
/** Offset 0x06CA - CPU VR Power Delivery Design
|
||||||
Used to communicate the power delivery design capability of the board. This value
|
Used to communicate the power delivery design capability of the board. This value
|
||||||
@ -1632,7 +1712,27 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x06CB - Reserved
|
/** Offset 0x06CB - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved31[32];
|
UINT8 Reserved51[5];
|
||||||
|
|
||||||
|
/** Offset 0x06D0 - Reserved
|
||||||
|
**/
|
||||||
|
UINT32 Reserved52;
|
||||||
|
|
||||||
|
/** Offset 0x06D4 - Reserved
|
||||||
|
**/
|
||||||
|
UINT32 Reserved53;
|
||||||
|
|
||||||
|
/** Offset 0x06D8 - Reserved
|
||||||
|
**/
|
||||||
|
UINT32 Reserved54;
|
||||||
|
|
||||||
|
/** Offset 0x06DC - Reserved
|
||||||
|
**/
|
||||||
|
UINT32 Reserved55;
|
||||||
|
|
||||||
|
/** Offset 0x06E0 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved56[11];
|
||||||
|
|
||||||
/** Offset 0x06EB - Enable Power Optimizer
|
/** Offset 0x06EB - Enable Power Optimizer
|
||||||
Enable DMI Power Optimizer on PCH side.
|
Enable DMI Power Optimizer on PCH side.
|
||||||
@ -1826,7 +1926,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x0894 - Reserved
|
/** Offset 0x0894 - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved32;
|
UINT8 Reserved57;
|
||||||
|
|
||||||
/** Offset 0x0895 - Touch Host Controller Port 1 Assignment
|
/** Offset 0x0895 - Touch Host Controller Port 1 Assignment
|
||||||
Assign THC Port 1
|
Assign THC Port 1
|
||||||
@ -1836,7 +1936,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x0896 - Reserved
|
/** Offset 0x0896 - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved33[2];
|
UINT8 Reserved58[2];
|
||||||
|
|
||||||
/** Offset 0x0898 - Touch Host Controller Port 1 Interrupt Pin Mux
|
/** Offset 0x0898 - Touch Host Controller Port 1 Interrupt Pin Mux
|
||||||
Set THC Port 1 Pin Muxing Value if signal can be enabled on multiple pads. Refer
|
Set THC Port 1 Pin Muxing Value if signal can be enabled on multiple pads. Refer
|
||||||
@ -1846,7 +1946,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x089C - Reserved
|
/** Offset 0x089C - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved34;
|
UINT8 Reserved59;
|
||||||
|
|
||||||
/** Offset 0x089D - PCIE RP Pcie Speed
|
/** Offset 0x089D - PCIE RP Pcie Speed
|
||||||
Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3;
|
Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3;
|
||||||
@ -1878,7 +1978,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x0929 - Reserved
|
/** Offset 0x0929 - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved35[28];
|
UINT8 Reserved60[28];
|
||||||
|
|
||||||
/** Offset 0x0945 - PCIE RP Ltr Enable
|
/** Offset 0x0945 - PCIE RP Ltr Enable
|
||||||
Latency Tolerance Reporting Mechanism.
|
Latency Tolerance Reporting Mechanism.
|
||||||
@ -1936,7 +2036,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x09A1 - Reserved
|
/** Offset 0x09A1 - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved36[3];
|
UINT8 Reserved61[3];
|
||||||
|
|
||||||
/** Offset 0x09A4 - PCIe EQ phase 1 downstream transmitter port preset
|
/** Offset 0x09A4 - PCIe EQ phase 1 downstream transmitter port preset
|
||||||
Allows to select the downstream port preset value that will be used during phase
|
Allows to select the downstream port preset value that will be used during phase
|
||||||
@ -2225,7 +2325,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x0A45 - Reserved
|
/** Offset 0x0A45 - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved37;
|
UINT8 Reserved62;
|
||||||
|
|
||||||
/** Offset 0x0A46 - Thermal Throttling Custimized T0Level Value
|
/** Offset 0x0A46 - Thermal Throttling Custimized T0Level Value
|
||||||
Custimized T0Level value.
|
Custimized T0Level value.
|
||||||
@ -2400,7 +2500,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x0A6B - Reserved
|
/** Offset 0x0A6B - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved38;
|
UINT8 Reserved63;
|
||||||
|
|
||||||
/** Offset 0x0A6C - Thermal Device Temperature
|
/** Offset 0x0A6C - Thermal Device Temperature
|
||||||
Decides the temperature.
|
Decides the temperature.
|
||||||
@ -2425,7 +2525,11 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x0A89 - Reserved
|
/** Offset 0x0A89 - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved39[3];
|
UINT8 Reserved64[2];
|
||||||
|
|
||||||
|
/** Offset 0x0A8B - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved65;
|
||||||
|
|
||||||
/** Offset 0x0A8C - xHCI High Idle Time LTR override
|
/** Offset 0x0A8C - xHCI High Idle Time LTR override
|
||||||
Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting
|
Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting
|
||||||
@ -2475,7 +2579,19 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x0A9C - Reserved
|
/** Offset 0x0A9C - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved40[4];
|
UINT8 Reserved66;
|
||||||
|
|
||||||
|
/** Offset 0x0A9D - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved67;
|
||||||
|
|
||||||
|
/** Offset 0x0A9E - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved68;
|
||||||
|
|
||||||
|
/** Offset 0x0A9F - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved69[1];
|
||||||
|
|
||||||
/** Offset 0x0AA0 - BgpdtHash[4]
|
/** Offset 0x0AA0 - BgpdtHash[4]
|
||||||
BgpdtHash values
|
BgpdtHash values
|
||||||
@ -2489,7 +2605,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x0AC4 - Reserved
|
/** Offset 0x0AC4 - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved41[4];
|
UINT8 Reserved70[4];
|
||||||
|
|
||||||
/** Offset 0x0AC8 - BiosGuardModulePtr
|
/** Offset 0x0AC8 - BiosGuardModulePtr
|
||||||
BiosGuardModulePtr default values
|
BiosGuardModulePtr default values
|
||||||
@ -2522,7 +2638,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x0ADB - Reserved
|
/** Offset 0x0ADB - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved42;
|
UINT8 Reserved71;
|
||||||
|
|
||||||
/** Offset 0x0ADC - Change Default SVID
|
/** Offset 0x0ADC - Change Default SVID
|
||||||
Change the default SVID used in FSP to programming internal devices. This is only
|
Change the default SVID used in FSP to programming internal devices. This is only
|
||||||
@ -2622,7 +2738,35 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x0B00 - Reserved
|
/** Offset 0x0B00 - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved43[12];
|
UINT8 Reserved72;
|
||||||
|
|
||||||
|
/** Offset 0x0B01 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved73;
|
||||||
|
|
||||||
|
/** Offset 0x0B02 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved74;
|
||||||
|
|
||||||
|
/** Offset 0x0B03 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved75;
|
||||||
|
|
||||||
|
/** Offset 0x0B04 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved76;
|
||||||
|
|
||||||
|
/** Offset 0x0B05 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved77;
|
||||||
|
|
||||||
|
/** Offset 0x0B06 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved78[2];
|
||||||
|
|
||||||
|
/** Offset 0x0B08 - Reserved
|
||||||
|
**/
|
||||||
|
UINT32 Reserved79;
|
||||||
|
|
||||||
/** Offset 0x0B0C - PCIE Eq Ph3 Lane Param Cm
|
/** Offset 0x0B0C - PCIE Eq Ph3 Lane Param Cm
|
||||||
CPU_PCIE_EQ_LANE_PARAM. Coefficient C-1.
|
CPU_PCIE_EQ_LANE_PARAM. Coefficient C-1.
|
||||||
@ -2715,7 +2859,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x0BD1 - Reserved
|
/** Offset 0x0BD1 - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved44[3];
|
UINT8 Reserved80[3];
|
||||||
|
|
||||||
/** Offset 0x0BD4 - CPU PCIE device override table pointer
|
/** Offset 0x0BD4 - CPU PCIE device override table pointer
|
||||||
The PCIe device table is being used to override PCIe device ASPM settings. This
|
The PCIe device table is being used to override PCIe device ASPM settings. This
|
||||||
@ -2992,7 +3136,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x0CA2 - Reserved
|
/** Offset 0x0CA2 - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved45[2];
|
UINT8 Reserved81[2];
|
||||||
|
|
||||||
/** Offset 0x0CA4 - LogoPixelHeight Address
|
/** Offset 0x0CA4 - LogoPixelHeight Address
|
||||||
Address of LogoPixelHeight
|
Address of LogoPixelHeight
|
||||||
@ -3006,7 +3150,15 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x0CAC - Reserved
|
/** Offset 0x0CAC - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved46[5];
|
UINT8 Reserved82;
|
||||||
|
|
||||||
|
/** Offset 0x0CAD - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved83;
|
||||||
|
|
||||||
|
/** Offset 0x0CAE - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved84[3];
|
||||||
|
|
||||||
/** Offset 0x0CB1 - RSR feature
|
/** Offset 0x0CB1 - RSR feature
|
||||||
Enable or Disable RSR feature; 0: Disable; <b>1: Enable </b>
|
Enable or Disable RSR feature; 0: Disable; <b>1: Enable </b>
|
||||||
@ -3016,7 +3168,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x0CB2 - Reserved
|
/** Offset 0x0CB2 - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved47[4];
|
UINT8 Reserved85[4];
|
||||||
|
|
||||||
/** Offset 0x0CB6 - Enable or Disable HWP
|
/** Offset 0x0CB6 - Enable or Disable HWP
|
||||||
Enable or Disable HWP(Hardware P states) Support. 0: Disable; <b>1: Enable;</b>
|
Enable or Disable HWP(Hardware P states) Support. 0: Disable; <b>1: Enable;</b>
|
||||||
@ -3409,7 +3561,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x0D2D - Reserved
|
/** Offset 0x0D2D - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved48;
|
UINT8 Reserved86;
|
||||||
|
|
||||||
/** Offset 0x0D2E - Platform Power Pmax
|
/** Offset 0x0D2E - Platform Power Pmax
|
||||||
PCODE MMIO Mailbox: Platform Power Pmax. <b>0 - Auto</b> Specified in 1/8 Watt increments.
|
PCODE MMIO Mailbox: Platform Power Pmax. <b>0 - Auto</b> Specified in 1/8 Watt increments.
|
||||||
@ -3449,7 +3601,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x0D3A - Reserved
|
/** Offset 0x0D3A - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved49[2];
|
UINT8 Reserved87[2];
|
||||||
|
|
||||||
/** Offset 0x0D3C - Package Long duration turbo mode power limit
|
/** Offset 0x0D3C - Package Long duration turbo mode power limit
|
||||||
Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
|
Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
|
||||||
@ -3552,7 +3704,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x0D73 - Reserved
|
/** Offset 0x0D73 - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved50[4];
|
UINT8 Reserved88[4];
|
||||||
|
|
||||||
/** Offset 0x0D77 - Intel Turbo Boost Max Technology 3.0
|
/** Offset 0x0D77 - Intel Turbo Boost Max Technology 3.0
|
||||||
Intel Turbo Boost Max Technology 3.0. 0: Disabled; <b>1: Enabled</b>
|
Intel Turbo Boost Max Technology 3.0. 0: Disabled; <b>1: Enabled</b>
|
||||||
@ -3624,7 +3776,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x0D82 - Reserved
|
/** Offset 0x0D82 - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved51;
|
UINT8 Reserved89;
|
||||||
|
|
||||||
/** Offset 0x0D83 - Dual Tau Boost
|
/** Offset 0x0D83 - Dual Tau Boost
|
||||||
Enable, Disable Dual Tau Boost feature. This is only applicable for Desktop; <b>0:
|
Enable, Disable Dual Tau Boost feature. This is only applicable for Desktop; <b>0:
|
||||||
@ -3635,7 +3787,19 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x0D84 - Reserved
|
/** Offset 0x0D84 - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved52[32];
|
UINT8 Reserved90;
|
||||||
|
|
||||||
|
/** Offset 0x0D85 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved91;
|
||||||
|
|
||||||
|
/** Offset 0x0D86 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved92[14];
|
||||||
|
|
||||||
|
/** Offset 0x0D94 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved93[16];
|
||||||
|
|
||||||
/** Offset 0x0DA4 - End of Post message
|
/** Offset 0x0DA4 - End of Post message
|
||||||
Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1):
|
Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1):
|
||||||
@ -3684,7 +3848,7 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x0DAB - Reserved
|
/** Offset 0x0DAB - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved53;
|
UINT8 Reserved94[1];
|
||||||
|
|
||||||
/** Offset 0x0DAC - PCIE RP Ltr Max Snoop Latency
|
/** Offset 0x0DAC - PCIE RP Ltr Max Snoop Latency
|
||||||
Latency Tolerance Reporting, Max Snoop Latency.
|
Latency Tolerance Reporting, Max Snoop Latency.
|
||||||
@ -3836,7 +4000,19 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x0F96 - Reserved
|
/** Offset 0x0F96 - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved54[16];
|
UINT8 Reserved95[4];
|
||||||
|
|
||||||
|
/** Offset 0x0F9A - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved96[4];
|
||||||
|
|
||||||
|
/** Offset 0x0F9E - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved97[4];
|
||||||
|
|
||||||
|
/** Offset 0x0FA2 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved98[4];
|
||||||
|
|
||||||
/** Offset 0x0FA6 - FOMS Control Policy
|
/** Offset 0x0FA6 - FOMS Control Policy
|
||||||
Choose the Foms Control Policy, <b>Default = 0 </b>
|
Choose the Foms Control Policy, <b>Default = 0 </b>
|
||||||
@ -3858,7 +4034,23 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x0FAF - Reserved
|
/** Offset 0x0FAF - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved55[33];
|
UINT8 Reserved99[8];
|
||||||
|
|
||||||
|
/** Offset 0x0FB7 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved100[8];
|
||||||
|
|
||||||
|
/** Offset 0x0FBF - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved101[8];
|
||||||
|
|
||||||
|
/** Offset 0x0FC7 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved102[8];
|
||||||
|
|
||||||
|
/** Offset 0x0FCF - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved103;
|
||||||
|
|
||||||
/** Offset 0x0FD0 - FspEventHandler
|
/** Offset 0x0FD0 - FspEventHandler
|
||||||
<b>Optional</b> pointer to the boot loader's implementation of FSP_EVENT_HANDLER.
|
<b>Optional</b> pointer to the boot loader's implementation of FSP_EVENT_HANDLER.
|
||||||
@ -3873,7 +4065,87 @@ typedef struct {
|
|||||||
|
|
||||||
/** Offset 0x0FD5 - Reserved
|
/** Offset 0x0FD5 - Reserved
|
||||||
**/
|
**/
|
||||||
UINT8 Reserved56[123];
|
UINT8 Reserved104[4];
|
||||||
|
|
||||||
|
/** Offset 0x0FD9 - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved105;
|
||||||
|
|
||||||
|
/** Offset 0x0FDA - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved106;
|
||||||
|
|
||||||
|
/** Offset 0x0FDB - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved107;
|
||||||
|
|
||||||
|
/** Offset 0x0FDC - Reserved
|
||||||
|
**/
|
||||||
|
UINT32 Reserved108;
|
||||||
|
|
||||||
|
/** Offset 0x0FE0 - Reserved
|
||||||
|
**/
|
||||||
|
UINT32 Reserved109;
|
||||||
|
|
||||||
|
/** Offset 0x0FE4 - Reserved
|
||||||
|
**/
|
||||||
|
UINT32 Reserved110[2];
|
||||||
|
|
||||||
|
/** Offset 0x0FEC - Reserved
|
||||||
|
**/
|
||||||
|
UINT32 Reserved111[2];
|
||||||
|
|
||||||
|
/** Offset 0x0FF4 - Reserved
|
||||||
|
**/
|
||||||
|
UINT32 Reserved112[2];
|
||||||
|
|
||||||
|
/** Offset 0x0FFC - Reserved
|
||||||
|
**/
|
||||||
|
UINT32 Reserved113[2];
|
||||||
|
|
||||||
|
/** Offset 0x1004 - Reserved
|
||||||
|
**/
|
||||||
|
UINT32 Reserved114[2];
|
||||||
|
|
||||||
|
/** Offset 0x100C - Reserved
|
||||||
|
**/
|
||||||
|
UINT32 Reserved115[2];
|
||||||
|
|
||||||
|
/** Offset 0x1014 - Reserved
|
||||||
|
**/
|
||||||
|
UINT32 Reserved116[2];
|
||||||
|
|
||||||
|
/** Offset 0x101C - Reserved
|
||||||
|
**/
|
||||||
|
UINT32 Reserved117[2];
|
||||||
|
|
||||||
|
/** Offset 0x1024 - Reserved
|
||||||
|
**/
|
||||||
|
UINT32 Reserved118[2];
|
||||||
|
|
||||||
|
/** Offset 0x102C - Reserved
|
||||||
|
**/
|
||||||
|
UINT32 Reserved119[2];
|
||||||
|
|
||||||
|
/** Offset 0x1034 - Reserved
|
||||||
|
**/
|
||||||
|
UINT32 Reserved120[2];
|
||||||
|
|
||||||
|
/** Offset 0x103C - Reserved
|
||||||
|
**/
|
||||||
|
UINT32 Reserved121[2];
|
||||||
|
|
||||||
|
/** Offset 0x1044 - Reserved
|
||||||
|
**/
|
||||||
|
UINT32 Reserved122[2];
|
||||||
|
|
||||||
|
/** Offset 0x104C - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved123[2];
|
||||||
|
|
||||||
|
/** Offset 0x104E - Reserved
|
||||||
|
**/
|
||||||
|
UINT8 Reserved124[2];
|
||||||
} FSP_S_CONFIG;
|
} FSP_S_CONFIG;
|
||||||
|
|
||||||
/** Fsp S UPD Configuration
|
/** Fsp S UPD Configuration
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user