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soc/mediatek: Move common definitions from rtc.h to rtc_reg_common.h

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Move the common definitions to rtc_reg_common.h, so we can reuse those
definitions on MT8188.

TEST=build pass
BUG=b:233720142

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Ia1d916a88b7cb875b35ee5813b7b52d9e98f5009
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66180
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Rex-BC Chen 2022-07-27 15:11:25 +08:00 committed by Paul Fagerburg
parent feb573e395
commit 9f81a8fc08
5 changed files with 163 additions and 528 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

134
src/soc/mediatek/common/include/soc/rtc_reg_common.h Normal file
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@ -0,0 +1,134 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef SOC_MEDIATEK_RTC_REG_COMMON_H
#define SOC_MEDIATEK_RTC_REG_COMMON_H
/* RTC registers */
enum {
RTC_BBPU = 0x0588,
RTC_IRQ_STA = 0x058A,
RTC_IRQ_EN = 0x058C,
RTC_CII_EN = 0x058E,
};
enum {
RTC_TC_SEC = 0x0592,
RTC_TC_MIN = 0x0594,
RTC_TC_HOU = 0x0596,
RTC_TC_DOM = 0x0598,
RTC_TC_DOW = 0x059A,
RTC_TC_MTH = 0x059C,
RTC_TC_YEA = 0x059E,
};
enum {
RTC_AL_SEC = 0x05A0,
RTC_AL_MIN = 0x05A2,
RTC_AL_HOU = 0x05A4,
RTC_AL_DOM = 0x05A6,
RTC_AL_DOW = 0x05A8,
RTC_AL_MTH = 0x05AA,
RTC_AL_YEA = 0x05AC,
RTC_AL_MASK = 0x0590,
};
enum {
RTC_OSC32CON = 0x05AE,
RTC_CON = 0x05C4,
RTC_WRTGR = 0x05C2,
};
enum {
RTC_POWERKEY1 = 0x05B0,
RTC_POWERKEY2 = 0x05B2,
};
enum {
RTC_PDN1 = 0x05B4,
RTC_PDN2 = 0x05B6,
RTC_SPAR0 = 0x05B8,
RTC_SPAR1 = 0x05BA,
RTC_PROT = 0x05BC,
RTC_DIFF = 0x05BE,
RTC_CALI = 0x05C0,
};
enum {
RTC_CON_VBAT_LPSTA_RAW = 1U << 0,
RTC_CON_EOSC32_LPEN = 1U << 1,
RTC_CON_XOSC32_LPEN = 1U << 2,
RTC_CON_LPRST = 1U << 3,
RTC_CON_CDBO = 1U << 4,
RTC_CON_F32KOB = 1U << 5,
RTC_CON_GPO = 1U << 6,
RTC_CON_GOE = 1U << 7,
RTC_CON_GSR = 1U << 8,
RTC_CON_GSMT = 1U << 9,
RTC_CON_GPEN = 1U << 10,
RTC_CON_GPU = 1U << 11,
RTC_CON_GE4 = 1U << 12,
RTC_CON_GE8 = 1U << 13,
RTC_CON_GPI = 1U << 14,
RTC_CON_LPSTA_RAW = 1U << 15,
};
enum {
RTC_LPD_OPT_XOSC_AND_EOSC_LPD = 0U << 13,
RTC_LPD_OPT_EOSC_LPD = 1U << 13,
RTC_LPD_OPT_XOSC_LPD = 2U << 13,
RTC_LPD_OPT_F32K_CK_ALIVE = 3U << 13,
RTC_LPD_OPT_MASK = 3U << 13,
};
/* PMIC TOP Register Definition */
enum {
PMIC_RG_SCK_TOP_CON0 = 0x050C,
};
/* PMIC TOP Register Definition */
enum {
PMIC_RG_TOP_CKPDN_CON0 = 0x010C,
PMIC_RG_TOP_CKPDN_CON0_SET = 0x010E,
PMIC_RG_TOP_CKPDN_CON0_CLR = 0x0110,
PMIC_RG_TOP_CKPDN_CON1 = 0x0112,
PMIC_RG_TOP_CKPDN_CON1_SET = 0x0114,
PMIC_RG_TOP_CKPDN_CON1_CLR = 0x0116,
PMIC_RG_TOP_CKSEL_CON0 = 0x0118,
PMIC_RG_TOP_CKSEL_CON0_SET = 0x011A,
PMIC_RG_TOP_CKSEL_CON0_CLR = 0x011C,
};
enum {
PMIC_RG_FQMTR_32K_CK_PDN_SHIFT = 10,
PMIC_RG_FQMTR_CK_PDN_SHIFT = 11,
};
enum {
PMIC_FQMTR_RST_SHIFT = 8,
};
enum {
PMIC_FQMTR_CON0_XOSC32_CK = 0U << 0,
PMIC_FQMTR_CON0_DCXO_F32K_CK = 1U << 0,
PMIC_FQMTR_CON0_EOSC32_CK = 2U << 0,
PMIC_FQMTR_CON0_XOSC32_CK_DETECTON = 3U << 0,
PMIC_FQMTR_CON0_FQM26M_CK = 4U << 0,
PMIC_FQMTR_CON0_FQM32k_CK = 5U << 0,
PMIC_FQMTR_CON0_TEST_CK = 6U << 0,
PMIC_FQMTR_CON0_TCKSEL_MASK = 7U << 0,
PMIC_FQMTR_CON0_BUSY = 1U << 3,
PMIC_FQMTR_CON0_DCXO26M_EN = 1U << 4,
PMIC_FQMTR_CON0_FQMTR_EN = 1U << 15,
};
enum {
RTC_FQMTR_LOW_BASE = 794 - 2,
RTC_FQMTR_HIGH_BASE = 794 + 2,
};
enum {
RTC_XOSCCALI_START = 0x00,
RTC_XOSCCALI_END = 0x1f,
};
#endif /* SOC_MEDIATEK_RTC_REG_COMMON_H */

176
src/soc/mediatek/mt8183/include/soc/rtc.h
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@ -5,87 +5,20 @@
#include <soc/pmic_wrap_common.h>
#include <soc/rtc_common.h>
#include <soc/rtc_reg_common.h>
#include <stdbool.h>
/* RTC registers */
enum {
RTC_BBPU = 0x0588,
RTC_IRQ_STA = 0x058A,
RTC_IRQ_EN = 0x058C,
RTC_CII_EN = 0x058E
};
RTC_BBPU_PWREN = 1U << 0,
RTC_BBPU_CLR = 1U << 1,
RTC_BBPU_INIT = 1U << 2,
RTC_BBPU_AUTO = 1U << 3,
RTC_BBPU_CLRPKY = 1U << 4,
RTC_BBPU_RELOAD = 1U << 5,
RTC_BBPU_CBUSY = 1U << 6,
enum {
RTC_TC_SEC = 0x0592,
RTC_TC_MIN = 0x0594,
RTC_TC_HOU = 0x0596,
RTC_TC_DOM = 0x0598,
RTC_TC_DOW = 0x059A,
RTC_TC_MTH = 0x059C,
RTC_TC_YEA = 0x059E
};
enum {
RTC_AL_SEC = 0x05A0,
RTC_AL_MIN = 0x05A2,
RTC_AL_HOU = 0x05A4,
RTC_AL_DOM = 0x05A6,
RTC_AL_DOW = 0x05A8,
RTC_AL_MTH = 0x05AA,
RTC_AL_YEA = 0x05AC,
RTC_AL_MASK = 0x0590
};
enum {
RTC_OSC32CON = 0x05AE,
RTC_CON = 0x05C4,
RTC_WRTGR = 0x05C2
};
enum {
RTC_POWERKEY1 = 0x05B0,
RTC_POWERKEY2 = 0x05B2
};
enum {
RTC_PDN1 = 0x05B4,
RTC_PDN2 = 0x05B6,
RTC_SPAR0 = 0x05B8,
RTC_SPAR1 = 0x05BA,
RTC_PROT = 0x05BC,
RTC_DIFF = 0x05BE,
RTC_CALI = 0x05C0
};
enum {
RTC_BBPU_PWREN = 1U << 0,
RTC_BBPU_CLR = 1U << 1,
RTC_BBPU_INIT = 1U << 2,
RTC_BBPU_AUTO = 1U << 3,
RTC_BBPU_CLRPKY = 1U << 4,
RTC_BBPU_RELOAD = 1U << 5,
RTC_BBPU_CBUSY = 1U << 6,
RTC_CBUSY_TIMEOUT_US = 8000
};
enum {
RTC_CON_VBAT_LPSTA_RAW = 1U << 0,
RTC_CON_EOSC32_LPEN = 1U << 1,
RTC_CON_XOSC32_LPEN = 1U << 2,
RTC_CON_LPRST = 1U << 3,
RTC_CON_CDBO = 1U << 4,
RTC_CON_F32KOB = 1U << 5,
RTC_CON_GPO = 1U << 6,
RTC_CON_GOE = 1U << 7,
RTC_CON_GSR = 1U << 8,
RTC_CON_GSMT = 1U << 9,
RTC_CON_GPEN = 1U << 10,
RTC_CON_GPU = 1U << 11,
RTC_CON_GE4 = 1U << 12,
RTC_CON_GE8 = 1U << 13,
RTC_CON_GPI = 1U << 14,
RTC_CON_LPSTA_RAW = 1U << 15
RTC_CBUSY_TIMEOUT_US = 8000,
};
enum {
@ -99,58 +32,28 @@ enum {
RTC_EMBCK_SRC_SEL = 1U << 8,
RTC_EMBCK_SEL_OPTION = 1U << 9,
RTC_GPS_CKOUT_EN = 1U << 10,
RTC_REG_XOSC32_ENB = 1U << 15
};
enum {
RTC_LPD_OPT_XOSC_AND_EOSC_LPD = 0U << 13,
RTC_LPD_OPT_EOSC_LPD = 1U << 13,
RTC_LPD_OPT_XOSC_LPD = 2U << 13,
RTC_LPD_OPT_F32K_CK_ALIVE = 3U << 13,
RTC_LPD_OPT_MASK = 3U << 13
};
/* PMIC TOP Register Definition */
enum {
PMIC_RG_SCK_TOP_CON0 = 0x050C
};
/* PMIC TOP Register Definition */
enum {
PMIC_RG_TOP_CKPDN_CON0 = 0x010C,
PMIC_RG_TOP_CKPDN_CON0_SET = 0x010E,
PMIC_RG_TOP_CKPDN_CON0_CLR = 0x0110,
PMIC_RG_TOP_CKPDN_CON1 = 0x0112,
PMIC_RG_TOP_CKPDN_CON1_SET = 0x0114,
PMIC_RG_TOP_CKPDN_CON1_CLR = 0x0116,
PMIC_RG_TOP_CKSEL_CON0 = 0x0118,
PMIC_RG_TOP_CKSEL_CON0_SET = 0x011A,
PMIC_RG_TOP_CKSEL_CON0_CLR = 0x011C
};
enum {
PMIC_RG_FQMTR_32K_CK_PDN_SHIFT = 10,
PMIC_RG_FQMTR_CK_PDN_SHIFT = 11
RTC_REG_XOSC32_ENB = 1U << 15,
};
/* PMIC DCXO Register Definition */
enum {
PMIC_RG_DCXO_CW00 = 0x0788,
PMIC_RG_DCXO_CW00_CLR = 0x078C,
PMIC_RG_DCXO_CW02 = 0x0790,
PMIC_RG_DCXO_CW07 = 0x079A,
PMIC_RG_DCXO_CW09 = 0x079E,
PMIC_RG_DCXO_CW11 = 0x07A2,
PMIC_RG_DCXO_CW13 = 0x07AA,
PMIC_RG_DCXO_CW15 = 0x07AE,
PMIC_RG_DCXO_CW16 = 0x07B0,
PMIC_RG_DCXO_CW21 = 0x07BA,
PMIC_RG_DCXO_CW23 = 0x07BE,
PMIC_RG_DCXO_ELR0 = 0x07C4
PMIC_RG_DCXO_CW00 = 0x0788,
PMIC_RG_DCXO_CW00_CLR = 0x078C,
PMIC_RG_DCXO_CW02 = 0x0790,
PMIC_RG_DCXO_CW03 = 0x0794,
PMIC_RG_DCXO_CW07 = 0x079A,
PMIC_RG_DCXO_CW09 = 0x079E,
PMIC_RG_DCXO_CW11 = 0x07A2,
PMIC_RG_DCXO_CW13 = 0x07AA,
PMIC_RG_DCXO_CW15 = 0x07AE,
PMIC_RG_DCXO_CW16 = 0x07B0,
PMIC_RG_DCXO_CW21 = 0x07BA,
PMIC_RG_DCXO_CW23 = 0x07BE,
PMIC_RG_DCXO_ELR0 = 0x07C4,
};
enum {
PMIC_RG_TOP_TMA_KEY = 0x03A8
PMIC_RG_TOP_TMA_KEY = 0x03A8,
};
/* PMIC Frequency Meter Definition */
@ -161,7 +64,7 @@ enum {
PMIC_RG_FQMTR_WINSET = 0x0516,
PMIC_RG_FQMTR_DATA = 0x0518,
FQMTR_TIMEOUT_US = 8000
FQMTR_TIMEOUT_US = 8000,
};
enum {
@ -172,36 +75,9 @@ enum {
PMIC_FQMTR_FIX_CLK_SMPS_CK = 4U << 0,
PMIC_FQMTR_FIX_CLK_TCK_SEC = 5U << 0,
PMIC_FQMTR_FIX_CLK_PMU_75K = 6U << 0,
PMIC_FQMTR_CKSEL_MASK = 7U << 0
PMIC_FQMTR_CKSEL_MASK = 7U << 0,
};
enum {
PMIC_FQMTR_RST_SHIFT = 8
};
enum {
PMIC_FQMTR_CON0_XOSC32_CK = 0U << 0,
PMIC_FQMTR_CON0_DCXO_F32K_CK = 1U << 0,
PMIC_FQMTR_CON0_EOSC32_CK = 2U << 0,
PMIC_FQMTR_CON0_XOSC32_CK_DETECTON = 3U << 0,
PMIC_FQMTR_CON0_FQM26M_CK = 4U << 0,
PMIC_FQMTR_CON0_FQM32k_CK = 5U << 0,
PMIC_FQMTR_CON0_TEST_CK = 6U << 0,
PMIC_FQMTR_CON0_TCKSEL_MASK = 7U << 0,
PMIC_FQMTR_CON0_BUSY = 1U << 3,
PMIC_FQMTR_CON0_DCXO26M_EN = 1U << 4,
PMIC_FQMTR_CON0_FQMTR_EN = 1U << 15
};
enum {
RTC_FQMTR_LOW_BASE = 794 - 2,
RTC_FQMTR_HIGH_BASE = 794 + 2
};
enum {
RTC_XOSCCALI_START = 0x00,
RTC_XOSCCALI_END = 0x1f
};
/* external API */
void rtc_bbpu_power_on(void);

127
src/soc/mediatek/mt8186/include/soc/rtc.h
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@ -10,58 +10,10 @@
#include <soc/pmic_wrap_common.h>
#include <soc/rtc_common.h>
#include <soc/rtc_reg_common.h>
#include <stdbool.h>
/* RTC registers */
enum {
RTC_BBPU = 0x0588,
RTC_IRQ_STA = 0x058A,
RTC_IRQ_EN = 0x058C,
RTC_CII_EN = 0x058E,
};
enum {
RTC_TC_SEC = 0x0592,
RTC_TC_MIN = 0x0594,
RTC_TC_HOU = 0x0596,
RTC_TC_DOM = 0x0598,
RTC_TC_DOW = 0x059A,
RTC_TC_MTH = 0x059C,
RTC_TC_YEA = 0x059E,
};
enum {
RTC_AL_SEC = 0x05A0,
RTC_AL_MIN = 0x05A2,
RTC_AL_HOU = 0x05A4,
RTC_AL_DOM = 0x05A6,
RTC_AL_DOW = 0x05A8,
RTC_AL_MTH = 0x05AA,
RTC_AL_YEA = 0x05AC,
RTC_AL_MASK = 0x0590,
};
enum {
RTC_OSC32CON = 0x05AE,
RTC_CON = 0x05C4,
RTC_WRTGR = 0x05C2,
};
enum {
RTC_POWERKEY1 = 0x05B0,
RTC_POWERKEY2 = 0x05B2,
};
enum {
RTC_PDN1 = 0x05B4,
RTC_PDN2 = 0x05B6,
RTC_SPAR0 = 0x05B8,
RTC_SPAR1 = 0x05BA,
RTC_PROT = 0x05BC,
RTC_DIFF = 0x05BE,
RTC_CALI = 0x05C0,
};
enum {
RTC_BBPU_PWREN = 1U << 0,
RTC_BBPU_CLR = 1U << 1,
@ -74,25 +26,6 @@ enum {
RTC_CBUSY_TIMEOUT_US = 8000,
};
enum {
RTC_CON_VBAT_LPSTA_RAW = 1U << 0,
RTC_CON_EOSC32_LPEN = 1U << 1,
RTC_CON_XOSC32_LPEN = 1U << 2,
RTC_CON_LPRST = 1U << 3,
RTC_CON_CDBO = 1U << 4,
RTC_CON_F32KOB = 1U << 5,
RTC_CON_GPO = 1U << 6,
RTC_CON_GOE = 1U << 7,
RTC_CON_GSR = 1U << 8,
RTC_CON_GSMT = 1U << 9,
RTC_CON_GPEN = 1U << 10,
RTC_CON_GPU = 1U << 11,
RTC_CON_GE4 = 1U << 12,
RTC_CON_GE8 = 1U << 13,
RTC_CON_GPI = 1U << 14,
RTC_CON_LPSTA_RAW = 1U << 15,
};
enum {
RTC_XOSCCALI_MASK = 0x1F << 0,
RTC_XOSC32_ENB = 1U << 5,
@ -107,37 +40,6 @@ enum {
RTC_REG_XOSC32_ENB = 1U << 15,
};
enum {
RTC_LPD_OPT_XOSC_AND_EOSC_LPD = 0U << 13,
RTC_LPD_OPT_EOSC_LPD = 1U << 13,
RTC_LPD_OPT_XOSC_LPD = 2U << 13,
RTC_LPD_OPT_F32K_CK_ALIVE = 3U << 13,
RTC_LPD_OPT_MASK = 3U << 13,
};
/* PMIC TOP Register Definition */
enum {
PMIC_RG_SCK_TOP_CON0 = 0x050C,
};
/* PMIC TOP Register Definition */
enum {
PMIC_RG_TOP_CKPDN_CON0 = 0x010C,
PMIC_RG_TOP_CKPDN_CON0_SET = 0x010E,
PMIC_RG_TOP_CKPDN_CON0_CLR = 0x0110,
PMIC_RG_TOP_CKPDN_CON1 = 0x0112,
PMIC_RG_TOP_CKPDN_CON1_SET = 0x0114,
PMIC_RG_TOP_CKPDN_CON1_CLR = 0x0116,
PMIC_RG_TOP_CKSEL_CON0 = 0x0118,
PMIC_RG_TOP_CKSEL_CON0_SET = 0x011A,
PMIC_RG_TOP_CKSEL_CON0_CLR = 0x011C,
};
enum {
PMIC_RG_FQMTR_32K_CK_PDN_SHIFT = 10,
PMIC_RG_FQMTR_CK_PDN_SHIFT = 11,
};
/* PMIC DCXO Register Definition */
enum {
PMIC_RG_DCXO_CW00 = 0x0788,
@ -181,33 +83,6 @@ enum {
PMIC_FQMTR_CKSEL_MASK = 7U << 0,
};
enum {
PMIC_FQMTR_RST_SHIFT = 8
};
enum {
PMIC_FQMTR_CON0_XOSC32_CK = 0U << 0,
PMIC_FQMTR_CON0_DCXO_F32K_CK = 1U << 0,
PMIC_FQMTR_CON0_EOSC32_CK = 2U << 0,
PMIC_FQMTR_CON0_XOSC32_CK_DETECTON = 3U << 0,
PMIC_FQMTR_CON0_FQM26M_CK = 4U << 0,
PMIC_FQMTR_CON0_FQM32k_CK = 5U << 0,
PMIC_FQMTR_CON0_TEST_CK = 6U << 0,
PMIC_FQMTR_CON0_TCKSEL_MASK = 7U << 0,
PMIC_FQMTR_CON0_BUSY = 1U << 3,
PMIC_FQMTR_CON0_DCXO26M_EN = 1U << 4,
PMIC_FQMTR_CON0_FQMTR_EN = 1U << 15,
};
enum {
RTC_FQMTR_LOW_BASE = 794 - 2,
RTC_FQMTR_HIGH_BASE = 794 + 2,
};
enum {
RTC_XOSCCALI_START = 0x00,
RTC_XOSCCALI_END = 0x1f,
};
/* external API */
void rtc_bbpu_power_on(void);

127
src/soc/mediatek/mt8192/include/soc/rtc.h
View File

@ -4,58 +4,10 @@
#define SOC_MEDIATEK_MT8192_RTC_H
#include <soc/pmif.h>
#include <soc/rtc_reg_common.h>
#include <stdbool.h>
/* RTC registers */
enum {
RTC_BBPU = 0x0588,
RTC_IRQ_STA = 0x058A,
RTC_IRQ_EN = 0x058C,
RTC_CII_EN = 0x058E,
};
enum {
RTC_TC_SEC = 0x0592,
RTC_TC_MIN = 0x0594,
RTC_TC_HOU = 0x0596,
RTC_TC_DOM = 0x0598,
RTC_TC_DOW = 0x059A,
RTC_TC_MTH = 0x059C,
RTC_TC_YEA = 0x059E,
};
enum {
RTC_AL_SEC = 0x05A0,
RTC_AL_MIN = 0x05A2,
RTC_AL_HOU = 0x05A4,
RTC_AL_DOM = 0x05A6,
RTC_AL_DOW = 0x05A8,
RTC_AL_MTH = 0x05AA,
RTC_AL_YEA = 0x05AC,
RTC_AL_MASK = 0x0590,
};
enum {
RTC_OSC32CON = 0x05AE,
RTC_CON = 0x05C4,
RTC_WRTGR = 0x05C2,
};
enum {
RTC_POWERKEY1 = 0x05B0,
RTC_POWERKEY2 = 0x05B2,
};
enum {
RTC_PDN1 = 0x05B4,
RTC_PDN2 = 0x05B6,
RTC_SPAR0 = 0x05B8,
RTC_SPAR1 = 0x05BA,
RTC_PROT = 0x05BC,
RTC_DIFF = 0x05BE,
RTC_CALI = 0x05C0,
};
enum {
RTC_BBPU_ENABLE_ALARM = 1U << 0,
RTC_BBPU_SPAR_SW = 1U << 1,
@ -67,25 +19,6 @@ enum {
RTC_CBUSY_TIMEOUT_US = 1000000,
};
enum {
RTC_CON_VBAT_LPSTA_RAW = 1U << 0,
RTC_CON_EOSC32_LPEN = 1U << 1,
RTC_CON_XOSC32_LPEN = 1U << 2,
RTC_CON_LPRST = 1U << 3,
RTC_CON_CDBO = 1U << 4,
RTC_CON_F32KOB = 1U << 5,
RTC_CON_GPO = 1U << 6,
RTC_CON_GOE = 1U << 7,
RTC_CON_GSR = 1U << 8,
RTC_CON_GSMT = 1U << 9,
RTC_CON_GPEN = 1U << 10,
RTC_CON_GPU = 1U << 11,
RTC_CON_GE4 = 1U << 12,
RTC_CON_GE8 = 1U << 13,
RTC_CON_GPI = 1U << 14,
RTC_CON_LPSTA_RAW = 1U << 15,
};
enum {
RTC_XOSCCALI_MASK = 0x1F << 0,
RTC_XOSC32_ENB = 1U << 5,
@ -109,37 +42,6 @@ enum {
RTC_EMB_K_EOSC32_MODE,
};
enum {
RTC_LPD_OPT_XOSC_AND_EOSC_LPD = 0U << 13,
RTC_LPD_OPT_EOSC_LPD = 1U << 13,
RTC_LPD_OPT_XOSC_LPD = 2U << 13,
RTC_LPD_OPT_F32K_CK_ALIVE = 3U << 13,
RTC_LPD_OPT_MASK = 3U << 13,
};
/* PMIC TOP Register Definition */
enum {
PMIC_RG_SCK_TOP_CON0 = 0x050C,
};
/* PMIC TOP Register Definition */
enum {
PMIC_RG_TOP_CKPDN_CON0 = 0x010C,
PMIC_RG_TOP_CKPDN_CON0_SET = 0x010E,
PMIC_RG_TOP_CKPDN_CON0_CLR = 0x0110,
PMIC_RG_TOP_CKPDN_CON1 = 0x0112,
PMIC_RG_TOP_CKPDN_CON1_SET = 0x0114,
PMIC_RG_TOP_CKPDN_CON1_CLR = 0x0116,
PMIC_RG_TOP_CKSEL_CON0 = 0x0118,
PMIC_RG_TOP_CKSEL_CON0_SET = 0x011A,
PMIC_RG_TOP_CKSEL_CON0_CLR = 0x011C,
};
enum {
PMIC_RG_FQMTR_32K_CK_PDN_SHIFT = 10,
PMIC_RG_FQMTR_CK_PDN_SHIFT = 11,
};
enum {
PMIC_RG_BANK_FQMTR_RST = 0x522,
};
@ -170,33 +72,6 @@ enum {
PMIC_FQMTR_CKSEL_MASK = 7U << 0,
};
enum {
PMIC_FQMTR_RST_SHIFT = 8,
};
enum {
PMIC_FQMTR_CON0_XOSC32_CK = 0U << 0,
PMIC_FQMTR_CON0_DCXO_F32K_CK = 1U << 0,
PMIC_FQMTR_CON0_EOSC32_CK = 2U << 0,
PMIC_FQMTR_CON0_XOSC32_CK_DETECTON = 3U << 0,
PMIC_FQMTR_CON0_FQM26M_CK = 4U << 0,
PMIC_FQMTR_CON0_FQM32k_CK = 5U << 0,
PMIC_FQMTR_CON0_TEST_CK = 6U << 0,
PMIC_FQMTR_CON0_TCKSEL_MASK = 7U << 0,
PMIC_FQMTR_CON0_BUSY = 1U << 3,
PMIC_FQMTR_CON0_DCXO26M_EN = 1U << 4,
PMIC_FQMTR_CON0_FQMTR_EN = 1U << 15,
};
enum {
RTC_FQMTR_LOW_BASE = 794 - 2,
RTC_FQMTR_HIGH_BASE = 794 + 2,
};
enum {
RTC_XOSCCALI_START = 0x00,
RTC_XOSCCALI_END = 0x1f,
};
enum {
RTC_TC_MTH_MASK = 0xf,

127
src/soc/mediatek/mt8195/include/soc/rtc.h
View File

@ -4,58 +4,10 @@
#define SOC_MEDIATEK_MT8195_RTC_H
#include <soc/pmif.h>
#include <soc/rtc_reg_common.h>
#include <stdbool.h>
/* RTC registers */
enum {
RTC_BBPU = 0x0588,
RTC_IRQ_STA = 0x058A,
RTC_IRQ_EN = 0x058C,
RTC_CII_EN = 0x058E,
};
enum {
RTC_TC_SEC = 0x0592,
RTC_TC_MIN = 0x0594,
RTC_TC_HOU = 0x0596,
RTC_TC_DOM = 0x0598,
RTC_TC_DOW = 0x059A,
RTC_TC_MTH = 0x059C,
RTC_TC_YEA = 0x059E,
};
enum {
RTC_AL_SEC = 0x05A0,
RTC_AL_MIN = 0x05A2,
RTC_AL_HOU = 0x05A4,
RTC_AL_DOM = 0x05A6,
RTC_AL_DOW = 0x05A8,
RTC_AL_MTH = 0x05AA,
RTC_AL_YEA = 0x05AC,
RTC_AL_MASK = 0x0590,
};
enum {
RTC_OSC32CON = 0x05AE,
RTC_CON = 0x05C4,
RTC_WRTGR = 0x05C2,
};
enum {
RTC_POWERKEY1 = 0x05B0,
RTC_POWERKEY2 = 0x05B2,
};
enum {
RTC_PDN1 = 0x05B4,
RTC_PDN2 = 0x05B6,
RTC_SPAR0 = 0x05B8,
RTC_SPAR1 = 0x05BA,
RTC_PROT = 0x05BC,
RTC_DIFF = 0x05BE,
RTC_CALI = 0x05C0,
};
enum {
RTC_BBPU_ENABLE_ALARM = 1U << 0,
RTC_BBPU_SPAR_SW = 1U << 1,
@ -67,25 +19,6 @@ enum {
RTC_CBUSY_TIMEOUT_US = 1000000,
};
enum {
RTC_CON_VBAT_LPSTA_RAW = 1U << 0,
RTC_CON_EOSC32_LPEN = 1U << 1,
RTC_CON_XOSC32_LPEN = 1U << 2,
RTC_CON_LPRST = 1U << 3,
RTC_CON_CDBO = 1U << 4,
RTC_CON_F32KOB = 1U << 5,
RTC_CON_GPO = 1U << 6,
RTC_CON_GOE = 1U << 7,
RTC_CON_GSR = 1U << 8,
RTC_CON_GSMT = 1U << 9,
RTC_CON_GPEN = 1U << 10,
RTC_CON_GPU = 1U << 11,
RTC_CON_GE4 = 1U << 12,
RTC_CON_GE8 = 1U << 13,
RTC_CON_GPI = 1U << 14,
RTC_CON_LPSTA_RAW = 1U << 15,
};
enum {
RTC_XOSCCALI_MASK = 0x1F << 0,
RTC_XOSC32_ENB = 1U << 5,
@ -109,37 +42,6 @@ enum {
RTC_EMB_K_EOSC32_MODE,
};
enum {
RTC_LPD_OPT_XOSC_AND_EOSC_LPD = 0U << 13,
RTC_LPD_OPT_EOSC_LPD = 1U << 13,
RTC_LPD_OPT_XOSC_LPD = 2U << 13,
RTC_LPD_OPT_F32K_CK_ALIVE = 3U << 13,
RTC_LPD_OPT_MASK = 3U << 13,
};
/* PMIC TOP Register Definition */
enum {
PMIC_RG_SCK_TOP_CON0 = 0x050C,
};
/* PMIC TOP Register Definition */
enum {
PMIC_RG_TOP_CKPDN_CON0 = 0x010C,
PMIC_RG_TOP_CKPDN_CON0_SET = 0x010E,
PMIC_RG_TOP_CKPDN_CON0_CLR = 0x0110,
PMIC_RG_TOP_CKPDN_CON1 = 0x0112,
PMIC_RG_TOP_CKPDN_CON1_SET = 0x0114,
PMIC_RG_TOP_CKPDN_CON1_CLR = 0x0116,
PMIC_RG_TOP_CKSEL_CON0 = 0x0118,
PMIC_RG_TOP_CKSEL_CON0_SET = 0x011A,
PMIC_RG_TOP_CKSEL_CON0_CLR = 0x011C,
};
enum {
PMIC_RG_FQMTR_32K_CK_PDN_SHIFT = 10,
PMIC_RG_FQMTR_CK_PDN_SHIFT = 11,
};
enum {
PMIC_RG_BANK_FQMTR_RST = 0x522,
};
@ -170,33 +72,6 @@ enum {
PMIC_FQMTR_CKSEL_MASK = 7U << 0,
};
enum {
PMIC_FQMTR_RST_SHIFT = 8,
};
enum {
PMIC_FQMTR_CON0_XOSC32_CK = 0U << 0,
PMIC_FQMTR_CON0_DCXO_F32K_CK = 1U << 0,
PMIC_FQMTR_CON0_EOSC32_CK = 2U << 0,
PMIC_FQMTR_CON0_XOSC32_CK_DETECTON = 3U << 0,
PMIC_FQMTR_CON0_FQM26M_CK = 4U << 0,
PMIC_FQMTR_CON0_FQM32k_CK = 5U << 0,
PMIC_FQMTR_CON0_TEST_CK = 6U << 0,
PMIC_FQMTR_CON0_TCKSEL_MASK = 7U << 0,
PMIC_FQMTR_CON0_BUSY = 1U << 3,
PMIC_FQMTR_CON0_DCXO26M_EN = 1U << 4,
PMIC_FQMTR_CON0_FQMTR_EN = 1U << 15,
};
enum {
RTC_FQMTR_LOW_BASE = 794 - 2,
RTC_FQMTR_HIGH_BASE = 794 + 2,
};
enum {
RTC_XOSCCALI_START = 0x00,
RTC_XOSCCALI_END = 0x1f,
};
enum {
RTC_TC_MTH_MASK = 0xf,