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baytrail: add GPIO SMI support

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GPIOs which trigger SMIs only set the status bits in the ALT_GPIO_SMI
regier. No bits in the SMI_STS register are set. Therefore, the
ALT_GPIO_SMI register needs to be read and cleared on every SMI.
Additionally, the mainboard_gpi_smi() handler needs to be called as
well on every SMI because of this property.

BUG=chrome-os-partner:23505
BRANCH=None
TEST=Built and booted to recovery screen. Typed 'lidclose' on EC
     console. SMI occurred which caused the board to be shutdown.

Change-Id: Ic204d8b928a0cb4f51f108a649f374d9f94e4f47
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176391
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4958
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Aaron Durbin
2013-11-11 14:45:27 -06:00
committed by Aaron Durbin
parent 59a4cd5578
commit 9f83e873f4
4 changed files with 62 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

57
src/soc/intel/baytrail/pmutil.c
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@ -52,14 +52,15 @@ uint16_t get_pmbase(void)
return pci_read_config16(get_pcu_dev(), ABASE) & 0xfff8;
}
static void print_status_bits(uint32_t status, const char *bit_names[])
static void print_num_status_bits(int num_bits, uint32_t status,
const char *bit_names[])
{
int i;
if (!status)
return;
for (i = 31; i >= 0; i--) {
for (i = num_bits - 1; i >= 0; i--) {
if (status & (1 << i)) {
if (bit_names[i])
printk(BIOS_DEBUG, "%s ", bit_names[i]);
@ -69,6 +70,11 @@ static void print_status_bits(uint32_t status, const char *bit_names[])
}
}
static void print_status_bits(uint32_t status, const char *bit_names[])
{
print_num_status_bits(32, status, bit_names);
}
static uint32_t print_smi_status(uint32_t smi_sts)
{
static const char *smi_sts_bits[] = {
@ -295,3 +301,50 @@ uint32_t clear_gpe_status(void)
{
return print_gpe_sts(reset_gpe_status());
}
static uint32_t reset_alt_status(void)
{
uint16_t pmbase = get_pmbase();
uint32_t alt_gpio_smi = inl(pmbase + ALT_GPIO_SMI);
outl(alt_gpio_smi, pmbase + ALT_GPIO_SMI);
return alt_gpio_smi;
}
static uint32_t print_alt_sts(uint32_t alt_gpio_smi)
{
uint32_t alt_gpio_sts;
static const char *alt_gpio_smi_sts_bits[] = {
[0] = "SUS_GPIO_0",
[1] = "SUS_GPIO_1",
[2] = "SUS_GPIO_2",
[3] = "SUS_GPIO_3",
[4] = "SUS_GPIO_4",
[5] = "SUS_GPIO_5",
[6] = "SUS_GPIO_6",
[7] = "SUS_GPIO_7",
[8] = "CORE_GPIO_0",
[9] = "CORE_GPIO_1",
[10] = "CORE_GPIO_2",
[11] = "CORE_GPIO_3",
[12] = "CORE_GPIO_4",
[13] = "CORE_GPIO_5",
[14] = "CORE_GPIO_6",
[15] = "CORE_GPIO_7",
};
/* Status bits are in the upper 16 bits. */
alt_gpio_sts = alt_gpio_smi >> 16;
if (!alt_gpio_sts)
return alt_gpio_smi;
printk(BIOS_DEBUG, "ALT_GPIO_SMI: ");
print_num_status_bits(16, alt_gpio_sts, alt_gpio_smi_sts_bits);
printk(BIOS_DEBUG, "\n");
return alt_gpio_smi;
}
uint32_t clear_alt_status(void)
{
return print_alt_sts(reset_alt_status());
}