SMM: Validate more user-provided pointers
Mitigate issues presented in "Digging Into The Core of Boot" found by "Yuriy Bulygin" and "Oleksandr Bazhaniuk" at RECON-MTL-2017. Validate user-provided pointers using the newly-added functions. This protects SMM from ring0 attacks. Change-Id: I8a347ccdd20816924bf1bceb3b24bf7b22309312 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
committed by
Patrick Georgi
parent
37ac368c78
commit
9f8f11513a
@ -2,6 +2,7 @@
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#include <arch/io.h>
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#include <device/pci_ops.h>
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#include <device/pci_def.h>
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#include <console/console.h>
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#include <cpu/x86/smm.h>
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#include <southbridge/intel/i82801gx/nvs.h>
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@ -16,25 +17,33 @@
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static void mainboard_smi_brightness_down(void)
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{
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u8 *bar;
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if ((bar = (u8 *)pci_read_config32(PCI_DEV(1, 0, 0), 0x18))) {
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printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, *(bar+LVTMA_BL_MOD_LEVEL));
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uint32_t reg32 = pci_read_config32(PCI_DEV(1, 0, 0), PCI_BASE_ADDRESS_2) & ~0xf;
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u8 *bar = (void *)(uintptr_t)reg32;
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/* Validate pointer before using it */
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if (!bar || smm_points_to_smram(bar, LVTMA_BL_MOD_LEVEL + sizeof(uint8_t)))
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return;
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printk(BIOS_DEBUG, "bar: %p, level %02X\n", bar, *(bar+LVTMA_BL_MOD_LEVEL));
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*(bar+LVTMA_BL_MOD_LEVEL) &= 0xf0;
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if (*(bar+LVTMA_BL_MOD_LEVEL) > 0x10)
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*(bar+LVTMA_BL_MOD_LEVEL) -= 0x10;
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}
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}
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static void mainboard_smi_brightness_up(void)
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{
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u8 *bar;
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if ((bar = (u8 *)pci_read_config32(PCI_DEV(1, 0, 0), 0x18))) {
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printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, *(bar+LVTMA_BL_MOD_LEVEL));
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uint32_t reg32 = pci_read_config32(PCI_DEV(1, 0, 0), PCI_BASE_ADDRESS_2) & ~0xf;
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u8 *bar = (void *)(uintptr_t)reg32;
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/* Validate pointer before using it */
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if (!bar || smm_points_to_smram(bar, LVTMA_BL_MOD_LEVEL + sizeof(uint8_t)))
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return;
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printk(BIOS_DEBUG, "bar: %p, level %02X\n", bar, *(bar+LVTMA_BL_MOD_LEVEL));
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*(bar+LVTMA_BL_MOD_LEVEL) |= 0x0f;
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if (*(bar+LVTMA_BL_MOD_LEVEL) < 0xf0)
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*(bar+LVTMA_BL_MOD_LEVEL) += 0x10;
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}
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}
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int mainboard_io_trap_handler(int smif)
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{
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@ -321,6 +321,10 @@ static void southbridge_smi_apmc(void)
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if (state) {
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/* EBX in the state save contains the GNVS pointer */
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gnvs = (struct global_nvs *)((uint32_t)state->rbx);
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if (smm_points_to_smram(gnvs, sizeof(*gnvs))) {
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printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n");
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return;
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}
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smm_initialized = 1;
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printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
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}
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@ -301,6 +301,10 @@ static void southbridge_smi_apmc(void)
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if (state) {
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/* EBX in the state save contains the GNVS pointer */
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gnvs = (struct global_nvs *)((uint32_t)state->rbx);
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if (smm_points_to_smram(gnvs, sizeof(*gnvs))) {
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printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n");
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return;
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}
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smm_initialized = 1;
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printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
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}
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@ -100,6 +100,10 @@ static void backlight_off(void)
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reg_base = (void *)((uintptr_t)pci_read_config32(SA_DEV_IGD,
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PCI_BASE_ADDRESS_0) & ~0xf);
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/* Validate pointer before using it */
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if (smm_points_to_smram(reg_base, PCH_PP_OFF_DELAYS + sizeof(uint32_t)))
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return;
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/* Check if backlight is enabled */
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pp_ctrl = read32(reg_base + PCH_PP_CONTROL);
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if (!(pp_ctrl & EDP_BLC_ENABLE))
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@ -341,6 +345,10 @@ static void southbridge_smi_apmc(void)
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if (state) {
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/* EBX in the state save contains the GNVS pointer */
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gnvs = (struct global_nvs *)((u32)state->rbx);
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if (smm_points_to_smram(gnvs, sizeof(*gnvs))) {
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printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n");
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return;
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}
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smm_initialized = 1;
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printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
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}
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@ -373,6 +373,10 @@ void smihandler_southbridge_apmc(
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/* EBX in the state save contains the GNVS pointer */
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uint32_t reg_ebx = save_state_ops->get_reg(state, RBX);
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gnvs = (struct global_nvs *)(uintptr_t)reg_ebx;
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if (smm_points_to_smram(gnvs, sizeof(*gnvs))) {
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printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n");
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return;
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}
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smm_initialized = 1;
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printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
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}
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@ -4,6 +4,7 @@
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#include <arch/io.h>
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#include <device/pci_ops.h>
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#include <console/console.h>
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#include <commonlib/region.h>
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#include <device/pci_def.h>
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#include <cpu/x86/smm.h>
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#include <cpu/intel/em64t101_save_state.h>
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@ -103,6 +104,7 @@ static void xhci_sleep(u8 slp_typ)
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xhci_bar = pci_read_config32(PCH_XHCI_DEV, PCI_BASE_ADDRESS_0) & ~0xFUL;
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/* FIXME: This looks broken (conditions are always false) */
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if ((xhci_bar + 0x4C0) & 1)
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pch_iobp_update(0xEC000082, ~0UL, (3 << 2));
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if ((xhci_bar + 0x4D0) & 1)
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@ -191,6 +193,11 @@ void southbridge_update_gnvs(u8 apm_cnt, int *smm_done)
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if (state) {
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/* EBX in the state save contains the GNVS pointer */
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gnvs = (struct global_nvs *)((u32)state->rbx);
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struct region r = {(uintptr_t)gnvs, sizeof(struct global_nvs)};
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if (smm_region_overlaps_handler(&r)) {
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printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n");
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return;
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}
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*smm_done = 1;
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printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
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}
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@ -152,6 +152,10 @@ void southbridge_update_gnvs(u8 apm_cnt, int *smm_done)
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if (state) {
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/* EBX in the state save contains the GNVS pointer */
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gnvs = (struct global_nvs *)((u32)state->rbx);
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if (smm_points_to_smram(gnvs, sizeof(*gnvs))) {
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printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n");
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return;
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}
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*smm_done = 1;
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printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
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}
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@ -314,6 +314,10 @@ static void southbridge_smi_apmc(void)
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if (state) {
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/* EBX in the state save contains the GNVS pointer */
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gnvs = (struct global_nvs *)((u32)state->rbx);
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if (smm_points_to_smram(gnvs, sizeof(*gnvs))) {
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printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n");
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return;
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}
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smm_initialized = 1;
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printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
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}
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