Kconfig: Unify power-after-failure options

The newest and most useful incarnation was hiding in soc/intel/common/.
We move it into the Mainboard menu and extend it with various flags to
be selected to control the default and which options are visible. Also
add a new `int` config MAINBOARD_POWER_FAILURE_STATE that moves the
boolean to int conversion into Kconfig:
  0 - S5
  1 - S0
  2 - previous state

This patch focuses on the Kconfig code. The C code could be unified as
well, e.g. starting with a common enum and safe wrapper around the
get_option() call.

TEST=Did what-jenkins-does with and without this commit and compared
     binaries. Nothing changed for the default configurations.

Change-Id: I61259f864c8a8cfc7099cc2699059f972fa056c0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

src/mainboard/Kconfig

@@ -177,3 +177,57 @@ config ENABLE_POWER_BUTTON
 config ENABLE_POWER_BUTTON
 	def_bool y if !POWER_BUTTON_IS_OPTIONAL && POWER_BUTTON_FORCE_ENABLE
 	def_bool n if !POWER_BUTTON_IS_OPTIONAL && POWER_BUTTON_FORCE_DISABLE
+
+config HAVE_POWER_STATE_AFTER_FAILURE
+	bool
+
+if HAVE_POWER_STATE_AFTER_FAILURE
+
+config HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
+	bool
+
+config POWER_STATE_DEFAULT_ON_AFTER_FAILURE
+	bool
+	help
+	  Selected by platforms or mainboards that want a "default on"
+	  behaviour.
+
+choice
+	prompt "System Power State after Failure"
+	default POWER_STATE_ON_AFTER_FAILURE \
+		if POWER_STATE_DEFAULT_ON_AFTER_FAILURE
+	default POWER_STATE_OFF_AFTER_FAILURE
+	help
+	  Provides a default for the power state the system should
+	  go into after G3 (power loss). On many boards this can be
+	  overridden by an NVRAM option.
+
+config POWER_STATE_OFF_AFTER_FAILURE
+	bool "S5 Soft Off"
+	help
+	  Choose this option if you want to put system into
+	  S5 after reapplying power after failure.
+
+config POWER_STATE_ON_AFTER_FAILURE
+	bool "S0 Full On"
+	help
+	  Choose this option if you want to keep system in
+	  S0 after reapplying power after failure.
+
+config POWER_STATE_PREVIOUS_AFTER_FAILURE
+	bool "Keep Previous State"
+	depends on HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
+	help
+	  Choose this option if you want to keep system in the
+	  same power state as before failure after reapplying
+	  power.
+
+endchoice
+
+config MAINBOARD_POWER_FAILURE_STATE
+	int
+	default 2 if POWER_STATE_PREVIOUS_AFTER_FAILURE
+	default 1 if POWER_STATE_ON_AFTER_FAILURE
+	default 0
+
+endif # HAVE_POWER_STATE_AFTER_FAILURE

src/mainboard/asrock/h81m-hds/Kconfig

@@ -64,11 +64,6 @@ config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 	hex
 	default 0x1849
 
-# This is overridden if CMOS is used for configuration values.
-config MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-	bool
-	default n
-
 config MAX_CPUS
 	int
 	default 8

src/mainboard/asus/kcma-d8/Kconfig

@@ -31,6 +31,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select DRIVERS_I2C_W83795
 	select DRIVERS_ASPEED_AST2050
 	select MAINBOARD_FORCE_NATIVE_VGA_INIT
+	select POWER_STATE_DEFAULT_ON_AFTER_FAILURE
 
 config MAINBOARD_DIR
 	string
@@ -89,10 +90,6 @@ config ONBOARD_VGA_IS_PRIMARY
 	bool
 	default y
 
-config MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-	bool
-	default y
-
 config MAX_REBOOT_CNT
 	int
 	default 10

src/mainboard/asus/kfsn4-dre/Kconfig

@@ -19,6 +19,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select ENABLE_APIC_EXT_ID
 	select DRIVERS_I2C_W83793
 	select DRIVERS_XGI_Z9S
+	select POWER_STATE_DEFAULT_ON_AFTER_FAILURE
 
 config MAINBOARD_DIR
 	string
@@ -80,10 +81,6 @@ config ONBOARD_VGA_IS_PRIMARY
 	bool
 	default y
 
-config MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-	bool
-	default y
-
 config MAX_REBOOT_CNT
 	int
 	default 10

src/mainboard/asus/kgpe-d16/Kconfig

@@ -32,6 +32,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select DRIVERS_I2C_W83795
 	select DRIVERS_ASPEED_AST2050
 	select MAINBOARD_FORCE_NATIVE_VGA_INIT
+	select POWER_STATE_DEFAULT_ON_AFTER_FAILURE
 
 config MAINBOARD_DIR
 	string
@@ -94,10 +95,6 @@ config VGA_BIOS_ID
 	string
 	default "1a03,2000"
 
-config MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-	bool
-	default y
-
 config MAX_REBOOT_CNT
 	int
 	default 10

src/mainboard/msi/ms9652_fam10/Kconfig

@@ -20,6 +20,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select LIFT_BSP_APIC_ID
 	select IOAPIC
 	select SMP
+	select POWER_STATE_DEFAULT_ON_AFTER_FAILURE
 
 config MAINBOARD_DIR
 	string
@@ -59,10 +60,6 @@ config DEFAULT_CONSOLE_LOGLEVEL
 	int
 	default 9
 
-config MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-	bool
-	default y
-
 config USBDEBUG
 	bool
 	default n

src/mainboard/samsung/lumpy/Kconfig

@@ -44,10 +44,6 @@ config VGA_BIOS_FILE
 	string
 	default "pci8086,0106.rom"
 
-config MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-	bool
-	default n
-
 if EARLY_PCI_BRIDGE
 
 config EARLY_PCI_BRIDGE_DEVICE

src/mainboard/samsung/stumpy/Kconfig

@@ -42,8 +42,4 @@ config VGA_BIOS_FILE
 	string
 	default "pci8086,0106.rom"
 
-config MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-	bool
-	default n
-
 endif # BOARD_SAMSUNG_STUMPY

src/soc/intel/broadwell/Kconfig

@@ -41,6 +41,8 @@ config CPU_SPECIFIC_OPTIONS
 	select INTEL_GMA_ACPI
 	select POSTCAR_STAGE
 	select POSTCAR_CONSOLE
+	select HAVE_POWER_STATE_AFTER_FAILURE
+	select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
 
 config PCIEXP_ASPM
 	bool

src/soc/intel/broadwell/lpc.c

@@ -152,7 +152,7 @@ static void pch_power_options(struct device *dev)
 	const char *state;
 	/* Get the chip configuration */
 	config_t *config = dev->chip_info;
-	int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+	int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
 
 	/* Which state do we want to goto after g3 (power restored)?
 	 * 0 == S0 Full On

src/soc/intel/broadwell/smihandler.c

@@ -152,7 +152,7 @@ static void southbridge_smi_sleep(void)
 	u8 reg8;
 	u32 reg32;
 	u8 slp_typ;
-	u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+	u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
 
 	/* save and recover RTC port values */
 	u8 tmp70, tmp72;

src/soc/intel/common/block/include/intelblocks/pmclib.h

@@ -213,6 +213,7 @@ void soc_fill_power_state(struct chipset_power_state *ps);
  * 0 == S5 Soft Off
  * 1 == S0 Full On
  * 2 == Keep Previous State
+ * Keep in sync with `config MAINBOARD_POWER_FAILURE_STATE`.
  */
 enum {
 	MAINBOARD_POWER_STATE_OFF,

src/soc/intel/common/block/pmc/Kconfig

@@ -2,35 +2,13 @@ config SOC_INTEL_COMMON_BLOCK_PMC
 	depends on SOC_INTEL_COMMON_BLOCK_GPIO
 	depends on ACPI_INTEL_HARDWARE_SLEEP_VALUES
 	bool
+	select HAVE_POWER_STATE_AFTER_FAILURE
+	select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
+	select POWER_STATE_DEFAULT_ON_AFTER_FAILURE
 	help
 	  Intel Processor common code for Power Management controller(PMC)
 	  subsystem
 
-choice
-	prompt "System Power State after Failure"
-	default POWER_STATE_ON_AFTER_FAILURE
-
-config POWER_STATE_OFF_AFTER_FAILURE
-	bool "S5 Soft Off"
-	help
-	  Choose this option if you want to keep system into
-	  S5 after reapplying power after failure
-
-config POWER_STATE_ON_AFTER_FAILURE
-	bool "S0 Full On"
-	help
-	  Choose this option if you want to keep system into
-	  S0 after reapplying power after failure
-
-config POWER_STATE_PREVIOUS_AFTER_FAILURE
-	bool "Keep Previous State"
-	help
-	  Choose this option if you want to keep system into
-	  same power state as before failure even after reapplying
-	  power
-
-endchoice
-
 config PMC_INVALID_READ_AFTER_WRITE
 	bool
 	default n

src/soc/intel/common/block/pmc/pmclib.c

@@ -587,10 +587,5 @@ void pmc_gpe_init(void)
  */
 int pmc_get_mainboard_power_failure_state_choice(void)
 {
-	if (IS_ENABLED(CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE))
+	return CONFIG_MAINBOARD_POWER_FAILURE_STATE;
-		return MAINBOARD_POWER_STATE_PREVIOUS;
-	else if (IS_ENABLED(CONFIG_POWER_STATE_ON_AFTER_FAILURE))
-		return MAINBOARD_POWER_STATE_ON;
-
-	return MAINBOARD_POWER_STATE_OFF;
 }

src/southbridge/amd/agesa/hudson/sm.c

@@ -30,10 +30,6 @@
 #define MAINBOARD_POWER_OFF 0
 #define MAINBOARD_POWER_ON 1
 
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
-#endif
-
 #define BIT0	(1 << 0)
 #define BIT1	(1 << 1)
 #define BIT2	(1 << 2)

src/southbridge/amd/amd8111/Kconfig

@@ -16,6 +16,7 @@
 config SOUTHBRIDGE_AMD_AMD8111
 	bool
 	select IOAPIC
+	select HAVE_POWER_STATE_AFTER_FAILURE
 
 config BOOTBLOCK_SOUTHBRIDGE_INIT
 	string

src/southbridge/amd/amd8111/acpi.c

@@ -29,11 +29,6 @@
 #define SLOW_CPU_OFF 0
 #define SLOW_CPU__ON 1
 
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
-#endif
-
-
 static int lsmbus_recv_byte(struct device *dev)
 {
 	unsigned int device;
@@ -148,7 +143,7 @@ static void acpi_init(struct device *dev)
 	pci_write_config8(dev, 0x41, byte | (1<<6)|(1<<5));
 
 	/* power on after power fail */
-	on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+	on = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
 	get_option(&on, "power_on_after_fail");
 	byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
 	byte &= ~0x40;

src/southbridge/amd/pi/hudson/sm.c

@@ -30,10 +30,6 @@
 #define MAINBOARD_POWER_OFF 0
 #define MAINBOARD_POWER_ON 1
 
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
-#endif
-
 /*
 * HUDSON enables all USB controllers by default in SMBUS Control.
 * HUDSON enables SATA by default in SMBUS Control.

src/southbridge/amd/sb700/Kconfig

@@ -23,6 +23,8 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy
 	select IOAPIC
 	select HAVE_USBDEBUG_OPTIONS
 	select SMBUS_HAS_AUX_CHANNELS
+	select HAVE_POWER_STATE_AFTER_FAILURE
+	select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
 
 config SOUTHBRIDGE_AMD_SB700_33MHZ_SPI
 	bool "Enable high speed SPI clock"

src/southbridge/amd/sb700/sm.c

@@ -44,10 +44,6 @@ enum power_mode {
 	POWER_MODE_LAST = 2,
 };
 
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL POWER_MODE_ON
-#endif
-
 static const char *power_mode_names[] = {
 	[POWER_MODE_OFF] = "off",
 	[POWER_MODE_ON] = "on",
@@ -152,11 +148,11 @@ static void sm_init(struct device *dev)
 	pm_iowrite(0x53, byte);
 
 	/* power after power fail */
-	power_state = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+	power_state = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
 	get_option(&power_state, "power_on_after_fail");
 	if (power_state > 2) {
 		printk(BIOS_WARNING, "Invalid power_on_after_fail setting, using default\n");
-		power_state = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+		power_state = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
 	}
 	byte = pm_ioread(0x74);
 	byte &= ~0x03;

src/southbridge/amd/sb800/sm.c

@@ -32,10 +32,6 @@
 #define MAINBOARD_POWER_OFF 0
 #define MAINBOARD_POWER_ON 1
 
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
-#endif
-
 #define BIT0	(1 << 0)
 #define BIT1	(1 << 1)
 #define BIT2	(1 << 2)

src/southbridge/intel/bd82x6x/lpc.c

@@ -181,7 +181,7 @@ static void pch_power_options(struct device *dev)
 	/* Get the chip configuration */
 	config_t *config = dev->chip_info;
 
-	int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+	int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
 	int nmi_option;
 
 	/* Which state do we want to goto after g3 (power restored)?

src/southbridge/intel/common/Kconfig

@@ -29,6 +29,8 @@ config HAVE_INTEL_CHIPSET_LOCKDOWN
 
 config SOUTHBRIDGE_INTEL_COMMON_SMM
 	def_bool n
+	select HAVE_POWER_STATE_AFTER_FAILURE
+	select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
 
 config SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT
 	bool

src/southbridge/intel/common/pmutil.h

@@ -45,10 +45,6 @@
 #define MAINBOARD_POWER_ON	1
 #define MAINBOARD_POWER_KEEP	2
 
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
-#endif
-
 #define PM1_STS		0x00
 #define   WAK_STS	(1 << 15)
 #define   PCIEXPWAK_STS	(1 << 14)

src/southbridge/intel/common/smihandler.c

@@ -112,7 +112,7 @@ static void southbridge_smi_sleep(void)
 	u8 reg8;
 	u32 reg32;
 	u8 slp_typ;
-	u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+	u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
 
 	// save and recover RTC port values
 	u8 tmp70, tmp72;

src/southbridge/intel/fsp_rangeley/soc.h

@@ -80,10 +80,6 @@ void rangeley_sb_early_initialization(void);
 #define MAINBOARD_POWER_ON	1
 #define MAINBOARD_POWER_KEEP	2
 
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
-#endif
-
 #define SOC_EHCI1_DEV		PCI_DEV(0, 0x1d, 0)
 #define PCIE_DEV_SLOT0	1
 #define PCIE_DEV_SLOT1	2

src/southbridge/intel/i82801dx/Kconfig

@@ -22,6 +22,8 @@ config SOUTHBRIDGE_INTEL_I82801DX
 	select HAVE_USBDEBUG
 	select SOUTHBRIDGE_INTEL_COMMON
 	select SOUTHBRIDGE_INTEL_COMMON_SMBUS
+	select HAVE_POWER_STATE_AFTER_FAILURE
+	select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
 
 if SOUTHBRIDGE_INTEL_I82801DX
 

src/southbridge/intel/i82801dx/i82801dx.h

@@ -45,10 +45,6 @@ int smbus_read_byte(unsigned device, unsigned address);
 #define MAINBOARD_POWER_ON	1
 #define MAINBOARD_POWER_KEEP	2
 
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
-#endif
-
 /*
  * 000 = Non-combined. P0 is primary master. P1 is secondary master.
  * 001 = Non-combined. P0 is secondary master. P1 is primary master.

src/southbridge/intel/i82801dx/lpc.c

@@ -103,7 +103,7 @@ static void i82801dx_power_options(struct device *dev)
 	u32 reg32;
 	const char *state;
 
-	int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+	int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
 	int nmi_option;
 
 	/* Which state do we want to goto after g3 (power restored)?

src/southbridge/intel/i82801dx/smihandler.c

@@ -276,7 +276,7 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
 	 * CMOS or even better from GNVS. Right now it's hard
 	 * coded at compile time.
 	 */
-	u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+	u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
 
 	/* First, disable further SMIs */
 	reg8 = inb(pmbase + SMI_EN);

src/southbridge/intel/i82801gx/i82801gx.h

@@ -58,10 +58,6 @@ int southbridge_detect_s3_resume(void);
 #define MAINBOARD_POWER_ON	1
 #define MAINBOARD_POWER_KEEP	2
 
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
-#endif
-
 /* PCI Configuration Space (D30:F0): PCI2PCI */
 #define PSTS	0x06
 #define SMLT	0x1b

src/southbridge/intel/i82801gx/lpc.c

@@ -172,7 +172,7 @@ static void i82801gx_power_options(struct device *dev)
 	/* Get the chip configuration */
 	config_t *config = dev->chip_info;
 
-	int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+	int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
 	int nmi_option;
 
 	/* Which state do we want to goto after g3 (power restored)?

src/southbridge/intel/i82801ix/i82801ix.h

@@ -85,11 +85,6 @@
 #define MAINBOARD_POWER_ON	1
 #define MAINBOARD_POWER_KEEP	2
 
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
-#endif
-
-
 /* D31:F0 LPC bridge */
 #define D31F0_PMBASE		0x40
 #define D31F0_ACPI_CNTL		0x44

src/southbridge/intel/i82801ix/lpc.c

@@ -170,7 +170,7 @@ static void i82801ix_power_options(struct device *dev)
 	/* Get the chip configuration */
 	config_t *config = dev->chip_info;
 
-	int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+	int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
 	int nmi_option;
 
 	/* BIOS must program... */

src/southbridge/intel/i82801jx/Kconfig

@@ -30,6 +30,8 @@ config SOUTHBRIDGE_INTEL_I82801JX
 	select COMMON_FADT
 	select SOUTHBRIDGE_INTEL_COMMON_SMM
 	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
+	select HAVE_POWER_STATE_AFTER_FAILURE
+	select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
 
 if SOUTHBRIDGE_INTEL_I82801JX
 

src/southbridge/intel/i82801jx/i82801jx.h

@@ -76,11 +76,6 @@
 #define MAINBOARD_POWER_ON	1
 #define MAINBOARD_POWER_KEEP	2
 
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
-#endif
-
-
 /* D31:F0 LPC bridge */
 #define D31F0_PMBASE		0x40
 #define PMBASE		D31F0_PMBASE

src/southbridge/intel/i82801jx/lpc.c

@@ -172,7 +172,7 @@ static void i82801jx_power_options(struct device *dev)
 	/* Get the chip configuration */
 	config_t *config = dev->chip_info;
 
-	int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+	int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
 	int nmi_option;
 
 	/* BIOS must program... */

src/southbridge/intel/ibexpeak/Kconfig

@@ -38,6 +38,8 @@ config SOUTH_BRIDGE_OPTIONS # dummy
 	select INTEL_DESCRIPTOR_MODE_CAPABLE
 	select SOUTHBRIDGE_INTEL_COMMON_GPIO
 	select HAVE_INTEL_CHIPSET_LOCKDOWN
+	select HAVE_POWER_STATE_AFTER_FAILURE
+	select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
 
 config EHCI_BAR
 	hex

src/southbridge/intel/ibexpeak/lpc.c

@@ -174,7 +174,7 @@ static void pch_power_options(struct device *dev)
 	/* Get the chip configuration */
 	config_t *config = dev->chip_info;
 
-	int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+	int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
 	int nmi_option;
 
 	/* Which state do we want to goto after g3 (power restored)?

src/southbridge/intel/ibexpeak/pch.h

@@ -82,10 +82,6 @@ void southbridge_configure_default_intmap(void);
 #define MAINBOARD_POWER_ON	1
 #define MAINBOARD_POWER_KEEP	2
 
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
-#endif
-
 /* PCI Configuration Space (D30:F0): PCI2PCI */
 #define PSTS	0x06
 #define SMLT	0x1b

src/southbridge/intel/ibexpeak/smihandler.c

@@ -403,7 +403,7 @@ static void southbridge_smi_sleep(void)
 	u8 reg8;
 	u32 reg32;
 	u8 slp_typ;
-	u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+	u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
 
 	// save and recover RTC port values
 	u8 tmp70, tmp72;

src/southbridge/intel/lynxpoint/Kconfig

@@ -39,6 +39,8 @@ config SOUTH_BRIDGE_OPTIONS # dummy
 	select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
 	select HAVE_INTEL_CHIPSET_LOCKDOWN
 	select COMMON_FADT
+	select HAVE_POWER_STATE_AFTER_FAILURE
+	select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
 
 config INTEL_LYNXPOINT_LP
 	bool

src/southbridge/intel/lynxpoint/lpc.c

@@ -189,7 +189,7 @@ static void pch_power_options(struct device *dev)
 	/* Get the chip configuration */
 	config_t *config = dev->chip_info;
 	u16 pmbase = get_pmbase();
-	int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+	int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
 	int nmi_option;
 
 	/* Which state do we want to goto after g3 (power restored)?

src/southbridge/intel/lynxpoint/pch.h

@@ -210,10 +210,6 @@ void mainboard_config_superio(void);
 #define MAINBOARD_POWER_ON	1
 #define MAINBOARD_POWER_KEEP	2
 
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
-#endif
-
 /* PCI Configuration Space (D30:F0): PCI2PCI */
 #define PSTS	0x06
 #define SMLT	0x1b

src/southbridge/intel/lynxpoint/smihandler.c

@@ -111,7 +111,7 @@ static void southbridge_smi_sleep(void)
 	u8 reg8;
 	u32 reg32;
 	u8 slp_typ;
-	u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+	u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
 	u16 pmbase = get_pmbase();
 
 	// save and recover RTC port values

src/southbridge/nvidia/ck804/Kconfig

@@ -2,6 +2,7 @@ config SOUTHBRIDGE_NVIDIA_CK804
 	bool
 	select HAVE_USBDEBUG
 	select IOAPIC
+	select HAVE_POWER_STATE_AFTER_FAILURE
 
 if SOUTHBRIDGE_NVIDIA_CK804
 

src/southbridge/nvidia/ck804/lpc.c

@@ -47,10 +47,6 @@
 #define SLOW_CPU_OFF 0
 #define SLOW_CPU__ON 1
 
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
-#endif
-
 static void lpc_common_init(struct device *dev)
 {
 	u32 dword;
@@ -114,7 +110,7 @@ static void lpc_init(struct device *dev)
 	printk(BIOS_INFO, "%s: pm_base = %x\n", __func__, pm_base);
 
 	/* Power after power fail */
-	on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+	on = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
 	get_option(&on, "power_on_after_fail");
 	byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
 	byte &= ~0x45;

src/southbridge/nvidia/mcp55/Kconfig

@@ -2,6 +2,7 @@ config SOUTHBRIDGE_NVIDIA_MCP55
 	bool
 	select HAVE_USBDEBUG
 	select IOAPIC
+	select HAVE_POWER_STATE_AFTER_FAILURE
 
 if SOUTHBRIDGE_NVIDIA_MCP55
 

src/southbridge/nvidia/mcp55/lpc.c

@@ -48,10 +48,6 @@
 #define SLOW_CPU_OFF		0
 #define SLOW_CPU__ON		1
 
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
-#endif
-
 static void lpc_common_init(struct device *dev, int master)
 {
 	u8 byte;
@@ -93,7 +89,7 @@ static void lpc_init(struct device *dev)
 	/* power after power fail */
 
 #if 1
-	on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+	on = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
 	get_option(&on, "power_on_after_fail");
 	byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
 	byte &= ~0x40;

src/superio/nuvoton/nct5572d/Kconfig

@@ -16,3 +16,5 @@
 config SUPERIO_NUVOTON_NCT5572D
 	bool
 	select SUPERIO_NUVOTON_COMMON_PRE_RAM
+	select HAVE_POWER_STATE_AFTER_FAILURE
+	select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE

src/superio/nuvoton/nct5572d/superio.c

@@ -28,12 +28,9 @@
 
 #include "nct5572d.h"
 
-#define MAINBOARD_POWER_OFF 0
+#define MAINBOARD_POWER_OFF	0
-#define MAINBOARD_POWER_ON 1
+#define MAINBOARD_POWER_ON	1
-
+#define MAINBOARD_POWER_KEEP	2
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
-#endif
 
 static void nct5572d_init(struct device *dev)
 {
@@ -68,16 +65,16 @@ static void nct5572d_init(struct device *dev)
 		break;
 	case NCT5572D_ACPI:
 		/* Set power state after power fail */
-		power_status = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+		power_status = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
 		get_option(&power_status, "power_on_after_fail");
 		pnp_enter_conf_mode_8787(dev);
 		pnp_set_logical_device(dev);
 		byte = pnp_read_config(dev, 0xe4);
 		byte &= ~0x60;
-		if (power_status == 1)
+		if (power_status == MAINBOARD_POWER_ON)
-			byte |= (0x1 << 5);    /* Force power on */
+			byte |= (0x1 << 5);
-		else if (power_status == 2)
+		else if (power_status == MAINBOARD_POWER_KEEP)
-			byte |= (0x2 << 5);    /* Use last power state */
+			byte |= (0x2 << 5);
 		pnp_write_config(dev, 0xe4, byte);
 		pnp_exit_conf_mode_aa(dev);
 		printk(BIOS_INFO, "set power %s after power fail\n", power_status ? "on" : "off");

src/superio/winbond/w83667hg-a/Kconfig

@@ -17,3 +17,5 @@
 config SUPERIO_WINBOND_W83667HG_A
 	bool
 	select SUPERIO_WINBOND_COMMON_PRE_RAM
+	select HAVE_POWER_STATE_AFTER_FAILURE
+	select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE

src/superio/winbond/w83667hg-a/superio.c

@@ -28,12 +28,9 @@
 
 #include "w83667hg-a.h"
 
-#define MAINBOARD_POWER_OFF 0
+#define MAINBOARD_POWER_OFF	0
-#define MAINBOARD_POWER_ON 1
+#define MAINBOARD_POWER_ON	1
-
+#define MAINBOARD_POWER_KEEP	2
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
-#endif
 
 static void w83667hg_a_init(struct device *dev)
 {
@@ -68,16 +65,16 @@ static void w83667hg_a_init(struct device *dev)
 		break;
 	case W83667HG_A_ACPI:
 		/* Set power state after power fail */
-		power_status = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+		power_status = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
 		get_option(&power_status, "power_on_after_fail");
 		pnp_enter_conf_mode_8787(dev);
 		pnp_set_logical_device(dev);
 		byte = pnp_read_config(dev, 0xe4);
 		byte &= ~0x60;
-		if (power_status == 1)
+		if (power_status == MAINBOARD_POWER_ON)
-			byte |= (0x1 << 5);    /* Force power on */
+			byte |= (0x1 << 5);
-		else if (power_status == 2)
+		else if (power_status == MAINBOARD_POWER_KEEP)
-			byte |= (0x2 << 5);    /* Use last power state */
+			byte |= (0x2 << 5);
 		pnp_write_config(dev, 0xe4, byte);
 		pnp_exit_conf_mode_aa(dev);
 		printk(BIOS_INFO, "set power %s after power fail\n", power_status ? "on" : "off");