Kconfig: Unify power-after-failure options

The newest and most useful incarnation was hiding in soc/intel/common/.
We move it into the Mainboard menu and extend it with various flags to
be selected to control the default and which options are visible. Also
add a new `int` config MAINBOARD_POWER_FAILURE_STATE that moves the
boolean to int conversion into Kconfig:
  0 - S5
  1 - S0
  2 - previous state

This patch focuses on the Kconfig code. The C code could be unified as
well, e.g. starting with a common enum and safe wrapper around the
get_option() call.

TEST=Did what-jenkins-does with and without this commit and compared
     binaries. Nothing changed for the default configurations.

Change-Id: I61259f864c8a8cfc7099cc2699059f972fa056c0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

src/southbridge/amd/agesa/hudson/sm.c

@@ -30,10 +30,6 @@
 #define MAINBOARD_POWER_OFF 0
 #define MAINBOARD_POWER_ON 1
 
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
-#endif
-
 #define BIT0	(1 << 0)
 #define BIT1	(1 << 1)
 #define BIT2	(1 << 2)

src/southbridge/amd/amd8111/Kconfig

@@ -16,6 +16,7 @@
 config SOUTHBRIDGE_AMD_AMD8111
 	bool
 	select IOAPIC
+	select HAVE_POWER_STATE_AFTER_FAILURE
 
 config BOOTBLOCK_SOUTHBRIDGE_INIT
 	string

src/southbridge/amd/amd8111/acpi.c

@@ -29,11 +29,6 @@
 #define SLOW_CPU_OFF 0
 #define SLOW_CPU__ON 1
 
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
-#endif
-
-
 static int lsmbus_recv_byte(struct device *dev)
 {
 	unsigned int device;
@@ -148,7 +143,7 @@ static void acpi_init(struct device *dev)
 	pci_write_config8(dev, 0x41, byte | (1<<6)|(1<<5));
 
 	/* power on after power fail */
-	on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+	on = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
 	get_option(&on, "power_on_after_fail");
 	byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
 	byte &= ~0x40;

src/southbridge/amd/pi/hudson/sm.c

@@ -30,10 +30,6 @@
 #define MAINBOARD_POWER_OFF 0
 #define MAINBOARD_POWER_ON 1
 
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
-#endif
-
 /*
 * HUDSON enables all USB controllers by default in SMBUS Control.
 * HUDSON enables SATA by default in SMBUS Control.

src/southbridge/amd/sb700/Kconfig

@@ -23,6 +23,8 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy
 	select IOAPIC
 	select HAVE_USBDEBUG_OPTIONS
 	select SMBUS_HAS_AUX_CHANNELS
+	select HAVE_POWER_STATE_AFTER_FAILURE
+	select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
 
 config SOUTHBRIDGE_AMD_SB700_33MHZ_SPI
 	bool "Enable high speed SPI clock"

src/southbridge/amd/sb700/sm.c

@@ -44,10 +44,6 @@ enum power_mode {
 	POWER_MODE_LAST = 2,
 };
 
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL POWER_MODE_ON
-#endif
-
 static const char *power_mode_names[] = {
 	[POWER_MODE_OFF] = "off",
 	[POWER_MODE_ON] = "on",
@@ -152,11 +148,11 @@ static void sm_init(struct device *dev)
 	pm_iowrite(0x53, byte);
 
 	/* power after power fail */
-	power_state = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+	power_state = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
 	get_option(&power_state, "power_on_after_fail");
 	if (power_state > 2) {
 		printk(BIOS_WARNING, "Invalid power_on_after_fail setting, using default\n");
-		power_state = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+		power_state = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
 	}
 	byte = pm_ioread(0x74);
 	byte &= ~0x03;

src/southbridge/amd/sb800/sm.c

@@ -32,10 +32,6 @@
 #define MAINBOARD_POWER_OFF 0
 #define MAINBOARD_POWER_ON 1
 
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
-#endif
-
 #define BIT0	(1 << 0)
 #define BIT1	(1 << 1)
 #define BIT2	(1 << 2)