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coreboot used to have two different "APIs" for memory accesses:

Browse Source 
read32(unsigned long addr) vs readl(void *addr)
and
write32(unsigned long addr, uint32_t value) vs writel(uint32_t value, void *addr)

read32 was only available in __PRE_RAM__ stage, while readl was used in stage2.
Some unclean implementations then made readl available to __PRE_RAM__ too which
results in really messy includes and code.

This patch fixes all code to use the read32/write32 variant, so that we can
remove readl/writel in another patch.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5022 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
2010-01-16 17:53:38 +00:00
committed by Stefan Reinauer
parent 984e0f3a0c
commit 9fe4d797a3
32 changed files with 264 additions and 219 deletions
Download Patch File Download Diff File Expand all files Collapse all files

22
src/southbridge/amd/cs5536/cs5536.c
View File

@@ -428,10 +428,10 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
bar = (uint8_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0);
/* Make HCCPARAMS writeable */
writel(readl(bar + IPREG04) | USB_HCCPW_SET, bar + IPREG04);
write32(bar + IPREG04, read32(bar + IPREG04) | USB_HCCPW_SET);
/* ; EECP=50h, IST=01h, ASPC=1 */
writel(0x00005012, bar + HCCPARAMS);
write32(bar + HCCPARAMS, 0x00005012);
}
dev = dev_find_device(PCI_VENDOR_ID_AMD,
@@ -439,19 +439,19 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
if (dev) {
bar = (uint8_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0);
writel(readl(bar + UOCMUX) & PUEN_SET, bar + UOCMUX);
write32(bar + UOCMUX, read32(bar + UOCMUX) & PUEN_SET);
/* Host or Device? */
if (sb->enable_USBP4_device) {
writel(readl(bar + UOCMUX) | PMUX_DEVICE, bar + UOCMUX);
write32(bar + UOCMUX, read32(bar + UOCMUX) | PMUX_DEVICE);
} else {
writel(readl(bar + UOCMUX) | PMUX_HOST, bar + UOCMUX);
write32(bar + UOCMUX, read32(bar + UOCMUX) | PMUX_HOST);
}
/* Overcurrent configuration */
if (sb->enable_USBP4_overcurrent) {
writel(readl(bar + UOCCAP)
| sb->enable_USBP4_overcurrent, bar + UOCCAP);
write32(bar + UOCCAP, read32(bar + UOCCAP)
| sb->enable_USBP4_overcurrent);
}
}
@@ -467,8 +467,8 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
if (dev) {
bar = (uint8_t *) pci_read_config32(dev,
PCI_BASE_ADDRESS_0);
writel(readl(bar + UDCDEVCTL) | UDC_SD_SET,
bar + UDCDEVCTL);
write32(bar + UDCDEVCTL,
read32(bar + UDCDEVCTL) | UDC_SD_SET);
}
@@ -477,8 +477,8 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
if (dev) {
bar = (uint8_t *) pci_read_config32(dev,
PCI_BASE_ADDRESS_0);
writel(readl(bar + UOCCTL) | PADEN_SET, bar + UOCCTL);
writel(readl(bar + UOCCAP) | APU_SET, bar + UOCCAP);
write32(bar + UOCCTL, read32(bar + UOCCTL) | PADEN_SET);
write32(bar + UOCCAP, read32(bar + UOCCAP) | APU_SET);
}
}