From a006c5522d4e0c0e8e3a29d5fa124f6dc080f306 Mon Sep 17 00:00:00 2001
From: Nick Vaccaro <nvaccaro@google.com>
Date: Mon, 28 Aug 2023 09:16:41 -0700
Subject: [PATCH] Revert "mb/google/brya: fix MRC cache failure for hynix
 parts"

This change causes a freeze during boot on an RPL-UR that does not have
the memory part string in the CBI.

BUG=b:296353047
BRANCH=firmware-brya-14505.B
TEST='emerge-brya coreboot chromeos-bootimage', flash and boot
problematic DUT to kernel.

This reverts commit c51a7cdde4e1cb9014be401136c3f07f220ef365.

Change-Id: I99fe5111b5294673d9e0a5d13f9c240e0f4a92c3
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77516
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: <srinivas.kulkarni@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../brya/variants/baseboard/brya/memory.c     | 75 -------------------
 1 file changed, 75 deletions(-)

diff --git a/src/mainboard/google/brya/variants/baseboard/brya/memory.c b/src/mainboard/google/brya/variants/baseboard/brya/memory.c
index 82605f901f..bcad9b4be9 100644
--- a/src/mainboard/google/brya/variants/baseboard/brya/memory.c
+++ b/src/mainboard/google/brya/variants/baseboard/brya/memory.c
@@ -2,10 +2,7 @@
 
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
-#include <console/console.h>
 #include <gpio.h>
-#include <memory_info.h>
-#include <string.h>
 
 static const struct mb_cfg baseboard_memcfg = {
 	.type = MEM_TYPE_LP4X,
@@ -69,80 +66,8 @@ static const struct mb_cfg baseboard_memcfg = {
 	.ect = 1, /* Enable Early Command Training */
 };
 
-static const struct mb_cfg hynix_memcfg = {
-	.type = MEM_TYPE_LP4X,
-
-	.rcomp = {
-		/* Baseboard uses only 100ohm Rcomp resistors */
-		.resistor = 100,
-
-		/* Baseboard Rcomp target values */
-		.targets = {40, 30, 30, 30, 30},
-	},
-
-	/* DQ byte map */
-	.lpx_dq_map = {
-		.ddr0 = {
-			.dq0 = {  9, 11,  8, 10, 12, 14, 13, 15, },
-			.dq1 = {  4,  7,  6,  5,  2,  3,  0,  1, },
-		},
-		.ddr1 = {
-			.dq0 = { 15, 12, 14, 13,  9, 10, 11,  8, },
-			.dq1 = {  0,  1,  3,  2,  7,  5,  4,  6, },
-		},
-		.ddr2 = {
-			.dq0 = {  2,  3,  1,  0,  6,  7,  5,  4, },
-			.dq1 = { 15,  9, 14,  8, 11, 10, 13, 12, },
-		},
-		.ddr3 = {
-			.dq0 = {  3,  1,  2,  0,  4,  6,  7,  5, },
-			.dq1 = { 13, 15, 14, 12, 11,  9,  8, 10, },
-		},
-		.ddr4 = {
-			.dq0 = { 13, 12, 14, 15,  9,  8, 10, 11, },
-			.dq1 = {  4,  7,  5,  6,  1,  2,  0,  3, },
-		},
-		.ddr5 = {
-			.dq0 = {  5,  0,  6,  4,  3,  1,  7,  2, },
-			.dq1 = { 11,  9, 10,  8, 15, 12, 14, 13, },
-		},
-		.ddr6 = {
-			.dq0 = { 15, 12, 14, 13, 10,  9, 11,  8, },
-			.dq1 = {  0,  1,  2,  3,  5,  6,  4,  7, },
-		},
-		.ddr7 = {
-			.dq0 = {  0,  3,  1,  2,  4,  5,  6,  7, },
-			.dq1 = { 11,  8, 13, 14,  9, 12, 15, 10, },
-		},
-	},
-
-	/* DQS CPU<>DRAM map */
-	.lpx_dqs_map = {
-		.ddr0 = { .dqs0 = 1, .dqs1 = 0 },
-		.ddr1 = { .dqs0 = 1, .dqs1 = 0 },
-		.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
-		.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
-		.ddr4 = { .dqs0 = 1, .dqs1 = 0 },
-		.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
-		.ddr6 = { .dqs0 = 1, .dqs1 = 0 },
-		.ddr7 = { .dqs0 = 0, .dqs1 = 1 },
-	},
-
-	.ect = 1, /* Enable Early Command Training */
-
-	.cs_pi_start_high_in_ect = 1
-};
-
 const struct mb_cfg *__weak variant_memory_params(void)
 {
-	const char *part_num = mainboard_get_dram_part_num();
-	const char *hynix_mem1 = "H54G46CYRBX267";
-	const char *hynix_mem2 = "H54G56CYRBX247";
-
-	if (!strcmp(part_num, hynix_mem1) || !strcmp(part_num, hynix_mem2)) {
-		printk(BIOS_INFO, "Enable cs_pi_start_high_in_ect for Hynix memory\n");
-		return &hynix_memcfg;
-	}
 	return &baseboard_memcfg;
 }