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arch/ppc64: Fix inline assembly for clang

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Use macros from the Linux kernel 6.5 to make the inline assembly also
compile on clang.

TEST: See that the generated code is identical on GCC and compiles on
clang.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I516033c69e62dfdb38f83285c156d5527917ad55
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
This commit is contained in:
Arthur Heymans
2023-10-17 11:36:11 -07:00
committed by Martin L Roth
parent 347b1170fb
commit a010b7f614
1 changed files with 6 additions and 1 deletions
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7
src/arch/ppc64/stages.c
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@@ -25,10 +25,15 @@ void stage_entry(uintptr_t stage_arg)
_cbmem_top_ptr = stage_arg; _cbmem_top_ptr = stage_arg;
#if ENV_RAMSTAGE #if ENV_RAMSTAGE
#define __stringify_in_c(...) #__VA_ARGS__
#define stringify_in_c(...) __stringify_in_c(__VA_ARGS__) " "
#define PPC_RAW_SLBIA(IH) (0x7c0003e4 | (((IH) & 0x7) << 21))
#define PPC_SLBIA(IH) stringify_in_c(.long PPC_RAW_SLBIA(IH))
hrmor = read_spr(SPR_HRMOR); hrmor = read_spr(SPR_HRMOR);
asm volatile("sync; isync" ::: "memory"); asm volatile("sync; isync" ::: "memory");
write_spr(SPR_HRMOR, 0); write_spr(SPR_HRMOR, 0);
asm volatile("or 1,1,%0; slbia 7; sync; isync" :: "r"(hrmor) : "memory"); asm volatile("or 1,1,%0;" PPC_SLBIA(7)"; sync; isync" :: "r"(hrmor) : "memory");
#endif #endif
main(); main();