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rockchip/rk3399: update the ddr 200MHz frequency configuration

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This patch updates the coreboot DDR Settings to match the configuration
used by ARM-Trusted-Firmware.

Change-Id: I34bc2950a9708ac89a5637bf682551e03d993fcc
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-on: https://review.coreboot.org/20304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit is contained in:
Caesar Wang 2017-06-22 16:14:58 +08:00 committed by Martin Roth
parent d55f5ebe44
commit a0199d8e1a
1 changed files with 1 additions and 1 deletions
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2
src/soc/rockchip/rk3399/clock.c
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@ -636,7 +636,7 @@ void rkclk_configure_ddr(unsigned int hz)
switch (hz) { switch (hz) {
case 200*MHz: case 200*MHz:
dpll_cfg = (struct pll_div) dpll_cfg = (struct pll_div)
{.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1}; {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 2};
break; break;
case 300*MHz: case 300*MHz:
dpll_cfg = (struct pll_div) dpll_cfg = (struct pll_div)