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soc/amd/picasso: Introduce enums for SPI read mode and speed

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This change adds enums for spi_read_mode and spi100_speed in
preparation for adding these to chip.h in follow-up CLs. This makes it
easier to reference what the mainboard is expected to set for these
SPI configs.

BUG=b:147758054,b:153675510
BRANCH=trembyle-bringup
TEST=Verified that SPI configuration is correct for trembyle.

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I7f9778b41bd059a50f20993415ebd8702a1ad58e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40823
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Furquan Shaikh
2020-04-28 18:45:20 -07:00
parent 73716d0e92
commit a0284db08d
2 changed files with 41 additions and 26 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
src/soc/amd/picasso/southbridge.c
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@@ -214,11 +214,8 @@ static uintptr_t sb_init_spi_base(void)
void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm)
{
uintptr_t base = sb_init_spi_base();
write16((void *)(base + SPI100_SPEED_CONFIG),
(norm << SPI_NORM_SPEED_NEW_SH) |
(fast << SPI_FAST_SPEED_NEW_SH) |
(alt << SPI_ALT_SPEED_NEW_SH) |
(tpm << SPI_TPM_SPEED_NEW_SH));
write16((void *)(base + SPI100_SPEED_CONFIG), SPI_SPEED_CFG(norm, fast, alt, tpm));
write16((void *)(base + SPI100_ENABLE), SPI_USE_SPI100);
}
@@ -233,9 +230,9 @@ void sb_disable_4dw_burst(void)
void sb_read_mode(u32 mode)
{
uintptr_t base = sb_init_spi_base();
write32((void *)(base + SPI_CNTRL0),
(read32((void *)(base + SPI_CNTRL0))
& ~SPI_READ_MODE_MASK) | mode);
uint32_t val = (read32((void *)(base + SPI_CNTRL0)) & ~SPI_READ_MODE_MASK);
write32((void *)(base + SPI_CNTRL0), val | SPI_READ_MODE(mode));
}
static void fch_smbus_init(void)