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siemens/mc_apl1: Make DRAM configuration more flexible

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By storing the FSP-M DRAM configuration parameter in the hwinfo block,
one becomes more flexible in case of a change of the DRAM type.
The configuration data from hwinfo block is a one-to-one representation
of the FSPM_UPD data starting with parameter 'Package' (offset 0x4d) and
ending before parameter 'Ch0_Bit_swizzling' (offset 0x88).

Change-Id: I58c1df0954a436710ecb59487ece07a0832b0de6
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/25586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This commit is contained in:
Mario Scheithauer
2018-04-10 12:57:02 +02:00
committed by Martin Roth
parent 8f031d8234
commit a0437b7563
1 changed files with 27 additions and 56 deletions
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83
src/mainboard/siemens/mc_apl1/romstage.c
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@@ -14,6 +14,9 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <console/console.h>
#include <hwilib.h>
#include <lib.h>
#include <string.h> #include <string.h>
#include <soc/romstage.h> #include <soc/romstage.h>
#include <fsp/api.h> #include <fsp/api.h>
@@ -48,67 +51,34 @@ static const uint8_t Ch3_Bit_swizzling[] = {
void mainboard_memory_init_params(FSPM_UPD *memupd) void mainboard_memory_init_params(FSPM_UPD *memupd)
{ {
const struct pad_config *pads; const struct pad_config *pads;
uint8_t spd[0x80];
size_t num; size_t num;
/* setup early gpio before memory */ /* setup early gpio before memory */
pads = brd_early_gpio_table(&num); pads = brd_early_gpio_table(&num);
gpio_configure_pads(pads, num); gpio_configure_pads(pads, num);
/* DRAM Config settings */ /* Get DRAM configuration data from hwinfo block.
memupd->FspmConfig.Package = 0x1; * The configuration data from hwinfo block is a one-to-one
memupd->FspmConfig.Profile = 0x19; * representation of the FSPM_UPD data starting with parameter
memupd->FspmConfig.MemoryDown = 0x5; * 'Package' (offset 0x4d) and ending before parameter
memupd->FspmConfig.DDR3LPageSize = 0x2; * 'Ch0_Bit_swizzling' (offset 0x88).
memupd->FspmConfig.DDR3LASR = 0x0; */
memupd->FspmConfig.ScramblerSupport = 0x0; if (hwilib_find_blocks("hwinfo.hex")) {
memupd->FspmConfig.ChannelHashMask = 0x0; printk(BIOS_ERR,
memupd->FspmConfig.SliceHashMask = 0x0; "HWInfo not found, use default values for FSP-M.\n");
memupd->FspmConfig.InterleavedMode = 0x0; return;
memupd->FspmConfig.ChannelsSlicesEnable = 0x0; }
memupd->FspmConfig.MinRefRate2xEnable = 0x1;
memupd->FspmConfig.DualRankSupportEnable = 0x1; if (hwilib_get_field(SPD, spd, sizeof(spd)) != sizeof(spd)) {
memupd->FspmConfig.RmtMode = 0x0; printk(BIOS_ERR,
memupd->FspmConfig.MemorySizeLimit = 0x1000; "SPD not found in HWInfo, use defaults for FSP-M.\n");
memupd->FspmConfig.LowMemoryMaxValue = 0x0; return;
memupd->FspmConfig.DisableFastBoot = 0x0; }
memupd->FspmConfig.HighMemoryMaxValue = 0x0;
memupd->FspmConfig.DIMM0SPDAddress = 0x0; memcpy(&memupd->FspmConfig.Package, &spd,
memupd->FspmConfig.DIMM1SPDAddress = 0x0; (((uint8_t *)memupd->FspmConfig.Ch0_Bit_swizzling)-
memupd->FspmConfig.Ch0_RankEnable = 0x1; (&memupd->FspmConfig.Package)));
memupd->FspmConfig.Ch0_DeviceWidth = 0x1;
memupd->FspmConfig.Ch0_DramDensity = 0x0;
memupd->FspmConfig.Ch0_Option = 0x3;
memupd->FspmConfig.Ch0_OdtConfig = 0x1;
memupd->FspmConfig.Ch0_TristateClk1 = 0x0;
memupd->FspmConfig.Ch0_Mode2N = 0x0;
memupd->FspmConfig.Ch0_OdtLevels = 0x0;
memupd->FspmConfig.Ch1_RankEnable = 0x1;
memupd->FspmConfig.Ch1_DeviceWidth = 0x1;
memupd->FspmConfig.Ch1_DramDensity = 0x0;
memupd->FspmConfig.Ch1_Option = 0x3;
memupd->FspmConfig.Ch1_OdtConfig = 0x1;
memupd->FspmConfig.Ch1_TristateClk1 = 0x0;
memupd->FspmConfig.Ch1_Mode2N = 0x0;
memupd->FspmConfig.Ch1_OdtLevels = 0x0;
memupd->FspmConfig.Ch2_RankEnable = 0x0;
memupd->FspmConfig.Ch2_DeviceWidth = 0x1;
memupd->FspmConfig.Ch2_DramDensity = 0x0;
memupd->FspmConfig.Ch2_Option = 0x3;
memupd->FspmConfig.Ch2_OdtConfig = 0x0;
memupd->FspmConfig.Ch2_TristateClk1 = 0x0;
memupd->FspmConfig.Ch2_Mode2N = 0x0;
memupd->FspmConfig.Ch2_OdtLevels = 0x0;
memupd->FspmConfig.Ch3_RankEnable = 0x0;
memupd->FspmConfig.Ch3_DeviceWidth = 0x1;
memupd->FspmConfig.Ch3_DramDensity = 0x0;
memupd->FspmConfig.Ch3_Option = 0x3;
memupd->FspmConfig.Ch3_OdtConfig = 0x0;
memupd->FspmConfig.Ch3_TristateClk1 = 0x0;
memupd->FspmConfig.Ch3_Mode2N = 0x0;
memupd->FspmConfig.Ch3_OdtLevels = 0x0;
memupd->FspmConfig.RmtCheckRun = 0x3;
memupd->FspmConfig.MrcDataSaving = 0x0;
memupd->FspmConfig.MrcFastBoot = 0x1;
memcpy(memupd->FspmConfig.Ch0_Bit_swizzling, &Ch0_Bit_swizzling, memcpy(memupd->FspmConfig.Ch0_Bit_swizzling, &Ch0_Bit_swizzling,
sizeof(Ch0_Bit_swizzling)); sizeof(Ch0_Bit_swizzling));
@@ -119,6 +89,7 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
memcpy(memupd->FspmConfig.Ch3_Bit_swizzling, &Ch3_Bit_swizzling, memcpy(memupd->FspmConfig.Ch3_Bit_swizzling, &Ch3_Bit_swizzling,
sizeof(Ch3_Bit_swizzling)); sizeof(Ch3_Bit_swizzling));
memupd->FspmConfig.RmtMarginCheckScaleHighThreshold = 0xC8;
memupd->FspmConfig.MsgLevelMask = 0x0; memupd->FspmConfig.MsgLevelMask = 0x0;
memupd->FspmConfig.MrcDataSaving = 0x0;
memupd->FspmConfig.MrcFastBoot = 0x1;
} }