mb/google/brya/var/xol: Override TDP PL1 value

Update TDP PL1 value for the DTT optimization. The new value 18W is from
internal thermal/performance team.
- tdp_pl1_override: 15 -> 18 (W)

BUG=b:336684032
BRANCH=brya
TEST=built and verified MSR PL1 value.
     Intel doc #614179 introduces how to check current PL values.

[Original MSR PL1/PL2/PL4 register values for xol]
cd /sys/class/powercap/intel-rapl/intel-rapl\:0/
grep . *power_limit*
  constraint_0_power_limit_uw:15000000 <= MSR PL1 (15W)
  constraint_1_power_limit_uw:55000000 <= MSR PL2 (55W)
  constraint_2_power_limit_uw:114000000 <= MSR PL4 (114W)

After this patch:
  constraint_0_power_limit_uw:18000000
  constraint_1_power_limit_uw:55000000
  constraint_2_power_limit_uw:114000000

Change-Id: I28c4f099e0169e8389f63083c03023dd8338589f
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82151
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/brya/variants/xol/overridetree.cb

@@ -25,6 +25,12 @@ chip soc/intel/alderlake
 	# display flickering issue.
 	register "disable_dynamic_tccold_handshake" = "true"
 
+	register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{
+		.tdp_pl1_override = 18,
+		.tdp_pl2_override = 55,
+		.tdp_pl4 = 114,
+	}"
+
 	register "tcc_offset" = "6"	# TCC of 94
 
 	register "platform_pmax" = "122"