soc/intel/cannonlake: Make correct IRQ mapping for CNL SA and PCH PCI devices

This patch provides option for PCI IRQ mapping in both PIC and APIC mode.

TEST=Build and Boot on CNL RVP.

Change-Id: Ie26750ac9dc2ce940b0c116085c041de439075df
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/28799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/soc/intel/cannonlake/acpi/irqlinks.asl

@@ -0,0 +1,282 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * PIRQ routing control is in PCR ITSS region.
+ *
+ * Due to what appears to be an ACPI interpreter bug we do not use
+ * the PCRB() method here as it may not be defined yet because the method
+ * definiton depends on the order of the include files in pch.asl.
+ *
+ * https://bugs.acpica.org/show_bug.cgi?id=1201
+ */
+OperationRegion (ITSS, SystemMemory,
+		 Add (PCR_ITSS_PIRQA_ROUT,
+		      Add (CONFIG_PCR_BASE_ADDRESS,
+		           ShiftLeft (PID_ITSS, PCR_PORTID_SHIFT))), 8)
+Field (ITSS, ByteAcc, NoLock, Preserve)
+{
+	PIRA, 8,	/* PIRQA Routing Control */
+	PIRB, 8,	/* PIRQB Routing Control */
+	PIRC, 8,	/* PIRQC Routing Control */
+	PIRD, 8,	/* PIRQD Routing Control */
+	PIRE, 8,	/* PIRQE Routing Control */
+	PIRF, 8,	/* PIRQF Routing Control */
+	PIRG, 8,	/* PIRQG Routing Control */
+	PIRH, 8,	/* PIRQH Routing Control */
+}
+
+Name (IREN, 0x80)	/* Interrupt Routing Enable */
+Name (IREM, 0x0f)	/* Interrupt Routing Mask */
+
+Device (LNKA)
+{
+	Name (_HID, EISAID ("PNP0C0F"))
+	Name (_UID, 1)
+
+	Method (_CRS, 0, Serialized)
+	{
+		Name (RTLA, ResourceTemplate ()
+		{
+			IRQ (Level, ActiveLow, Shared) {11}
+		})
+		CreateWordField (RTLA, 1, IRQ0)
+		Store (Zero, IRQ0)
+
+		/* Set the bit from PIRQ Routing Register */
+		ShiftLeft (1, And (^^PIRA, ^^IREM), IRQ0)
+
+		Return (RTLA)
+	}
+
+	Method (_STA, 0, Serialized)
+	{
+		If (And (^^PIRA, ^^IREN)) {
+			Return (0x9)
+		} Else {
+			Return (0xb)
+		}
+	}
+}
+
+Device (LNKB)
+{
+	Name (_HID, EISAID ("PNP0C0F"))
+	Name (_UID, 2)
+
+	Method (_CRS, 0, Serialized)
+	{
+		Name (RTLB, ResourceTemplate ()
+		{
+			IRQ (Level, ActiveLow, Shared) {10}
+		})
+		CreateWordField (RTLB, 1, IRQ0)
+		Store (Zero, IRQ0)
+
+		/* Set the bit from PIRQ Routing Register */
+		ShiftLeft (1, And (^^PIRB, ^^IREM), IRQ0)
+
+		Return (RTLB)
+	}
+
+	Method (_STA, 0, Serialized)
+	{
+		If (And (^^PIRB, ^^IREN)) {
+			Return (0x9)
+		} Else {
+			Return (0xb)
+		}
+	}
+}
+
+Device (LNKC)
+{
+	Name (_HID, EISAID ("PNP0C0F"))
+	Name (_UID, 3)
+
+	Method (_CRS, 0, Serialized)
+	{
+		Name (RTLC, ResourceTemplate ()
+		{
+			IRQ (Level, ActiveLow, Shared) {11}
+		})
+		CreateWordField (RTLC, 1, IRQ0)
+		Store (Zero, IRQ0)
+
+		/* Set the bit from PIRQ Routing Register */
+		ShiftLeft (1, And (^^PIRC, ^^IREM), IRQ0)
+
+		Return (RTLC)
+	}
+
+	Method (_STA, 0, Serialized)
+	{
+		If (And (^^PIRC, ^^IREN)) {
+			Return (0x9)
+		} Else {
+			Return (0xb)
+		}
+	}
+}
+
+Device (LNKD)
+{
+	Name (_HID, EISAID ("PNP0C0F"))
+	Name (_UID, 4)
+
+	Method (_CRS, 0, Serialized)
+	{
+		Name (RTLD, ResourceTemplate ()
+		{
+			IRQ (Level, ActiveLow, Shared) {11}
+		})
+		CreateWordField (RTLD, 1, IRQ0)
+		Store (Zero, IRQ0)
+
+		/* Set the bit from PIRQ Routing Register */
+		ShiftLeft (1, And (^^PIRD, ^^IREM), IRQ0)
+
+		Return (RTLD)
+	}
+
+	Method (_STA, 0, Serialized)
+	{
+		If (And (^^PIRD, ^^IREN)) {
+			Return (0x9)
+		} Else {
+			Return (0xb)
+		}
+	}
+}
+
+Device (LNKE)
+{
+	Name (_HID, EISAID ("PNP0C0F"))
+	Name (_UID, 5)
+
+	Method (_CRS, 0, Serialized)
+	{
+		Name (RTLE, ResourceTemplate ()
+		{
+			IRQ (Level, ActiveLow, Shared) {11}
+		})
+		CreateWordField (RTLE, 1, IRQ0)
+		Store (Zero, IRQ0)
+
+		/* Set the bit from PIRQ Routing Register */
+		ShiftLeft (1, And (^^PIRE, ^^IREM), IRQ0)
+
+		Return (RTLE)
+	}
+
+	Method (_STA, 0, Serialized)
+	{
+		If (And (^^PIRE, ^^IREN)) {
+			Return (0x9)
+		} Else {
+			Return (0xb)
+		}
+	}
+}
+
+Device (LNKF)
+{
+	Name (_HID, EISAID ("PNP0C0F"))
+	Name (_UID, 6)
+
+	Method (_CRS, 0, Serialized)
+	{
+		Name (RTLF, ResourceTemplate ()
+		{
+			IRQ (Level, ActiveLow, Shared) {11}
+		})
+		CreateWordField (RTLF, 1, IRQ0)
+		Store (Zero, IRQ0)
+
+		/* Set the bit from PIRQ Routing Register */
+		ShiftLeft (1, And (^^PIRF, ^^IREM), IRQ0)
+
+		Return (RTLF)
+	}
+
+	Method (_STA, 0, Serialized)
+	{
+		If (And (^^PIRF, ^^IREN)) {
+			Return (0x9)
+		} Else {
+			Return (0xb)
+		}
+	}
+}
+
+Device (LNKG)
+{
+	Name (_HID, EISAID ("PNP0C0F"))
+	Name (_UID, 7)
+
+	Method (_CRS, 0, Serialized)
+	{
+		Name (RTLG, ResourceTemplate ()
+		{
+			IRQ (Level, ActiveLow, Shared) {11}
+		})
+		CreateWordField (RTLG, 1, IRQ0)
+		Store (Zero, IRQ0)
+
+		/* Set the bit from PIRQ Routing Register */
+		ShiftLeft (1, And (^^PIRG, ^^IREM), IRQ0)
+
+		Return (RTLG)
+	}
+
+	Method (_STA, 0, Serialized)
+	{
+		If (And (^^PIRG, ^^IREN)) {
+			Return (0x9)
+		} Else {
+			Return (0xb)
+		}
+	}
+}
+
+Device (LNKH)
+{
+	Name (_HID, EISAID ("PNP0C0F"))
+	Name (_UID, 8)
+
+	Method (_CRS, 0, Serialized)
+	{
+		Name (RTLH, ResourceTemplate ()
+		{
+			IRQ (Level, ActiveLow, Shared) {11}
+		})
+		CreateWordField (RTLH, 1, IRQ0)
+		Store (Zero, IRQ0)
+
+		/* Set the bit from PIRQ Routing Register */
+		ShiftLeft (1, And (^^PIRH, ^^IREM), IRQ0)
+
+		Return (RTLH)
+	}
+
+	Method (_STA, 0, Serialized)
+	{
+		If (And (^^PIRH, ^^IREN)) {
+			Return (0x9)
+		} Else {
+			Return (0xb)
+		}
+	}
+}

src/soc/intel/cannonlake/acpi/pci_irqs.asl

@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2017 Intel Corp.
+ * Copyright (C) 2017-2018 Intel Corp.
  * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
  *
  * This program is free software; you can redistribute it and/or modify
@@ -15,85 +15,127 @@
  * GNU General Public License for more details.
  */
 
-Method(_PRT)
+#include <soc/irq.h>
+
+Name (PICP, Package () {
+	/* PCI Bridge */
+	/* cAVS, SMBus, GbE, Nothpeak */
+	Package(){0x001FFFFF, 0, 0, cAVS_INTA_IRQ },
+	Package(){0x001FFFFF, 1, 0, SMBUS_INTB_IRQ },
+	Package(){0x001FFFFF, 2, 0, GbE_INTC_IRQ },
+	Package(){0x001FFFFF, 3, 0, TRACE_HUB_INTD_IRQ },
+	/* SerialIo and SCS */
+	Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ },
+	Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ },
+	Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ },
+	Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ },
+	/* PCI Express Port 9-16 */
+	Package(){0x001DFFFF, 0, 0, PCIE_9_IRQ },
+	Package(){0x001DFFFF, 1, 0, PCIE_10_IRQ },
+	Package(){0x001DFFFF, 2, 0, PCIE_11_IRQ },
+	Package(){0x001DFFFF, 3, 0, PCIE_12_IRQ },
+	/* PCI Express Port 1-8 */
+	Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ },
+	Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ },
+	Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ },
+	Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ },
+	/* eMMC */
+	Package(){0x001AFFFF, 0, 0, eMMC_IRQ },
+	/* SerialIo */
+	Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ },
+	Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ },
+	Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ },
+	/* SATA controller */
+	Package(){0x0017FFFF, 0, 0, SATA_IRQ },
+	/* CSME (HECI, IDE-R, Keyboard and Text redirection */
+	Package(){0x0016FFFF, 0, 0, HECI_1_IRQ },
+	Package(){0x0016FFFF, 1, 0, HECI_2_IRQ },
+	Package(){0x0016FFFF, 2, 0, IDER_IRQ },
+	Package(){0x0016FFFF, 3, 0, KT_IRQ },
+	/* SerialIo */
+	Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ },
+	Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ },
+	Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ },
+	Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ },
+	/* D20: xHCI, OTG, SRAM, CNVi WiFi */
+	Package(){0x0014FFFF, 0, 0, XHCI_IRQ },
+	Package(){0x0014FFFF, 1, 0, OTG_IRQ },
+	Package(){0x0014FFFF, 2, 0, PMC_SRAM_IRQ },
+	Package(){0x0014FFFF, 3, 0, CNViWIFI_IRQ },
+	/* Integrated Sensor Hub */
+	Package(){0x0013FFFF, 0, 0, ISH_IRQ },
+	/* Thermal */
+	Package(){0x0012FFFF, 0, 0, THERMAL_IRQ },
+	/* Host Bridge */
+	/* Root Port D1F0 */
+	Package(){0x0001FFFF, 0, 0, PEG_RP_INTA_IRQ },
+	Package(){0x0001FFFF, 1, 0, PEG_RP_INTB_IRQ },
+	Package(){0x0001FFFF, 2, 0, PEG_RP_INTC_IRQ },
+	Package(){0x0001FFFF, 3, 0, PEG_RP_INTD_IRQ },
+	/* SA IGFX Device */
+	Package(){0x0002FFFF, 0, 0, IGFX_IRQ },
+	/* SA Thermal Device */
+	Package(){0x0004FFFF, 0, 0, SA_THERMAL_IRQ },
+	/* SA IPU Device */
+	Package(){0x0005FFFF, 0, 0, IPU_IRQ },
+	/* SA GNA Device */
+	Package(){0x0008FFFF, 0, 0, GNA_IRQ },
+})
+
+Name (PICN, Package () {
+	/* D31: cAVS, SMBus, GbE, Nothpeak */
+	Package () { 0x001FFFFF, 0, \_SB.PCI0.LNKA, 0 },
+	Package () { 0x001FFFFF, 1, \_SB.PCI0.LNKB, 0 },
+	Package () { 0x001FFFFF, 2, \_SB.PCI0.LNKC, 0 },
+	Package () { 0x001FFFFF, 3, \_SB.PCI0.LNKD, 0 },
+	/* D32: Can't use PIC*/
+	/* D29: PCI Express Port 9-16 */
+	Package () { 0x001DFFFF, 0, \_SB.PCI0.LNKA, 0 },
+	Package () { 0x001DFFFF, 1, \_SB.PCI0.LNKB, 0 },
+	Package () { 0x001DFFFF, 2, \_SB.PCI0.LNKC, 0 },
+	Package () { 0x001DFFFF, 3, \_SB.PCI0.LNKD, 0 },
+	/* D28: PCI Express Port 1-8 */
+	Package () { 0x001CFFFF, 0, \_SB.PCI0.LNKA, 0 },
+	Package () { 0x001CFFFF, 1, \_SB.PCI0.LNKB, 0 },
+	Package () { 0x001CFFFF, 2, \_SB.PCI0.LNKC, 0 },
+	Package () { 0x001CFFFF, 3, \_SB.PCI0.LNKD, 0 },
+	/* D25: Can't use PIC*/
+	/* D23 */
+	Package () { 0x0017FFFF, 0, \_SB.PCI0.LNKA, 0 },
+	/* D22: CSME (HECI, IDE-R, KT redirection */
+	Package () { 0x0016FFFF, 0, \_SB.PCI0.LNKA, 0 },
+	Package () { 0x0016FFFF, 1, \_SB.PCI0.LNKB, 0 },
+	Package () { 0x0016FFFF, 2, \_SB.PCI0.LNKC, 0 },
+	Package () { 0x0016FFFF, 3, \_SB.PCI0.LNKD, 0 },
+	/* D21: Can't use PIC*/
+	/* D20: xHCI, OTG, SRAM, CNVi WiFi */
+	Package () { 0x0014FFFF, 0, \_SB.PCI0.LNKA, 0 },
+	Package () { 0x0014FFFF, 1, \_SB.PCI0.LNKB, 0 },
+	Package () { 0x0014FFFF, 2, \_SB.PCI0.LNKC, 0 },
+	Package () { 0x0014FFFF, 3, \_SB.PCI0.LNKD, 0 },
+	/* D19: Can't use PIC*/
+	/* Thermal */
+	Package () { 0x0012FFFF, 0, \_SB.PCI0.LNKA, 0 },
+	/* P.E.G. Root Port D1F0 */
+	Package () { 0x0001FFFF, 0, \_SB.PCI0.LNKA, 0 },
+	Package () { 0x0001FFFF, 1, \_SB.PCI0.LNKB, 0 },
+	Package () { 0x0001FFFF, 2, \_SB.PCI0.LNKC, 0 },
+	Package () { 0x0001FFFF, 3, \_SB.PCI0.LNKD, 0 },
+	/* SA IGFX Device */
+	Package () { 0x0002FFFF, 0, \_SB.PCI0.LNKA, 0 },
+	/* SA Thermal Device */
+	Package () { 0x0004FFFF, 0, \_SB.PCI0.LNKA, 0 },
+	/* SA IPU Device */
+	Package () { 0x0005FFFF, 0, \_SB.PCI0.LNKA, 0 },
+	/* SA GNA Device */
+	Package () { 0x0008FFFF, 0, \_SB.PCI0.LNKA, 0 },
+})
+
+Method (_PRT)
 {
-	Return(Package() {
+	If (PICM) {
-
+		Return (^PICP)
-		// PCI Bridge
+	} Else {
-		// cAVS, SMBus, GbE, Nothpeak
+		Return (^PICN)
-		Package(){0x001FFFFF, 0, 0, 16 },
+	}
-		Package(){0x001FFFFF, 1, 0, 17 },
-		Package(){0x001FFFFF, 2, 0, 18 },
-		Package(){0x001FFFFF, 3, 0, 19 },
-		// SerialIo and SCS
-		Package(){0x001EFFFF, 0, 0, 20 },
-		Package(){0x001EFFFF, 1, 0, 21 },
-		Package(){0x001EFFFF, 2, 0, 22 },
-		Package(){0x001EFFFF, 3, 0, 23 },
-		// PCI Express Port 9-16
-		Package(){0x001DFFFF, 0, 0, 16 },
-		Package(){0x001DFFFF, 1, 0, 17 },
-		Package(){0x001DFFFF, 2, 0, 18 },
-		Package(){0x001DFFFF, 3, 0, 19 },
-		// PCI Express Port 1-8
-		Package(){0x001CFFFF, 0, 0, 16 },
-		Package(){0x001CFFFF, 1, 0, 17 },
-		Package(){0x001CFFFF, 2, 0, 18 },
-		Package(){0x001CFFFF, 3, 0, 19 },
-		// PCI Express Port 17-20
-		Package(){0x001BFFFF, 0, 0, 16 },
-		Package(){0x001BFFFF, 1, 0, 17 },
-		Package(){0x001BFFFF, 2, 0, 18 },
-		Package(){0x001BFFFF, 3, 0, 19 },
-		// eMMC
-		Package(){0x001AFFFF, 0, 0, 16 },
-		Package(){0x001AFFFF, 1, 0, 17 },
-		Package(){0x001AFFFF, 2, 0, 18 },
-		Package(){0x001AFFFF, 3, 0, 19 },
-		// SerialIo
-		Package(){0x0019FFFF, 0, 0, 32 },
-		Package(){0x0019FFFF, 1, 0, 33 },
-		Package(){0x0019FFFF, 2, 0, 34 },
-		// SATA controller
-		Package(){0x0017FFFF, 0, 0, 16 },
-		// CSME (HECI, IDE-R, Keyboard and Text redirection
-		Package(){0x0016FFFF, 0, 0, 16 },
-		Package(){0x0016FFFF, 1, 0, 17 },
-		Package(){0x0016FFFF, 2, 0, 18 },
-		Package(){0x0016FFFF, 3, 0, 19 },
-		// SerialIo
-		Package(){0x0015FFFF, 0, 0, 16 },
-		Package(){0x0015FFFF, 1, 0, 17 },
-		Package(){0x0015FFFF, 2, 0, 18 },
-		Package(){0x0015FFFF, 3, 0, 19 },
-		// CNL: D20: xHCI, OTG, CNVi WiFi, SDcard
-		Package(){0x0014FFFF, 0, 0, 16 },
-		Package(){0x0014FFFF, 1, 0, 17 },
-		Package(){0x0014FFFF, 2, 0, 18 },
-		Package(){0x0014FFFF, 3, 0, 19 },
-		// Integrated Sensor Hub
-		Package(){0x0013FFFF, 0, 0, 20 },
-		// Thermal, UFS, SerialIo SPI 2
-		Package(){0x0012FFFF, 0, 0, 16 },
-		Package(){0x0012FFFF, 1, 0, 24 },
-		Package(){0x0012FFFF, 2, 0, 18 },
-		Package(){0x0012FFFF, 3, 0, 19 },
-
-		// Host Bridge
-		// Root Port D1F0
-		Package(){0x0001FFFF, 0, 0, 16 },
-		Package(){0x0001FFFF, 1, 0, 17 },
-		Package(){0x0001FFFF, 2, 0, 18 },
-		Package(){0x0001FFFF, 3, 0, 19 },
-		// Root Port D1F1
-		// Root Port D1F2
-		// IGFX Device
-		Package(){0x0002FFFF, 0, 0, 16 },
-		// Thermal Device
-		Package(){0x0004FFFF, 0, 0, 16 },
-		// IPU Device
-		Package(){0x0005FFFF, 0, 0, 16 },
-		// GNA Device
-		Package(){0x0008FFFF, 0, 0, 16 },
-	})
 }

src/soc/intel/cannonlake/acpi/southbridge.asl

@@ -15,6 +15,13 @@
  * GNU General Public License for more details.
  */
 
+#include <intelblocks/itss.h>
+#include <intelblocks/pcr.h>
+#include <soc/itss.h>
+#include <soc/pcr_ids.h>
+
+/* Interrupt Routing */
+#include "irqlinks.asl"
 
 /* PCI IRQ assignment */
 #include "pci_irqs.asl"

src/soc/intel/cannonlake/include/soc/irq.h

@@ -87,8 +87,9 @@
 
 #define XHCI_IRQ 16
 #define OTG_IRQ 17
-#define THRMAL_IRQ 16
+#define PMC_SRAM_IRQ 18
-#define CNViWIFI_IRQ 16
+#define THERMAL_IRQ 16
+#define CNViWIFI_IRQ 19
 #define UFS_IRQ 16
 #define CIO_INTA_IRQ 16
 #define CIO_INTD_IRQ 19
@@ -101,6 +102,6 @@
 
 #define IGFX_IRQ 16
 #define SA_THERMAL_IRQ 16
-#define SKYCAM_IRQ 16
+#define IPU_IRQ 16
-#define GMM_IRQ 16
+#define GNA_IRQ 16
 #endif /* _SOC_IRQ_H_ */