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vc/amd/agesa: Remove fam12

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With removal of Torpedo mainboard, this code is no longer
necessary. Will resolve some unique Coverity issues.

Change-Id: I2927245c426566a8f80863a109d015ebf6176803
Signed-off-by: Joe Moore <awokd@danwin1210.me>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
This commit is contained in:
Joe Moore
2019-10-21 00:32:00 -06:00
committed by Patrick Georgi
parent 2c08ea7cfc
commit a0e1e596f8
560 changed files with 0 additions and 183916 deletions
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1
src/vendorcode/amd/agesa/Makefile.inc
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@ -1,4 +1,3 @@
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += f12
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += f14
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += f15tn
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += f16kb

3295
src/vendorcode/amd/agesa/f12/AGESA.h
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File diff suppressed because it is too large Load Diff

486
src/vendorcode/amd/agesa/f12/AMD.h
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@ -1,486 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Agesa structures and definitions
*
* Contains AMD AGESA core interface
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Include
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _AMD_H_
#define _AMD_H_
#define AGESA_REVISION "Arch2008"
#define AGESA_ID "AGESA"
#define Int16FromChar(a,b) ((a) << 0 | (b) << 8)
#define Int32FromChar(a,b,c,d) ((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24)
//
//
// AGESA Types and Definitions
//
//
#define LAST_ENTRY 0xFFFFFFFF
#define IMAGE_SIGNATURE Int32FromChar ('$', 'A', 'M', 'D')
#define IOCF8 0xCF8
#define IOCFC 0xCFC
/// The return status for all AGESA public services.
///
/// Services return the most severe status of any logged event. Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK
/// will have log entries with more detail.
///
typedef enum {
AGESA_SUCCESS = 0, ///< The service completed normally. Info may be logged.
AGESA_UNSUPPORTED, ///< The dispatcher or create struct had an unimplemented function requested.
///< Not logged.
AGESA_BOUNDS_CHK, ///< A dynamic parameter was out of range and the service was not provided.
///< Example, memory address not installed, heap buffer handle not found.
///< Not Logged.
// AGESA_STATUS of greater severity (the ones below this line), always have a log entry available.
AGESA_ALERT, ///< An observed condition, but no loss of function.
///< See log. Example, HT CRC.
AGESA_WARNING, ///< Possible or minor loss of function. See Log.
AGESA_ERROR, ///< Significant loss of function, boot may be possible. See Log.
AGESA_CRITICAL, ///< Continue boot only to notify user. See Log.
AGESA_FATAL, ///< Halt booting. See Log, however Fatal errors pertaining to heap problems
///< may not be able to reliably produce log events.
AgesaStatusMax ///< Not a status, for limit checking.
} AGESA_STATUS;
/// For checking whether a status is at or above the mandatory log level.
#define AGESA_STATUS_LOG_LEVEL AGESA_ALERT
/**
* Callout method to the host environment.
*
* Callout using a dispatch with appropriate thunk layer, which is determined by the host environment.
*
* @param[in] Function The specific callout function being invoked.
* @param[in] FcnData Function specific data item.
* @param[in,out] ConfigPtr Reference to Callout params.
*/
typedef AGESA_STATUS (*CALLOUT_ENTRY) (
IN UINT32 Function,
IN UINTN FcnData,
IN OUT VOID *ConfigPtr
);
typedef AGESA_STATUS (*IMAGE_ENTRY) (VOID *ConfigPtr);
typedef AGESA_STATUS (*MODULE_ENTRY) (VOID *ConfigPtr);
///This allocation type is used by the AmdCreateStruct entry point
typedef enum {
PreMemHeap = 0, ///< Create heap in cache.
PostMemDram, ///< Create heap in memory.
ByHost ///< Create heap by Host.
} ALLOCATION_METHOD;
/// These width descriptors are used by the library function, and others, to specify the data size
typedef enum ACCESS_WIDTH {
AccessWidth8 = 1, ///< Access width is 8 bits.
AccessWidth16, ///< Access width is 16 bits.
AccessWidth32, ///< Access width is 32 bits.
AccessWidth64, ///< Access width is 64 bits.
AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data.
AccessS3SaveWidth16, ///< Save 16 bits data.
AccessS3SaveWidth32, ///< Save 32 bits data.
AccessS3SaveWidth64, ///< Save 64 bits data.
} ACCESS_WIDTH;
/// AGESA struct name
typedef enum {
// AGESA BASIC FUNCTIONS
AMD_INIT_RECOVERY = 0x00020000, ///< AmdInitRecovery entry point handle
AMD_CREATE_STRUCT, ///< AmdCreateStruct handle
AMD_INIT_EARLY, ///< AmdInitEarly entry point handle
AMD_INIT_ENV, ///< AmdInitEnv entry point handle
AMD_INIT_LATE, ///< AmdInitLate entry point handle
AMD_INIT_MID, ///< AmdInitMid entry point handle
AMD_INIT_POST, ///< AmdInitPost entry point handle
AMD_INIT_RESET, ///< AmdInitReset entry point handle
AMD_INIT_RESUME, ///< AmdInitResume entry point handle
AMD_RELEASE_STRUCT, ///< AmdReleaseStruct handle
AMD_S3LATE_RESTORE, ///< AmdS3LateRestore entry point handle
AMD_S3_SAVE, ///< AmdS3Save entry point handle
AMD_GET_APIC_ID, ///< AmdGetApicId entry point handle
AMD_GET_PCI_ADDRESS, ///< AmdGetPciAddress entry point handle
AMD_IDENTIFY_CORE, ///< AmdIdentifyCore general service handle
AMD_READ_EVENT_LOG, ///< AmdReadEventLog general service handle
AMD_GET_EXECACHE_SIZE, ///< AmdGetAvailableExeCacheSize general service handle
AMD_LATE_RUN_AP_TASK, ///< AmdLateRunApTask entry point handle
AMD_IDENTIFY_DIMMS, ///< AmdIdentifyDimm general service handle
AMD_GET_2D_DATA_EYE, ///< AmdGet2DDataEye general service handle
AMD_S3FINAL_RESTORE, ///< AmdS3FinalRestore entry point handle
AMD_INIT_RTB ///< AmdInitRtb entry point handle
} AGESA_STRUCT_NAME;
/* ResetType constant values */
#define WARM_RESET_WHENEVER 1
#define COLD_RESET_WHENEVER 2
#define WARM_RESET_IMMEDIATELY 3
#define COLD_RESET_IMMEDIATELY 4
// AGESA Structures
/// The standard header for all AGESA services.
/// For internal AGESA naming conventions, see @ref amdconfigparamname .
typedef struct {
IN UINT32 ImageBasePtr; ///< The AGESA Image base address.
IN UINT32 Func; ///< The service desired
IN UINT32 AltImageBasePtr; ///< Alternate Image location
IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA
IN UINT8 HeapStatus; ///< For heap status from boot time slide.
IN UINT64 HeapBasePtr; ///< Location of the heap
IN OUT UINT8 Reserved[7]; ///< This space is reserved for future use.
} AMD_CONFIG_PARAMS;
/// Create Struct Interface.
typedef struct {
IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
IN AGESA_STRUCT_NAME AgesaFunctionName; ///< The service to init
IN ALLOCATION_METHOD AllocationMethod; ///< How to handle buffer allocation
IN OUT UINT32 NewStructSize; ///< The size of the allocated data, in for ByHost, else out only.
IN OUT VOID *NewStructPtr; ///< The struct for the service.
///< The struct to init for ByHost allocation,
///< the initialized struct on return.
} AMD_INTERFACE_PARAMS;
#define FUNC_0 0 // bit-placed for PCI address creation
#define FUNC_1 1
#define FUNC_2 2
#define FUNC_3 3
#define FUNC_4 4
#define FUNC_5 5
#define FUNC_6 6
#define FUNC_7 7
/// AGESA Binary module header structure
typedef struct {
IN UINT32 Signature; ///< Binary Signature
IN CHAR8 CreatorID[8]; ///< 8 characters ID
IN CHAR8 Version[12]; ///< 12 characters version
IN UINT32 ModuleInfoOffset; ///< Offset of module
IN UINT32 EntryPointAddress; ///< Entry address
IN UINT32 ImageBase; ///< Image base
IN UINT32 RelocTableOffset; ///< Relocate Table offset
IN UINT32 ImageSize; ///< Size
IN UINT16 Checksum; ///< Checksum
IN UINT8 ImageType; ///< Type
IN UINT8 V_Reserved; ///< Reserved
} AMD_IMAGE_HEADER;
/// AGESA Binary module header structure
typedef struct _AMD_MODULE_HEADER {
IN UINT32 ModuleHeaderSignature; ///< Module signature
IN CHAR8 ModuleIdentifier[8]; ///< 8 characters ID
IN CHAR8 ModuleVersion[12]; ///< 12 characters version
IN VOID *ModuleDispatcher; ///< A pointer point to dispatcher
IN struct _AMD_MODULE_HEADER *NextBlock; ///< Next module header link
} AMD_MODULE_HEADER;
// AMD_CODE_HEADER Signatures.
#define AGESA_CODE_SIGNATURE {'!', '!', 'A', 'G', 'E', 'S', 'A', ' '}
#define CIMXNB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'N', 'B'}
#define CIMXSB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'S', 'B'}
/// AGESA_CODE_SIGNATURE
typedef struct {
IN CHAR8 Signature[8]; ///< code header Signature
IN CHAR8 ComponentName[8]; ///< 8 character name of the code module
IN CHAR8 Version[12]; ///< 12 character version string
IN CHAR8 TerminatorNull; ///< null terminated string
IN CHAR8 VerReserved[7]; ///< reserved space
} AMD_CODE_HEADER;
/// Extended PCI address format
typedef struct {
IN OUT UINT32 Register:12; ///< Register offset
IN OUT UINT32 Function:3; ///< Function number
IN OUT UINT32 Device:5; ///< Device number
IN OUT UINT32 Bus:8; ///< Bus number
IN OUT UINT32 Segment:4; ///< Segment
} EXT_PCI_ADDR;
/// Union type for PCI address
typedef union _PCI_ADDR {
IN UINT32 AddressValue; ///< Formal address
IN EXT_PCI_ADDR Address; ///< Extended address
} PCI_ADDR;
// SBDFO - Segment Bus Device Function Offset
// 31:28 Segment (4-bits)
// 27:20 Bus (8-bits)
// 19:15 Device (5-bits)
// 14:12 Function(3-bits)
// 11:00 Offset (12-bits)
#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((UINT32) (Seg)) << 28) | (((UINT32) (Bus)) << 20) | \
(((UINT32)(Dev)) << 15) | (((UINT32)(Fun)) << 12) | ((UINT32)(Off)))
#define ILLEGAL_SBDFO 0xFFFFFFFF
/// CPUID data received registers format
typedef struct {
OUT UINT32 EAX_Reg; ///< CPUID instruction result in EAX
OUT UINT32 EBX_Reg; ///< CPUID instruction result in EBX
OUT UINT32 ECX_Reg; ///< CPUID instruction result in ECX
OUT UINT32 EDX_Reg; ///< CPUID instruction result in EDX
} CPUID_DATA;
/// HT frequency for external callbacks
typedef enum {
HT_FREQUENCY_200M = 0, ///< HT speed 200 for external callbacks
HT_FREQUENCY_400M = 2, ///< HT speed 400 for external callbacks
HT_FREQUENCY_600M = 4, ///< HT speed 600 for external callbacks
HT_FREQUENCY_800M = 5, ///< HT speed 800 for external callbacks
HT_FREQUENCY_1000M = 6, ///< HT speed 1000 for external callbacks
HT_FREQUENCY_1200M = 7, ///< HT speed 1200 for external callbacks
HT_FREQUENCY_1400M = 8, ///< HT speed 1400 for external callbacks
HT_FREQUENCY_1600M = 9, ///< HT speed 1600 for external callbacks
HT_FREQUENCY_1800M = 10, ///< HT speed 1800 for external callbacks
HT_FREQUENCY_2000M = 11, ///< HT speed 2000 for external callbacks
HT_FREQUENCY_2200M = 12, ///< HT speed 2200 for external callbacks
HT_FREQUENCY_2400M = 13, ///< HT speed 2400 for external callbacks
HT_FREQUENCY_2600M = 14, ///< HT speed 2600 for external callbacks
HT_FREQUENCY_2800M = 17, ///< HT speed 2800 for external callbacks
HT_FREQUENCY_3000M = 18, ///< HT speed 3000 for external callbacks
HT_FREQUENCY_3200M = 19, ///< HT speed 3200 for external callbacks
HT_FREQUENCY_MAX ///< Limit check.
} HT_FREQUENCIES;
// The minimum HT3 frequency
#define HT3_FREQUENCY_MIN HT_FREQUENCY_1200M
#ifndef BIT0
#define BIT0 0x0000000000000001ull
#endif
#ifndef BIT1
#define BIT1 0x0000000000000002ull
#endif
#ifndef BIT2
#define BIT2 0x0000000000000004ull
#endif
#ifndef BIT3
#define BIT3 0x0000000000000008ull
#endif
#ifndef BIT4
#define BIT4 0x0000000000000010ull
#endif
#ifndef BIT5
#define BIT5 0x0000000000000020ull
#endif
#ifndef BIT6
#define BIT6 0x0000000000000040ull
#endif
#ifndef BIT7
#define BIT7 0x0000000000000080ull
#endif
#ifndef BIT8
#define BIT8 0x0000000000000100ull
#endif
#ifndef BIT9
#define BIT9 0x0000000000000200ull
#endif
#ifndef BIT10
#define BIT10 0x0000000000000400ull
#endif
#ifndef BIT11
#define BIT11 0x0000000000000800ull
#endif
#ifndef BIT12
#define BIT12 0x0000000000001000ull
#endif
#ifndef BIT13
#define BIT13 0x0000000000002000ull
#endif
#ifndef BIT14
#define BIT14 0x0000000000004000ull
#endif
#ifndef BIT15
#define BIT15 0x0000000000008000ull
#endif
#ifndef BIT16
#define BIT16 0x0000000000010000ull
#endif
#ifndef BIT17
#define BIT17 0x0000000000020000ull
#endif
#ifndef BIT18
#define BIT18 0x0000000000040000ull
#endif
#ifndef BIT19
#define BIT19 0x0000000000080000ull
#endif
#ifndef BIT20
#define BIT20 0x0000000000100000ull
#endif
#ifndef BIT21
#define BIT21 0x0000000000200000ull
#endif
#ifndef BIT22
#define BIT22 0x0000000000400000ull
#endif
#ifndef BIT23
#define BIT23 0x0000000000800000ull
#endif
#ifndef BIT24
#define BIT24 0x0000000001000000ull
#endif
#ifndef BIT25
#define BIT25 0x0000000002000000ull
#endif
#ifndef BIT26
#define BIT26 0x0000000004000000ull
#endif
#ifndef BIT27
#define BIT27 0x0000000008000000ull
#endif
#ifndef BIT28
#define BIT28 0x0000000010000000ull
#endif
#ifndef BIT29
#define BIT29 0x0000000020000000ull
#endif
#ifndef BIT30
#define BIT30 0x0000000040000000ull
#endif
#ifndef BIT31
#define BIT31 0x0000000080000000ull
#endif
#ifndef BIT32
#define BIT32 0x0000000100000000ull
#endif
#ifndef BIT33
#define BIT33 0x0000000200000000ull
#endif
#ifndef BIT34
#define BIT34 0x0000000400000000ull
#endif
#ifndef BIT35
#define BIT35 0x0000000800000000ull
#endif
#ifndef BIT36
#define BIT36 0x0000001000000000ull
#endif
#ifndef BIT37
#define BIT37 0x0000002000000000ull
#endif
#ifndef BIT38
#define BIT38 0x0000004000000000ull
#endif
#ifndef BIT39
#define BIT39 0x0000008000000000ull
#endif
#ifndef BIT40
#define BIT40 0x0000010000000000ull
#endif
#ifndef BIT41
#define BIT41 0x0000020000000000ull
#endif
#ifndef BIT42
#define BIT42 0x0000040000000000ull
#endif
#ifndef BIT43
#define BIT43 0x0000080000000000ull
#endif
#ifndef BIT44
#define BIT44 0x0000100000000000ull
#endif
#ifndef BIT45
#define BIT45 0x0000200000000000ull
#endif
#ifndef BIT46
#define BIT46 0x0000400000000000ull
#endif
#ifndef BIT47
#define BIT47 0x0000800000000000ull
#endif
#ifndef BIT48
#define BIT48 0x0001000000000000ull
#endif
#ifndef BIT49
#define BIT49 0x0002000000000000ull
#endif
#ifndef BIT50
#define BIT50 0x0004000000000000ull
#endif
#ifndef BIT51
#define BIT51 0x0008000000000000ull
#endif
#ifndef BIT52
#define BIT52 0x0010000000000000ull
#endif
#ifndef BIT53
#define BIT53 0x0020000000000000ull
#endif
#ifndef BIT54
#define BIT54 0x0040000000000000ull
#endif
#ifndef BIT55
#define BIT55 0x0080000000000000ull
#endif
#ifndef BIT56
#define BIT56 0x0100000000000000ull
#endif
#ifndef BIT57
#define BIT57 0x0200000000000000ull
#endif
#ifndef BIT58
#define BIT58 0x0400000000000000ull
#endif
#ifndef BIT59
#define BIT59 0x0800000000000000ull
#endif
#ifndef BIT60
#define BIT60 0x1000000000000000ull
#endif
#ifndef BIT61
#define BIT61 0x2000000000000000ull
#endif
#ifndef BIT62
#define BIT62 0x4000000000000000ull
#endif
#ifndef BIT63
#define BIT63 0x8000000000000000ull
#endif
#endif // _AMD_H_

140
src/vendorcode/amd/agesa/f12/Config/OptionC6Install.h
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@ -1,140 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: C6 C-state
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_C6_STATE_INSTALL_H_
#define _OPTION_C6_STATE_INSTALL_H_
#include "cpuC6State.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_C6_STATE_FEAT
#define F12_C6_STATE_SUPPORT
#define F14_ON_C6_STATE_SUPPORT
#define F15_OR_C6_STATE_SUPPORT
#if OPTION_C6_STATE == TRUE
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
#ifdef OPTION_FAMILY12H
#if OPTION_FAMILY12H == TRUE
#if OPTION_FAMILY12H_LN == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State;
#undef OPTION_C6_STATE_FEAT
#define OPTION_C6_STATE_FEAT &CpuFeatureC6State,
extern CONST C6_FAMILY_SERVICES ROMDATA F12C6Support;
#undef F12_C6_STATE_SUPPORT
#define F12_C6_STATE_SUPPORT {AMD_FAMILY_12_LN, &F12C6Support},
#if OPTION_EARLY_SAMPLES == TRUE
extern F_F12_ES_C6_INIT F12C6A0Workaround;
CONST F12_ES_C6_SUPPORT ROMDATA F12EarlySampleC6Support =
{
F12C6A0Workaround
};
#else
CONST F12_ES_C6_SUPPORT ROMDATA F12EarlySampleC6Support =
{
(PF_F12_ES_C6_INIT) CommonVoid
};
#endif
#endif
#endif
#endif
#ifdef OPTION_FAMILY14H
#if OPTION_FAMILY14H == TRUE
#if (OPTION_FAMILY14H_ON == TRUE)
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State;
#undef OPTION_C6_STATE_FEAT
#define OPTION_C6_STATE_FEAT &CpuFeatureC6State,
extern CONST C6_FAMILY_SERVICES ROMDATA F14OnC6Support;
#undef F14_ON_C6_STATE_SUPPORT
#define F14_ON_C6_STATE_SUPPORT {AMD_FAMILY_14_ON, &F14OnC6Support},
CONST F14_ON_ES_C6_SUPPORT ROMDATA F14OnEarlySampleC6Support =
{
(PF_F14_ON_ES_IS_C6_SUPPORTED) CommonVoid,
(PF_F14_ON_ES_C6_INIT) CommonVoid
};
#endif
#endif
#endif
#ifdef OPTION_FAMILY15H
#if OPTION_FAMILY15H == TRUE
#if (OPTION_FAMILY15H_OR == TRUE)
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State;
#undef OPTION_C6_STATE_FEAT
#define OPTION_C6_STATE_FEAT &CpuFeatureC6State,
extern CONST C6_FAMILY_SERVICES ROMDATA F15OrC6Support;
#undef F15_OR_C6_STATE_SUPPORT
#define F15_OR_C6_STATE_SUPPORT {AMD_FAMILY_15_OR, &F15OrC6Support},
CONST F15_OR_ES_C6_SUPPORT ROMDATA F15OrEarlySampleC6Support =
{
(PF_F15_OR_ES_IS_C6_SUPPORTED) CommonVoid
};
#endif
#endif
#endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA C6FamilyServiceArray[] =
{
F12_C6_STATE_SUPPORT
F14_ON_C6_STATE_SUPPORT
F15_OR_C6_STATE_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA C6FamilyServiceTable =
{
(sizeof (C6FamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&C6FamilyServiceArray[0]
};
#endif // _OPTION_C6_STATE_INSTALL_H_

144
src/vendorcode/amd/agesa/f12/Config/OptionCpbInstall.h
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@ -1,144 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: Core Performance Boost
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 46389 $ @e \$Date: 2011-02-01 11:22:49 +0800 (Tue, 01 Feb 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_CPB_INSTALL_H_
#define _OPTION_CPB_INSTALL_H_
#include "cpuCpb.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_CPB_FEAT
#define F10_CPB_SUPPORT
#define F12_CPB_SUPPORT
#define F14_ON_CPB_SUPPORT
#define F15_OR_CPB_SUPPORT
#if OPTION_CPB == TRUE
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)
// Family 10h
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
#if OPTION_FAMILY10H_PH == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
#undef OPTION_CPB_FEAT
#define OPTION_CPB_FEAT &CpuFeatureCpb,
extern CONST CPB_FAMILY_SERVICES ROMDATA F10CpbSupport;
#undef F10_CPB_SUPPORT
#define F10_CPB_SUPPORT {AMD_FAMILY_10_PH, &F10CpbSupport},
#endif
#endif
#endif
// Family 12h
#ifdef OPTION_FAMILY12H
#if OPTION_FAMILY12H == TRUE
#if OPTION_FAMILY12H_LN == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
#undef OPTION_CPB_FEAT
#define OPTION_CPB_FEAT &CpuFeatureCpb,
extern CONST CPB_FAMILY_SERVICES ROMDATA F12CpbSupport;
#undef F12_CPB_SUPPORT
#define F12_CPB_SUPPORT {AMD_FAMILY_12_LN, &F12CpbSupport},
// CONST F12_ES_CPB_SUPPORT ROMDATA F12EarlySampleCpbSupport =
// {
// (PF_F12_ES_CPB_INIT) CommonVoid
// };
#endif
#endif
#endif
// Family 14h
#ifdef OPTION_FAMILY14H
#if OPTION_FAMILY14H == TRUE
#if OPTION_FAMILY14H_ON == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
#undef OPTION_CPB_FEAT
#define OPTION_CPB_FEAT &CpuFeatureCpb,
extern CONST CPB_FAMILY_SERVICES ROMDATA F14OnCpbSupport;
#undef F14_ON_CPB_SUPPORT
#define F14_ON_CPB_SUPPORT {AMD_FAMILY_14_ON, &F14OnCpbSupport},
#endif
#endif
#endif
// Family 15h
#ifdef OPTION_FAMILY15H
#if OPTION_FAMILY15H == TRUE
#if (OPTION_FAMILY15H_OR == TRUE)
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
#undef OPTION_CPB_FEAT
#define OPTION_CPB_FEAT &CpuFeatureCpb,
extern CONST CPB_FAMILY_SERVICES ROMDATA F15OrCpbSupport;
#undef F15_OR_CPB_SUPPORT
#define F15_OR_CPB_SUPPORT {AMD_FAMILY_15_OR, &F15OrCpbSupport},
CONST F15_OR_ES_CPB_SUPPORT ROMDATA F15OrEarlySampleCpbSupport =
{
(PF_F15_OR_ES_IS_CPB_SUPPORTED) CommonVoid
};
#endif
#endif
#endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CpbFamilyServiceArray[] =
{
F10_CPB_SUPPORT
F12_CPB_SUPPORT
F14_ON_CPB_SUPPORT
F15_OR_CPB_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CpbFamilyServiceTable =
{
(sizeof (CpbFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&CpbFamilyServiceArray[0]
};
#endif // _OPTION_CPB_INSTALL_H_

117
src/vendorcode/amd/agesa/f12/Config/OptionCpuCacheFlushOnHaltInstall.h
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@ -1,117 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: CPU Cache Flush On Halt
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 44737 $ @e \$Date: 2011-01-05 15:59:55 +0800 (Wed, 05 Jan 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_
#define _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_
#include "cpuPostInit.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
#define F10_BL_CPU_CFOH_SUPPORT
#define F10_DA_CPU_CFOH_SUPPORT
#define F10_CPU_CFOH_SUPPORT
#define F15_OR_CPU_CFOH_SUPPORT
#if OPTION_CPU_CFOH == TRUE
#if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE)
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCacheFlushOnHalt;
#undef OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
#define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT &CpuFeatureCacheFlushOnHalt,
#if OPTION_FAMILY10H_BL == TRUE
extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10BlCacheFlushOnHalt;
#undef F10_BL_CPU_CFOH_SUPPORT
#define F10_BL_CPU_CFOH_SUPPORT {AMD_FAMILY_10_BL, &F10BlCacheFlushOnHalt},
#endif
#if OPTION_FAMILY10H_DA == TRUE
extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10DaCacheFlushOnHalt;
#undef F10_DA_CPU_CFOH_SUPPORT
#define F10_DA_CPU_CFOH_SUPPORT {AMD_FAMILY_10_DA, &F10DaCacheFlushOnHalt},
#endif
#if (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_HY == TRUE) || (OPTION_FAMILY10H_PH == TRUE)
extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10CacheFlushOnHalt;
#undef F10_CPU_CFOH_SUPPORT
#define F10_CPU_CFOH_SUPPORT {AMD_FAMILY_10_RB | AMD_FAMILY_10_HY | AMD_FAMILY_10_PH, &F10CacheFlushOnHalt},
#endif
#endif
#endif
#ifdef OPTION_FAMILY15H
#if OPTION_FAMILY15H == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCacheFlushOnHalt;
#undef OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
#define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT &CpuFeatureCacheFlushOnHalt,
#if OPTION_FAMILY15H_OR == TRUE
extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F15OrCacheFlushOnHalt;
#undef F15_OR_CPU_CFOH_SUPPORT
#define F15_OR_CPU_CFOH_SUPPORT {AMD_FAMILY_15_OR, &F15OrCacheFlushOnHalt},
#endif
#endif
#endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CacheFlushOnHaltFamilyServiceArray[] =
{
F10_BL_CPU_CFOH_SUPPORT
F10_DA_CPU_CFOH_SUPPORT
F10_CPU_CFOH_SUPPORT
F15_OR_CPU_CFOH_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CacheFlushOnHaltFamilyServiceTable =
{
(sizeof (CacheFlushOnHaltFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&CacheFlushOnHaltFamilyServiceArray[0]
};
#endif // _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_

109
src/vendorcode/amd/agesa/f12/Config/OptionCpuCoreLevelingInstall.h
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@ -1,109 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: CPU Core Leveling
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_CPU_CORELEVELING_INSTALL_H_
#define _OPTION_CPU_CORELEVELING_INSTALL_H_
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_CPU_CORE_LEVELING_FEAT
#define F10_REVE_CPU_CORELEVELING_SUPPORT
#define F10_REVD_CPU_CORELEVELING_SUPPORT
#define F10_REVC_CPU_CORELEVELING_SUPPORT
#define F15_OR_CPU_CORELEVELING_SUPPORT
#if OPTION_CPU_CORELEVLING == TRUE
#if (AGESA_ENTRY_INIT_EARLY == TRUE)
// Family 10h
#if OPTION_FAMILY10H == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCoreLeveling;
#undef OPTION_CPU_CORE_LEVELING_FEAT
#define OPTION_CPU_CORE_LEVELING_FEAT &CpuFeatureCoreLeveling,
#if OPTION_FAMILY10H_HY == TRUE
extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevDCoreLeveling;
#undef F10_REVD_CPU_CORELEVELING_SUPPORT
#define F10_REVD_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_HY, &F10RevDCoreLeveling},
#endif
#if (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_BL == TRUE) || (OPTION_FAMILY10H_DA == TRUE)
extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevCCoreLeveling;
#undef F10_REVC_CPU_CORELEVELING_SUPPORT
#define F10_REVC_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_RB | AMD_FAMILY_10_BL | AMD_FAMILY_10_DA, &F10RevCCoreLeveling},
#endif
#if (OPTION_FAMILY10H_PH == TRUE)
extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevECoreLeveling;
#undef F10_REVE_CPU_CORELEVELING_SUPPORT
#define F10_REVE_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_PH, &F10RevECoreLeveling},
#endif
#endif
// Family 15h
#if OPTION_FAMILY15H == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCoreLeveling;
#undef OPTION_CPU_CORE_LEVELING_FEAT
#define OPTION_CPU_CORE_LEVELING_FEAT &CpuFeatureCoreLeveling,
extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F15OrCoreLeveling;
#undef F15_OR_CPU_CORELEVELING_SUPPORT
#define F15_OR_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_15_OR, &F15OrCoreLeveling},
#endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CoreLevelingFamilyServiceArray[] =
{
F10_REVE_CPU_CORELEVELING_SUPPORT
F10_REVD_CPU_CORELEVELING_SUPPORT
F10_REVC_CPU_CORELEVELING_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CoreLevelingFamilyServiceTable =
{
(sizeof (CoreLevelingFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&CoreLevelingFamilyServiceArray[0]
};
#endif // _OPTION_CPU_CORELEVELING_INSTALL_H_

357
src/vendorcode/amd/agesa/f12/Config/OptionCpuFamiliesInstall.h
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@ -1,357 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of all appropriate CPU family specific support.
*
* This file generates the defaults tables for all family specific
* combinations.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 49967 $ @e \$Date: 2011-03-31 11:15:12 +0800 (Thu, 31 Mar 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
/* Default all CPU Specific Service members to off. They
will be enabled as needed by cross referencing families
with entry points in the family / model install files. */
#define GET_PSTATE_POWER FALSE
#define GET_PSTATE_FREQ FALSE
#define DISABLE_PSTATE FALSE
#define TRANSITION_PSTATE FALSE
#define PROC_IDD_MAX FALSE
#define GET_TSC_RATE FALSE
#define PSTATE_TRANSITION_LATENCY FALSE
#define GET_PSTATE_REGISTER_INFO FALSE
#define GET_PSTATE_MAX_STATE FALSE
#define SET_PSTATE_LEVELING_REG FALSE
#define GET_NB_FREQ FALSE
#define GET_NB_IDD_MAX FALSE
#define IS_NBCOF_INIT_NEEDED FALSE
#define AP_INITIAL_LAUNCH FALSE
#define GET_AP_MAILBOX_FROM_HW FALSE
#define SET_AP_CORE_NUMBER FALSE
#define GET_AP_CORE_NUMBER FALSE
#define TRANSFER_AP_CORE_NUMBER FALSE
#define ID_POSITION_INITIAL_APICID FALSE
#define SAVE_FEATURES FALSE
#define WRITE_FEATURES FALSE
#define SET_DOWN_CORE_REG FALSE
#define SET_WARM_RESET_FLAG FALSE
#define GET_WARM_RESET_FLAG FALSE
#define USES_REGISTER_TABLES FALSE
#define BASE_FAMILY_PCI FALSE
#define MODEL_SPECIFIC_PCI FALSE
#define BASE_FAMILY_MSR FALSE
#define MODEL_SPECIFIC_MSR FALSE
#define BRAND_STRING1 FALSE
#define BRAND_STRING2 FALSE
#define BASE_FAMILY_HT_PCI FALSE
#define MODEL_SPECIFIC_HT_PCI FALSE
#define BASE_FAMILY_WORKAROUNDS FALSE
#define GET_PATCHES FALSE
#define GET_PATCHES_EQUIVALENCE_TABLE FALSE
#define GET_CACHE_INFO FALSE
#define GET_SYSTEM_PM_TABLE FALSE
#define GET_WHEA_INIT FALSE
#define GET_CFOH_REG FALSE
#define GET_PLATFORM_TYPE_SPECIFIC_INFO FALSE
#define IS_NB_PSTATE_ENABLED FALSE
/*
* Pull in family specific services based on entry point
*/
#if AGESA_ENTRY_INIT_RESET == TRUE
#undef ID_POSITION_INITIAL_APICID
#define ID_POSITION_INITIAL_APICID TRUE
#undef GET_AP_MAILBOX_FROM_HW
#define GET_AP_MAILBOX_FROM_HW TRUE
#undef SET_WARM_RESET_FLAG
#define SET_WARM_RESET_FLAG TRUE
#undef GET_WARM_RESET_FLAG
#define GET_WARM_RESET_FLAG TRUE
#undef GET_CACHE_INFO
#define GET_CACHE_INFO TRUE
#undef GET_AP_CORE_NUMBER
#define GET_AP_CORE_NUMBER TRUE
#undef TRANSFER_AP_CORE_NUMBER
#define TRANSFER_AP_CORE_NUMBER TRUE
#endif
#if AGESA_ENTRY_INIT_EARLY == TRUE
#undef TRANSITION_PSTATE
#define TRANSITION_PSTATE TRUE
#undef DISABLE_PSTATE
#define DISABLE_PSTATE TRUE
#undef PROC_IDD_MAX
#define PROC_IDD_MAX TRUE
#undef GET_TSC_RATE
#define GET_TSC_RATE TRUE
#undef GET_NB_FREQ
#define GET_NB_FREQ TRUE
#undef GET_NB_IDD_MAX
#define GET_NB_IDD_MAX TRUE
#undef IS_NBCOF_INIT_NEEDED
#define IS_NBCOF_INIT_NEEDED TRUE
#undef AP_INITIAL_LAUNCH
#define AP_INITIAL_LAUNCH TRUE
#undef GET_AP_MAILBOX_FROM_HW
#define GET_AP_MAILBOX_FROM_HW TRUE
#undef SET_AP_CORE_NUMBER
#define SET_AP_CORE_NUMBER TRUE
#undef GET_AP_CORE_NUMBER
#define GET_AP_CORE_NUMBER TRUE
#undef TRANSFER_AP_CORE_NUMBER
#define TRANSFER_AP_CORE_NUMBER TRUE
#undef ID_POSITION_INITIAL_APICID
#define ID_POSITION_INITIAL_APICID TRUE
#undef SET_DOWN_CORE_REG
#define SET_DOWN_CORE_REG TRUE
#undef SET_WARM_RESET_FLAG
#define SET_WARM_RESET_FLAG TRUE
#undef GET_WARM_RESET_FLAG
#define GET_WARM_RESET_FLAG TRUE
#undef USES_REGISTER_TABLES
#define USES_REGISTER_TABLES TRUE
#undef BASE_FAMILY_PCI
#define BASE_FAMILY_PCI TRUE
#undef MODEL_SPECIFIC_PCI
#define MODEL_SPECIFIC_PCI TRUE
#undef BASE_FAMILY_MSR
#define BASE_FAMILY_MSR TRUE
#undef MODEL_SPECIFIC_MSR
#define MODEL_SPECIFIC_MSR TRUE
#undef BRAND_STRING1
#define BRAND_STRING1 TRUE
#undef BRAND_STRING2
#define BRAND_STRING2 TRUE
#undef BASE_FAMILY_HT_PCI
#define BASE_FAMILY_HT_PCI TRUE
#undef MODEL_SPECIFIC_HT_PCI
#define MODEL_SPECIFIC_HT_PCI TRUE
#undef BASE_FAMILY_WORKAROUNDS
#define BASE_FAMILY_WORKAROUNDS TRUE
#undef GET_PATCHES
#define GET_PATCHES TRUE
#undef GET_PATCHES_EQUIVALENCE_TABLE
#define GET_PATCHES_EQUIVALENCE_TABLE TRUE
#undef GET_SYSTEM_PM_TABLE
#define GET_SYSTEM_PM_TABLE TRUE
#undef GET_CACHE_INFO
#define GET_CACHE_INFO TRUE
#undef GET_PLATFORM_TYPE_SPECIFIC_INFO
#define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
#undef IS_NB_PSTATE_ENABLED
#define IS_NB_PSTATE_ENABLED TRUE
#endif
#if AGESA_ENTRY_INIT_POST == TRUE
#undef ID_POSITION_INITIAL_APICID
#define ID_POSITION_INITIAL_APICID TRUE
#undef GET_PSTATE_POWER
#define GET_PSTATE_POWER TRUE
#undef GET_PSTATE_FREQ
#define GET_PSTATE_FREQ TRUE
#undef TRANSITION_PSTATE
#define TRANSITION_PSTATE TRUE
#undef PROC_IDD_MAX
#define PROC_IDD_MAX TRUE
#undef GET_AP_CORE_NUMBER
#define GET_AP_CORE_NUMBER TRUE
#undef GET_PSTATE_REGISTER_INFO
#define GET_PSTATE_REGISTER_INFO TRUE
#undef GET_PSTATE_MAX_STATE
#define GET_PSTATE_MAX_STATE TRUE
#undef SET_PSTATE_LEVELING_REG
#define SET_PSTATE_LEVELING_REG TRUE
#undef SET_WARM_RESET_FLAG
#define SET_WARM_RESET_FLAG TRUE
#undef GET_WARM_RESET_FLAG
#define GET_WARM_RESET_FLAG TRUE
#undef SAVE_FEATURES
#define SAVE_FEATURES TRUE
#undef WRITE_FEATURES
#define WRITE_FEATURES TRUE
#undef GET_CFOH_REG
#define GET_CFOH_REG TRUE
#undef IS_NB_PSTATE_ENABLED
#define IS_NB_PSTATE_ENABLED TRUE
#endif
#if AGESA_ENTRY_INIT_ENV == TRUE
#endif
#if AGESA_ENTRY_INIT_MID == TRUE
#endif
#if AGESA_ENTRY_INIT_LATE == TRUE
#undef GET_AP_CORE_NUMBER
#define GET_AP_CORE_NUMBER TRUE
#undef GET_PSTATE_FREQ
#define GET_PSTATE_FREQ TRUE
#undef TRANSITION_PSTATE
#define TRANSITION_PSTATE TRUE
#undef PSTATE_TRANSITION_LATENCY
#define PSTATE_TRANSITION_LATENCY TRUE
#undef GET_WHEA_INIT
#define GET_WHEA_INIT TRUE
#undef GET_PLATFORM_TYPE_SPECIFIC_INFO
#define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
#undef GET_TSC_RATE
#define GET_TSC_RATE TRUE
#undef BRAND_STRING1
#define BRAND_STRING1 TRUE
#undef BRAND_STRING2
#define BRAND_STRING2 TRUE
#endif
#if AGESA_ENTRY_INIT_S3SAVE == TRUE
#endif
#if AGESA_ENTRY_INIT_RESUME == TRUE
#undef GET_CFOH_REG
#define GET_CFOH_REG TRUE
#endif
#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
#endif
#if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE
#undef ID_POSITION_INITIAL_APICID
#define ID_POSITION_INITIAL_APICID TRUE
#endif
/*
* Initialize PCI MMIO mask to 0
*/
#define FAMILY_MMIO_BASE_MASK (0ull)
/*
* Initialize all families to disabled
*/
#define OPT_F12_TABLE
#define OPT_F12_ID_TABLE
/*
* Install family specific support
*/
#if (OPTION_FAMILY12H == TRUE)
#include "OptionFamily12hInstall.h"
#endif
/*
* Process PCI MMIO mask
*/
// If size is 0, but base is not, break the build.
#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE == 0)
#error BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256
#endif
// If base is 0, but size is not, break the build.
#if (CFG_PCI_MMIO_BASE == 0) && (CFG_PCI_MMIO_SIZE != 0)
#error BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater
#endif
#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE != 0)
// Both are non-zero, begin further processing.
// Heap runs from 4MB to 8MB. Disallow any addresses below 8MB.
#if (CFG_PCI_MMIO_BASE < 0x800000)
#error BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater
#endif
// Break the build if the address is too high for the enabled families.
#if ((CFG_PCI_MMIO_BASE & FAMILY_MMIO_BASE_MASK) != 0)
#error BLDCFG: Invalid PCI MMIO base address for the installed CPU families
#endif
// If the size parameter is not valid, break the build.
#if (CFG_PCI_MMIO_SIZE != 1) && (CFG_PCI_MMIO_SIZE != 2) && (CFG_PCI_MMIO_SIZE != 4) && (CFG_PCI_MMIO_SIZE != 8) && (CFG_PCI_MMIO_SIZE != 16)
#if (CFG_PCI_MMIO_SIZE != 32) && (CFG_PCI_MMIO_SIZE != 64) && (CFG_PCI_MMIO_SIZE != 128) && (CFG_PCI_MMIO_SIZE != 256)
#error BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256
#endif
#endif
#define PCI_MMIO_ALIGNMENT ((0x100000 * CFG_PCI_MMIO_SIZE) - 1)
// If the base is not aligned according to size, break the build.
#if ((CFG_PCI_MMIO_BASE & PCI_MMIO_ALIGNMENT) != 0)
#error BLDCFG: Invalid PCI MMIO base -- must be properly aligned according to MMIO size
#endif
#undef PCI_MMIO_ALIGNMENT
#endif
/*
* Process sockets / modules
*/
#ifndef ADVCFG_PLATFORM_SOCKETS
#error BLDOPT Set Family supported sockets.
#endif
#ifndef ADVCFG_PLATFORM_MODULES
#error BLDOPT Set Family supported modules.
#endif
CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration =
{
ADVCFG_PLATFORM_SOCKETS,
ADVCFG_PLATFORM_MODULES
};
/*
* Instantiate global data needed for processor identification
*/
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CpuSupportedFamiliesArray[] =
{
OPT_F12_TABLE
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CpuSupportedFamiliesTable =
{
(sizeof (CpuSupportedFamiliesArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&CpuSupportedFamiliesArray[0]
};
CONST CPU_LOGICAL_ID_FAMILY_XLAT ROMDATA CpuSupportedFamilyIdArray[] =
{
OPT_F12_ID_TABLE
};
CONST CPU_FAMILY_ID_XLAT_TABLE ROMDATA CpuSupportedFamilyIdTable =
{
(sizeof (CpuSupportedFamilyIdArray) / sizeof (CPU_LOGICAL_ID_FAMILY_XLAT)),
CpuSupportedFamilyIdArray
};

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src/vendorcode/amd/agesa/f12/Config/OptionCpuFeaturesInstall.h
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/* $NoKeywords:$ */
/**
* @file
*
* Install of multiple CPU features.
*
* Aggregates enabled CPU features into a list for the dispatcher to process.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_CPU_FEATURES_INSTALL_H_
#define _OPTION_CPU_FEATURES_INSTALL_H_
#include "OptionHwC1eInstall.h"
#include "OptionMsgBasedC1eInstall.h"
#include "OptionSwC1eInstall.h"
#include "OptionL3FeaturesInstall.h"
#include "OptionCpuCoreLevelingInstall.h"
#include "OptionIoCstateInstall.h"
#include "OptionC6Install.h"
#include "OptionCpbInstall.h"
#include "OptionCpuCacheFlushOnHaltInstall.h"
#include "OptionLowPwrPstateInstall.h"
#include "OptionPreserveMailboxInstall.h"
CONST CPU_FEATURE_DESCRIPTOR* ROMDATA SupportedCpuFeatureList[] =
{
OPTION_HW_C1E_FEAT
OPTION_MSG_BASED_C1E_FEAT
OPTION_SW_C1E_FEAT
OPTION_L3_FEAT
OPTION_CPU_CORE_LEVELING_FEAT
OPTION_IO_CSTATE_FEAT
OPTION_C6_STATE_FEAT
OPTION_CPB_FEAT
OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT // this function should be run before creating ACPI objects and after Pstate initialization
OPTION_PRESERVE_MAILBOX_FEAT
NULL
};
#endif // _OPTION_CPU_FEATURES_INSTALL_H_

206
src/vendorcode/amd/agesa/f12/Config/OptionDmiInstall.h
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@ -1,206 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: DMI
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_DMI_INSTALL_H_
#define _OPTION_DMI_INSTALL_H_
#include "cpuLateInit.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#if AGESA_ENTRY_INIT_LATE == TRUE
#ifndef OPTION_DMI
#error BLDOPT: Option not defined: "OPTION_DMI"
#endif
#if OPTION_DMI == TRUE
OPTION_DMI_FEATURE GetDmiInfoMain;
OPTION_DMI_RELEASE_BUFFER ReleaseDmiBuffer;
#define USER_DMI_OPTION &GetDmiInfoMain
#define USER_DMI_RELEASE_BUFFER &ReleaseDmiBuffer
// This additional check keeps AP launch routines from being unnecessarily included
// in single socket systems.
#if OPTION_MULTISOCKET == TRUE
#define CPU_DMI_AP_GET_TYPE4_TYPE7 {AP_LATE_TASK_GET_TYPE4_TYPE7, (IMAGE_ENTRY) GetType4Type7Info},
#else
#define CPU_DMI_AP_GET_TYPE4_TYPE7
#endif
// Family 10
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
extern PROC_FAMILY_TABLE ProcFamily10DmiTable;
#define FAM10_DMI_SUPPORT FAM10_ENABLED,
#define FAM10_DMI_TABLE &ProcFamily10DmiTable,
#else
#define FAM10_DMI_SUPPORT
#define FAM10_DMI_TABLE
#endif
#else
#define FAM10_DMI_SUPPORT
#define FAM10_DMI_TABLE
#endif
// Family 12
#ifdef OPTION_FAMILY12H
#if OPTION_FAMILY12H == TRUE
extern PROC_FAMILY_TABLE ProcFamily12DmiTable;
#define FAM12_DMI_SUPPORT FAM12_ENABLED,
#define FAM12_DMI_TABLE &ProcFamily12DmiTable,
#else
#define FAM12_DMI_SUPPORT
#define FAM12_DMI_TABLE
#endif
#else
#define FAM12_DMI_SUPPORT
#define FAM12_DMI_TABLE
#endif
// Family 14
#ifdef OPTION_FAMILY14H
#if OPTION_FAMILY14H == TRUE
extern PROC_FAMILY_TABLE ProcFamily14DmiTable;
#define FAM14_DMI_SUPPORT FAM14_ENABLED,
#define FAM14_DMI_TABLE &ProcFamily14DmiTable,
#else
#define FAM14_DMI_SUPPORT
#define FAM14_DMI_TABLE
#endif
#else
#define FAM14_DMI_SUPPORT
#define FAM14_DMI_TABLE
#endif
// Family 15
#ifdef OPTION_FAMILY15H
#if OPTION_FAMILY15H == TRUE
#if OPTION_FAMILY15H_OR == TRUE
extern PROC_FAMILY_TABLE ProcFamily15OrDmiTable;
#define FAM15_OR_DMI_SUPPORT FAM15_OR_ENABLED,
#define FAM15_OR_DMI_TABLE &ProcFamily15OrDmiTable,
#else
#define FAM15_OR_DMI_SUPPORT
#define FAM15_OR_DMI_TABLE
#endif
#define FAM15_TN_DMI_SUPPORT
#define FAM15_TN_DMI_TABLE
#else
#define FAM15_OR_DMI_SUPPORT
#define FAM15_OR_DMI_TABLE
#define FAM15_TN_DMI_SUPPORT
#define FAM15_TN_DMI_TABLE
#endif
#else
#define FAM15_OR_DMI_SUPPORT
#define FAM15_OR_DMI_TABLE
#define FAM15_TN_DMI_SUPPORT
#define FAM15_TN_DMI_TABLE
#endif
#else
OPTION_DMI_FEATURE GetDmiInfoStub;
OPTION_DMI_RELEASE_BUFFER ReleaseDmiBufferStub;
#define USER_DMI_OPTION GetDmiInfoStub
#define USER_DMI_RELEASE_BUFFER ReleaseDmiBufferStub
#define FAM10_DMI_SUPPORT
#define FAM10_DMI_TABLE
#define FAM12_DMI_SUPPORT
#define FAM12_DMI_TABLE
#define FAM14_DMI_SUPPORT
#define FAM14_DMI_TABLE
#define FAM15_OR_DMI_SUPPORT
#define FAM15_OR_DMI_TABLE
#define FAM15_TN_DMI_SUPPORT
#define FAM15_TN_DMI_TABLE
#define CPU_DMI_AP_GET_TYPE4_TYPE7
#endif
#else
OPTION_DMI_FEATURE GetDmiInfoStub;
OPTION_DMI_RELEASE_BUFFER ReleaseDmiBufferStub;
#define USER_DMI_OPTION GetDmiInfoStub
#define USER_DMI_RELEASE_BUFFER ReleaseDmiBufferStub
#define FAM10_DMI_SUPPORT
#define FAM10_DMI_TABLE
#define FAM12_DMI_SUPPORT
#define FAM12_DMI_TABLE
#define FAM14_DMI_SUPPORT
#define FAM14_DMI_TABLE
#define FAM15_OR_DMI_SUPPORT
#define FAM15_OR_DMI_TABLE
#define FAM15_TN_DMI_SUPPORT
#define FAM15_TN_DMI_TABLE
#define CPU_DMI_AP_GET_TYPE4_TYPE7
#endif
/// DMI supported families enum
typedef enum {
FAM10_DMI_SUPPORT ///< Conditionally define F10 support
FAM12_DMI_SUPPORT ///< Conditionally define F12 support
FAM14_DMI_SUPPORT ///< Conditionally define F14 support
FAM15_OR_DMI_SUPPORT ///< Conditionally define F15 OR support
FAM15_TN_DMI_SUPPORT ///< Conditionally define F15 TN support
NUM_DMI_FAMILIES ///< Number of installed families
} AGESA_DMI_SUPPORTED_FAM;
/* Declare the Family List. An array of pointers to tables that each describe a family */
CONST PROC_FAMILY_TABLE ROMDATA *ProcTables[] = {
FAM10_DMI_TABLE
FAM12_DMI_TABLE
FAM14_DMI_TABLE
FAM15_OR_DMI_TABLE
FAM15_TN_DMI_TABLE
NULL
};
/* Declare the instance of the DMI option configuration structure */
CONST OPTION_DMI_CONFIGURATION ROMDATA OptionDmiConfiguration = {
DMI_STRUCT_VERSION,
USER_DMI_OPTION,
USER_DMI_RELEASE_BUFFER,
NUM_DMI_FAMILIES,
(VOID *((*)[])) &ProcTables // Compiler says array size must match struct decl
};
#endif // _OPTION_DMI_INSTALL_H_

694
src/vendorcode/amd/agesa/f12/Config/OptionFamily12hInstall.h
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@ -1,694 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of family 12h support
*
* This file generates the defaults tables for family 12h processors.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 49967 $ @e \$Date: 2011-03-31 11:15:12 +0800 (Thu, 31 Mar 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_FAMILY_12H_INSTALL_H_
#define _OPTION_FAMILY_12H_INSTALL_H_
#include "OptionFamily12hEarlySample.h"
/*
* Common Family 12h routines
*/
extern F_CPU_DISABLE_PSTATE F12DisablePstate;
extern F_CPU_TRANSITION_PSTATE F12TransitionPstate;
extern F_CPU_GET_TSC_RATE F12GetTscRate;
extern F_CPU_GET_NB_FREQ F12GetCurrentNbFrequency;
extern F_CPU_GET_NB_PSTATE_INFO F12GetNbPstateInfo;
extern F_CPU_IS_NBCOF_INIT_NEEDED F12GetNbCofVidUpdate;
extern F_CPU_AP_INITIAL_LAUNCH F12LaunchApCore;
extern F_CPU_GET_IDD_MAX F12GetProcIddMax;
extern F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE F12GetApMailboxFromHardware;
extern F_CPU_GET_AP_CORE_NUMBER F12GetApCoreNumber;
extern F_CORE_ID_POSITION_IN_INITIAL_APIC_ID F12CpuAmdCoreIdPositionInInitialApicId;
extern F_CPU_SET_DOWN_CORE_REGISTER F12SetDownCoreRegister;
extern F_CPU_SET_WARM_RESET_FLAG F12SetAgesaWarmResetFlag;
extern F_CPU_GET_WARM_RESET_FLAG F12GetAgesaWarmResetFlag;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12BrandIdString1;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12BrandIdString2;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12CacheInfo;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12SysPmTable;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12WheaInitData;
//extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetEmptyArray;
extern F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO F12GetPlatformTypeSpecificInfo;
extern CONST REGISTER_TABLE ROMDATA F12PciRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F12PerCorePciRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F12MsrRegisterTable;
extern F_CPU_NUMBER_OF_PHYSICAL_CORES F12GetNumberOfPhysicalCores;
extern F_GET_EARLY_INIT_TABLE GetCommonEarlyInitOnCoreTable;
extern F_IS_NB_PSTATE_ENABLED F12IsNbPstateEnabled;
#if OPTION_EARLY_SAMPLES == TRUE
extern CONST REGISTER_TABLE ROMDATA F12EarlySampleMsrRegisterTable;
#endif
/*
* Install family 12h model 0 support
*/
#ifdef OPTION_FAMILY12H_LN
#if OPTION_FAMILY12H_LN == TRUE
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12LnMicroCodePatchesStruct;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12LnMicrocodeEquivalenceTable;
#if USES_REGISTER_TABLES == TRUE
CONST REGISTER_TABLE ROMDATA *F12LnRegisterTables[] =
{
#if BASE_FAMILY_PCI == TRUE
&F12PciRegisterTable,
#endif
#if BASE_FAMILY_PCI == TRUE
&F12PerCorePciRegisterTable,
#endif
#if BASE_FAMILY_MSR == TRUE
&F12MsrRegisterTable,
#if OPTION_EARLY_SAMPLES == TRUE
&F12EarlySampleMsrRegisterTable,
#endif
#endif
// the end.
NULL
};
#endif
#if USES_REGISTER_TABLES == TRUE
CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F12LnTableEntryTypeDescriptors[] =
{
{MsrRegister, SetRegisterForMsrEntry},
{PciRegister, SetRegisterForPciEntry},
{FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
{ProfileFixup, (PF_DO_TABLE_ENTRY)CommonVoid},
// End
{TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
};
#endif
CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF12LnServices =
{
0,
#if DISABLE_PSTATE == TRUE
F12DisablePstate,
#else
(PF_CPU_DISABLE_PSTATE) CommonAssert,
#endif
#if TRANSITION_PSTATE == TRUE
F12TransitionPstate,
#else
(PF_CPU_TRANSITION_PSTATE) CommonAssert,
#endif
#if PROC_IDD_MAX == TRUE
F12GetProcIddMax,
#else
(PF_CPU_GET_IDD_MAX) CommonAssert,
#endif
#if GET_TSC_RATE == TRUE
F12GetTscRate,
#else
(PF_CPU_GET_TSC_RATE) CommonAssert,
#endif
#if GET_NB_FREQ == TRUE
F12GetCurrentNbFrequency,
#else
(PF_CPU_GET_NB_FREQ) CommonAssert,
#endif
#if GET_NB_FREQ == TRUE
(PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
#else
(PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
#endif
#if GET_NB_FREQ == TRUE
F12GetNbPstateInfo,
#else
(PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
#endif
#if IS_NBCOF_INIT_NEEDED == TRUE
F12GetNbCofVidUpdate,
#else
(PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
#endif
#if GET_NB_IDD_MAX == TRUE
(PF_CPU_GET_NB_IDD_MAX) CommonAssert,
#else
(PF_CPU_GET_NB_IDD_MAX) CommonAssert,
#endif
#if AP_INITIAL_LAUNCH == TRUE
F12LaunchApCore,
#else
(PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
#endif
#if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
F12GetNumberOfPhysicalCores,
#else
(PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert,
#endif
#if GET_AP_MAILBOX_FROM_HW == TRUE
F12GetApMailboxFromHardware,
#else
(PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
#endif
#if SET_AP_CORE_NUMBER == TRUE
(PF_CPU_SET_AP_CORE_NUMBER) CommonVoid,
#else
(PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
#endif
#if GET_AP_CORE_NUMBER == TRUE
F12GetApCoreNumber,
#else
(PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
#endif
#if TRANSFER_AP_CORE_NUMBER == TRUE
(PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonVoid,
#else
(PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
#endif
#if ID_POSITION_INITIAL_APICID == TRUE
F12CpuAmdCoreIdPositionInInitialApicId,
#else
(PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
#endif
#if SAVE_FEATURES == TRUE
(PF_CPU_SAVE_FEATURES) CommonVoid,
#else
(PF_CPU_SAVE_FEATURES) CommonAssert,
#endif
#if WRITE_FEATURES == TRUE
(PF_CPU_WRITE_FEATURES) CommonVoid,
#else
(PF_CPU_WRITE_FEATURES) CommonAssert,
#endif
#if SET_WARM_RESET_FLAG == TRUE
F12SetAgesaWarmResetFlag,
#else
(PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
#endif
#if GET_WARM_RESET_FLAG == TRUE
F12GetAgesaWarmResetFlag,
#else
(PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
#endif
#if BRAND_STRING1 == TRUE
GetF12BrandIdString1,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if BRAND_STRING2 == TRUE
GetF12BrandIdString2,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PATCHES == TRUE
GetF12LnMicroCodePatchesStruct,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
GetF12LnMicrocodeEquivalenceTable,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_CACHE_INFO == TRUE
GetF12CacheInfo,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_SYSTEM_PM_TABLE == TRUE
GetF12SysPmTable,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_WHEA_INIT == TRUE
GetF12WheaInitData,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
F12GetPlatformTypeSpecificInfo,
#else
(PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
#endif
#if IS_NB_PSTATE_ENABLED == TRUE
F12IsNbPstateEnabled,
#else
(PF_IS_NB_PSTATE_ENABLED) CommonAssert,
#endif
#if (BASE_FAMILY_HT_PCI == TRUE)
(PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
#else
(PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
#endif
#if (BASE_FAMILY_HT_PCI == TRUE)
(PF_SET_HT_PHY_REGISTER) CommonVoid,
#else
(PF_SET_HT_PHY_REGISTER) CommonAssert,
#endif
#if BASE_FAMILY_PCI == TRUE
(PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
#else
(PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
#endif
#if USES_REGISTER_TABLES == TRUE
(REGISTER_TABLE **) F12LnRegisterTables,
#else
NULL,
#endif
#if USES_REGISTER_TABLES == TRUE
(TABLE_ENTRY_TYPE_DESCRIPTOR *) F12LnTableEntryTypeDescriptors,
#else
NULL,
#endif
#if MODEL_SPECIFIC_HT_PCI == TRUE
NULL,
#else
NULL,
#endif
NULL,
InitCacheDisabled,
#if AGESA_ENTRY_INIT_EARLY == TRUE
GetCommonEarlyInitOnCoreTable
#else
(PF_GET_EARLY_INIT_TABLE) CommonVoid
#endif
};
#define LN_SOCKETS 1
#define LN_MODULES 1
#define LN_RECOVERY_SOCKETS 1
#define LN_RECOVERY_MODULES 1
extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF12LnLogicalIdAndRev;
#define OPT_F12_LN_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF12LnLogicalIdAndRev,
#ifndef ADVCFG_PLATFORM_SOCKETS
#define ADVCFG_PLATFORM_SOCKETS LN_SOCKETS
#else
#if ADVCFG_PLATFORM_SOCKETS < LN_SOCKETS
#undef ADVCFG_PLATFORM_SOCKETS
#define ADVCFG_PLATFORM_SOCKETS LN_SOCKETS
#endif
#endif
#ifndef ADVCFG_PLATFORM_MODULES
#define ADVCFG_PLATFORM_MODULES LN_MODULES
#else
#if ADVCFG_PLATFORM_MODULES < LN_MODULES
#undef ADVCFG_PLATFORM_MODULES
#define ADVCFG_PLATFORM_MODULES LN_MODULES
#endif
#endif
#if GET_PATCHES == TRUE
#define F12_LN_UCODE_02
#define F12_LN_UCODE_0E
#define F12_LN_UCODE_0F
#if AGESA_ENTRY_INIT_EARLY == TRUE
extern CONST MICROCODE_PATCHES ROMDATA CpuF12MicrocodePatch03000027;
#undef F12_LN_UCODE_0F
#define F12_LN_UCODE_0F &CpuF12MicrocodePatch03000027,
#if OPTION_EARLY_SAMPLES == TRUE
extern CONST MICROCODE_PATCHES ROMDATA CpuF12MicrocodePatch03000002;
extern CONST MICROCODE_PATCHES ROMDATA CpuF12MicrocodePatch0300000e;
#undef F12_LN_UCODE_02
#define F12_LN_UCODE_02 &CpuF12MicrocodePatch03000002,
#undef F12_LN_UCODE_0E
#define F12_LN_UCODE_0E &CpuF12MicrocodePatch0300000e,
#endif
#endif
CONST MICROCODE_PATCHES ROMDATA *CpuF12LnMicroCodePatchArray[] =
{
F12_LN_UCODE_0F
F12_LN_UCODE_0E
F12_LN_UCODE_02
NULL
};
CONST UINT8 ROMDATA CpuF12LnNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF12LnMicroCodePatchArray) / sizeof (CpuF12LnMicroCodePatchArray[0])) - 1);
#endif
#if OPTION_EARLY_SAMPLES == TRUE
extern F_F12_ES_NB_PSTATE_INIT F12NbPstateInitEarlySampleHook;
extern F_F12_ES_POWER_PLANE_INIT F12PowerPlaneInitEarlySampleHook;
CONST F12_ES_CORE_SUPPORT ROMDATA F12EarlySampleCoreSupport =
{
#if AGESA_ENTRY_INIT_EARLY == TRUE
F12PowerPlaneInitEarlySampleHook,
#else
(PF_F12_ES_POWER_PLANE_INIT) CommonAssert,
#endif
#if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE)
F12NbPstateInitEarlySampleHook
#else
(PF_F12_ES_NB_PSTATE_INIT) CommonAssert
#endif
};
#else
CONST F12_ES_CORE_SUPPORT ROMDATA F12EarlySampleCoreSupport =
{
#if AGESA_ENTRY_INIT_EARLY == TRUE
(PF_F12_ES_POWER_PLANE_INIT) CommonVoid,
#else
(PF_F12_ES_POWER_PLANE_INIT) CommonAssert,
#endif
#if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE)
(PF_F12_ES_NB_PSTATE_INIT) CommonVoid
#else
(PF_F12_ES_NB_PSTATE_INIT) CommonAssert
#endif
};
#endif
#define OPT_F12_LN_CPU {AMD_FAMILY_12_LN, &cpuF12LnServices},
#else // OPTION_FAMILY12H_LN == TRUE
#define OPT_F12_LN_CPU
#define OPT_F12_LN_ID
#endif // OPTION_FAMILY12H_LN == TRUE
#else // defined (OPTION_FAMILY12H_LN)
#define OPT_F12_LN_CPU
#define OPT_F12_LN_ID
#endif // defined (OPTION_FAMILY12H_LN)
/*
* Install unknown family 12h support
*/
#if USES_REGISTER_TABLES == TRUE
CONST REGISTER_TABLE ROMDATA *F12UnknownRegisterTables[] =
{
#if BASE_FAMILY_PCI == TRUE
&F12PciRegisterTable,
#endif
#if BASE_FAMILY_PCI == TRUE
&F12PerCorePciRegisterTable,
#endif
#if BASE_FAMILY_MSR == TRUE
&F12MsrRegisterTable,
#endif
// the end.
NULL
};
#endif
#if USES_REGISTER_TABLES == TRUE
CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F12UnknownTableEntryTypeDescriptors[] =
{
{MsrRegister, SetRegisterForMsrEntry},
{PciRegister, SetRegisterForPciEntry},
{FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
{ProfileFixup, (PF_DO_TABLE_ENTRY)CommonVoid},
// End
{TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
};
#endif
CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF12UnknownServices =
{
0,
#if DISABLE_PSTATE == TRUE
F12DisablePstate,
#else
(PF_CPU_DISABLE_PSTATE) CommonAssert,
#endif
#if TRANSITION_PSTATE == TRUE
F12TransitionPstate,
#else
(PF_CPU_TRANSITION_PSTATE) CommonAssert,
#endif
#if PROC_IDD_MAX == TRUE
F12GetProcIddMax,
#else
(PF_CPU_GET_IDD_MAX) CommonAssert,
#endif
#if GET_TSC_RATE == TRUE
F12GetTscRate,
#else
(PF_CPU_GET_TSC_RATE) CommonAssert,
#endif
#if GET_NB_FREQ == TRUE
F12GetCurrentNbFrequency,
#else
(PF_CPU_GET_NB_FREQ) CommonAssert,
#endif
#if GET_NB_FREQ == TRUE
(PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
#else
(PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
#endif
#if GET_NB_FREQ == TRUE
F12GetNbPstateInfo,
#else
(PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
#endif
#if IS_NBCOF_INIT_NEEDED == TRUE
F12GetNbCofVidUpdate,
#else
(PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
#endif
#if GET_NB_IDD_MAX == TRUE
(PF_CPU_GET_NB_IDD_MAX) CommonAssert,
#else
(PF_CPU_GET_NB_IDD_MAX) CommonAssert,
#endif
#if AP_INITIAL_LAUNCH == TRUE
F12LaunchApCore,
#else
(PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
#endif
#if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
F12GetNumberOfPhysicalCores,
#else
(PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert,
#endif
#if GET_AP_MAILBOX_FROM_HW == TRUE
F12GetApMailboxFromHardware,
#else
(PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
#endif
#if SET_AP_CORE_NUMBER == TRUE
(PF_CPU_SET_AP_CORE_NUMBER) CommonVoid,
#else
(PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
#endif
#if GET_AP_CORE_NUMBER == TRUE
F12GetApCoreNumber,
#else
(PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
#endif
#if TRANSFER_AP_CORE_NUMBER == TRUE
(PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonVoid,
#else
(PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
#endif
#if ID_POSITION_INITIAL_APICID == TRUE
F12CpuAmdCoreIdPositionInInitialApicId,
#else
(PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
#endif
#if SAVE_FEATURES == TRUE
(PF_CPU_SAVE_FEATURES) CommonVoid,
#else
(PF_CPU_SAVE_FEATURES) CommonAssert,
#endif
#if WRITE_FEATURES == TRUE
(PF_CPU_WRITE_FEATURES) CommonVoid,
#else
(PF_CPU_WRITE_FEATURES) CommonAssert,
#endif
#if SET_WARM_RESET_FLAG == TRUE
F12SetAgesaWarmResetFlag,
#else
(PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
#endif
#if GET_WARM_RESET_FLAG == TRUE
F12GetAgesaWarmResetFlag,
#else
(PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
#endif
#if BRAND_STRING1 == TRUE
GetF12BrandIdString1,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if BRAND_STRING2 == TRUE
GetF12BrandIdString2,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PATCHES == TRUE
GetEmptyArray,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
GetEmptyArray,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_CACHE_INFO == TRUE
GetF12CacheInfo,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_SYSTEM_PM_TABLE == TRUE
GetF12SysPmTable,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_WHEA_INIT == TRUE
GetF12WheaInitData,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
F12GetPlatformTypeSpecificInfo,
#else
(PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
#endif
#if IS_NB_PSTATE_ENABLED == TRUE
F12IsNbPstateEnabled,
#else
(PF_IS_NB_PSTATE_ENABLED) CommonAssert,
#endif
#if (BASE_FAMILY_HT_PCI == TRUE)
(PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
#else
(PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonAssert,
#endif
#if (BASE_FAMILY_HT_PCI == TRUE)
(PF_SET_HT_PHY_REGISTER) CommonVoid,
#else
(PF_SET_HT_PHY_REGISTER) CommonAssert,
#endif
#if BASE_FAMILY_PCI == TRUE
(PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
#else
(PF_GET_NEXT_HT_LINK_FEATURES) CommonAssert,
#endif
#if USES_REGISTER_TABLES == TRUE
(REGISTER_TABLE **) F12UnknownRegisterTables,
#else
NULL,
#endif
#if USES_REGISTER_TABLES == TRUE
(TABLE_ENTRY_TYPE_DESCRIPTOR *) F12UnknownTableEntryTypeDescriptors,
#else
NULL,
#endif
#if MODEL_SPECIFIC_HT_PCI == TRUE
NULL,
#else
NULL,
#endif
NULL,
InitCacheDisabled,
#if AGESA_ENTRY_INIT_EARLY == TRUE
GetCommonEarlyInitOnCoreTable
#else
(PF_GET_EARLY_INIT_TABLE) CommonVoid
#endif
};
// Family 12h maximum base address is 40 bits. Limit BLDCFG to 40 bits, if appropriate.
#if (FAMILY_MMIO_BASE_MASK < 0xFFFFFF0000000000ull)
#undef FAMILY_MMIO_BASE_MASK
#define FAMILY_MMIO_BASE_MASK (0xFFFFFF0000000000ull)
#endif
#undef OPT_F12_ID_TABLE
#define OPT_F12_ID_TABLE {0x12ul, {AMD_FAMILY_12, AMD_F12_UNKNOWN}, F12LogicalIdTable, (sizeof (F12LogicalIdTable) / sizeof (F12LogicalIdTable[0]))},
#define OPT_F12_UNKNOWN_CPU {AMD_FAMILY_12, &cpuF12UnknownServices},
#undef OPT_F12_TABLE
#define OPT_F12_TABLE OPT_F12_LN_CPU OPT_F12_UNKNOWN_CPU
#if OPTION_FS1_SOCKET_SUPPORT == TRUE
extern CONST CPU_BRAND_TABLE ROMDATA F12LnBrandIdString1ArrayFs1;
extern CONST CPU_BRAND_TABLE ROMDATA F12LnBrandIdString2ArrayFs1;
#define F12_FS1_BRANDSTRING1 &F12LnBrandIdString1ArrayFs1,
#define F12_FS1_BRANDSTRING2 &F12LnBrandIdString2ArrayFs1,
#else
#define F12_FS1_BRANDSTRING1
#define F12_FS1_BRANDSTRING2
#endif
#if OPTION_FM1_SOCKET_SUPPORT == TRUE
extern CONST CPU_BRAND_TABLE ROMDATA F12LnBrandIdString1ArrayFm1;
extern CONST CPU_BRAND_TABLE ROMDATA F12LnBrandIdString2ArrayFm1;
#define F12_FM1_BRANDSTRING1 &F12LnBrandIdString1ArrayFm1,
#define F12_FM1_BRANDSTRING2 &F12LnBrandIdString2ArrayFm1,
#else
#define F12_FM1_BRANDSTRING1
#define F12_FM1_BRANDSTRING2
#endif
#if OPTION_FP1_SOCKET_SUPPORT == TRUE
#define F12_FP1_BRANDSTRING1 NULL,
#define F12_FP1_BRANDSTRING2 NULL,
#else
#define F12_FP1_BRANDSTRING1
#define F12_FP1_BRANDSTRING2
#endif
#if BRAND_STRING1 == TRUE
CONST CPU_BRAND_TABLE ROMDATA *F12BrandIdString1Tables[] =
{
F12_FS1_BRANDSTRING1
F12_FM1_BRANDSTRING1
F12_FP1_BRANDSTRING1
};
CONST UINT8 F12BrandIdString1TableCount = (sizeof (F12BrandIdString1Tables) / sizeof (F12BrandIdString1Tables[0]));
#endif
#if BRAND_STRING2 == TRUE
CONST CPU_BRAND_TABLE ROMDATA *F12BrandIdString2Tables[] =
{
F12_FS1_BRANDSTRING2
F12_FM1_BRANDSTRING2
F12_FP1_BRANDSTRING2
};
CONST UINT8 F12BrandIdString2TableCount = (sizeof (F12BrandIdString2Tables) / sizeof (F12BrandIdString2Tables[0]));
#endif
CONST PF_CPU_GET_SUBFAMILY_ID_ARRAY ROMDATA F12LogicalIdTable[] =
{
OPT_F12_LN_ID
};
#endif // _OPTION_FAMILY_12H_INSTALL_H_

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src/vendorcode/amd/agesa/f12/Config/OptionFchInstall.h
View File

@ -1,928 +0,0 @@
/*********************************************************************************
;
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;*********************************************************************************/
#ifndef _OPTION_FCH_INSTALL_H_
#define _OPTION_FCH_INSTALL_H_
#include "AmdFch.h"
#ifndef FCH_SUPPORT
#define FCH_SUPPORT FALSE
#endif
/* ACPI block register offset definitions */
#define PM1_STATUS_OFFSET 0x00
#define PM1_ENABLE_OFFSET 0x02
#define PM_CONTROL_OFFSET 0x04
#define PM_TIMER_OFFSET 0x08
#define CPU_CONTROL_OFFSET 0x10
#define EVENT_STATUS_OFFSET 0x20
#define EVENT_ENABLE_OFFSET 0x24
#if FCH_SUPPORT == TRUE
/*
* FCH subfunctions
*/
#ifdef AGESA_ENTRY_INIT_RESET
#if AGESA_ENTRY_INIT_RESET == TRUE
extern FCH_TASK_ENTRY FchInitResetHwAcpiP;
extern FCH_TASK_ENTRY FchInitResetHwAcpi;
extern FCH_TASK_ENTRY FchInitResetAb;
extern FCH_TASK_ENTRY FchInitResetSpi;
extern FCH_TASK_ENTRY FchInitResetGec;
extern FCH_TASK_ENTRY FchInitResetSata;
extern FCH_TASK_ENTRY FchInitResetLpc;
extern FCH_TASK_ENTRY FchInitResetPcib;
extern FCH_TASK_ENTRY FchInitResetPcie;
extern FCH_TASK_ENTRY FchInitResetGpp;
extern FCH_TASK_ENTRY FchInitResetUsb;
extern FCH_TASK_ENTRY FchInitResetEhci;
extern FCH_TASK_ENTRY FchInitResetOhci;
extern FCH_TASK_ENTRY FchInitResetXhci;
extern FCH_TASK_ENTRY FchInitResetImc;
#endif
#endif
#ifdef AGESA_ENTRY_INIT_ENV
#if AGESA_ENTRY_INIT_ENV == TRUE
extern FCH_TASK_ENTRY FchInitEnvUsbXhci;
extern FCH_TASK_ENTRY FchInitEnvUsbOhci;
extern FCH_TASK_ENTRY FchInitEnvUsbEhci;
extern FCH_TASK_ENTRY FchInitEnvUsb;
extern FCH_TASK_ENTRY FchInitEnvAb;
extern FCH_TASK_ENTRY FchInitEnvGpp;
extern FCH_TASK_ENTRY FchInitEnvPcie;
extern FCH_TASK_ENTRY FchInitEnvPcib;
extern FCH_TASK_ENTRY FchInitEnvHwAcpiP;
extern FCH_TASK_ENTRY FchInitEnvHwAcpi;
extern FCH_TASK_ENTRY FchInitEnvAbSpecial;
extern FCH_TASK_ENTRY FchInitEnvSpi;
extern FCH_TASK_ENTRY FchInitEnvGec;
extern FCH_TASK_ENTRY FchInitEnvSata;
extern FCH_TASK_ENTRY FchInitEnvIde;
extern FCH_TASK_ENTRY FchInitEnvSd;
extern FCH_TASK_ENTRY FchInitEnvIr;
extern FCH_TASK_ENTRY FchInitEnvAzalia;
extern FCH_TASK_ENTRY FchInitEnvHwm;
extern FCH_TASK_ENTRY FchInitEnvImc;
#endif
#endif
#ifdef AGESA_ENTRY_INIT_MID
#if AGESA_ENTRY_INIT_MID == TRUE
extern FCH_TASK_ENTRY FchInitMidHwm;
extern FCH_TASK_ENTRY FchInitMidAzalia;
extern FCH_TASK_ENTRY FchInitMidGec;
extern FCH_TASK_ENTRY FchInitMidSata;
extern FCH_TASK_ENTRY FchInitMidIde;
extern FCH_TASK_ENTRY FchInitMidAb;
extern FCH_TASK_ENTRY FchInitMidUsb;
extern FCH_TASK_ENTRY FchInitMidUsbEhci;
extern FCH_TASK_ENTRY FchInitMidUsbOhci;
extern FCH_TASK_ENTRY FchInitMidUsbXhci;
extern FCH_TASK_ENTRY FchInitMidImc;
#endif
#endif
#ifdef AGESA_ENTRY_INIT_LATE
#if AGESA_ENTRY_INIT_LATE == TRUE
extern FCH_TASK_ENTRY FchInitLateHwAcpi;
extern FCH_TASK_ENTRY FchInitLateSpi;
extern FCH_TASK_ENTRY FchInitLateGec;
extern FCH_TASK_ENTRY FchInitLateSata;
extern FCH_TASK_ENTRY FchInitLateIde;
extern FCH_TASK_ENTRY FchInitLatePcib;
extern FCH_TASK_ENTRY FchInitLateAb;
extern FCH_TASK_ENTRY FchInitLatePcie;
extern FCH_TASK_ENTRY FchInitLateGpp;
extern FCH_TASK_ENTRY FchInitLateUsb;
extern FCH_TASK_ENTRY FchInitLateUsbEhci;
extern FCH_TASK_ENTRY FchInitLateUsbOhci;
extern FCH_TASK_ENTRY FchInitLateUsbXhci;
extern FCH_TASK_ENTRY FchInitLateImc;
extern FCH_TASK_ENTRY FchInitLateAzalia;
extern FCH_TASK_ENTRY FchInitLateHwm;
#endif
#endif
extern FCH_TASK_ENTRY FchTaskDummy;
/* FCH Interface entries */
extern FCH_INIT CommonFchInitStub;
/* FCH Interface entries */
#ifdef AGESA_ENTRY_INIT_RESET
#if AGESA_ENTRY_INIT_RESET == TRUE
extern FCH_INIT FchInitReset;
extern FCH_INIT FchResetConstructor;
#define FP_FCH_INIT_RESET &FchInitReset
#define FP_FCH_INIT_RESET_CONSTRUCT &FchResetConstructor
#else
#define FP_FCH_INIT_RESET &CommonFchInitStub
#define FP_FCH_INIT_RESET_CONSTRUCT &CommonFchInitStub
#endif
#endif
#ifdef AGESA_ENTRY_INIT_ENV
#if AGESA_ENTRY_INIT_ENV == TRUE
extern FCH_INIT FchInitEnv;
extern FCH_INIT FchEnvConstructor;
#define FP_FCH_INIT_ENV &FchInitEnv
#define FP_FCH_INIT_ENV_CONSTRUCT &FchEnvConstructor
#else
#define FP_FCH_INIT_ENV &CommonFchInitStub
#define FP_FCH_INIT_ENV_CONSTRUCT &CommonFchInitStub
#endif
#endif
#ifdef AGESA_ENTRY_INIT_MID
#if AGESA_ENTRY_INIT_MID == TRUE
extern FCH_INIT FchInitMid;
extern FCH_INIT FchMidConstructor;
#define FP_FCH_INIT_MID &FchInitMid
#define FP_FCH_INIT_MID_CONSTRUCT &FchMidConstructor
#else
#define FP_FCH_INIT_MID &CommonFchInitStub
#define FP_FCH_INIT_MID_CONSTRUCT &CommonFchInitStub
#endif
#endif
#ifdef AGESA_ENTRY_INIT_LATE
#if AGESA_ENTRY_INIT_LATE == TRUE
extern FCH_INIT FchInitLate;
extern FCH_INIT FchLateConstructor;
#define FP_FCH_INIT_LATE &FchInitLate
#define FP_FCH_INIT_LATE_CONSTRUCT &FchLateConstructor
#else
#define FP_FCH_INIT_LATE &CommonFchInitStub
#define FP_FCH_INIT_LATE_CONSTRUCT &CommonFchInitStub
#endif
#endif
/* FCH subcomponent build options */
#undef FCH_NO_HWACPI_SUPPORT
#undef FCH_NO_AB_SUPPORT
#undef FCH_NO_SPI_SUPPORT
#undef FCH_NO_GEC_SUPPORT
#undef FCH_NO_SATA_SUPPORT
#undef FCH_NO_IDE_SUPPORT
#undef FCH_NO_LPC_SUPPORT
#undef FCH_NO_PCIB_SUPPORT
#undef FCH_NO_PCIE_SUPPORT
#undef FCH_NO_GPP_SUPPORT
#undef FCH_NO_USB_SUPPORT
#undef FCH_NO_EHCI_SUPPORT
#undef FCH_NO_OHCI_SUPPORT
#undef FCH_NO_XHCI_SUPPORT
#undef FCH_NO_IMC_SUPPORT
#undef FCH_NO_SD_SUPPORT
#undef FCH_NO_IR_SUPPORT
#undef FCH_NO_AZALIA_SUPPORT
#undef FCH_NO_HWM_SUPPORT
// Following are determined by silicon characteristics
#if (OPTION_FAMILY14H_KR == TRUE)
#define FCH_NO_GPP_SUPPORT TRUE
#define FCH_NO_PCIB_SUPPORT TRUE
#define FCH_NO_PCIE_SUPPORT TRUE
#else
#if (OPTION_FAMILY15H_TN == TRUE)
//#define FCH_NO_GEC_SUPPORT TRUE
#else
#error FCH_SUPPORT: No chip type selected.
#endif
#endif
//
// Installable blocks depending on build switches
//
#ifndef FCH_NO_HWACPI_SUPPORT
#define BLOCK_HWACPI_SIZE sizeof (FCH_ACPI)
#define InstallFchInitResetHwAcpiP &FchInitResetHwAcpiP
#define InstallFchInitResetHwAcpi &FchInitResetHwAcpi
#define InstallFchInitEnvHwAcpiP &FchInitEnvHwAcpiP
#define InstallFchInitEnvHwAcpi &FchInitEnvHwAcpi
#define InstallFchInitMidHwAcpi &FchTaskDummy
#define InstallFchInitLateHwAcpi &FchInitLateHwAcpi
#else
#define BLOCK_HWACPI_SIZE 0
#define InstallFchInitResetHwAcpiP &FchTaskDummy
#define InstallFchInitResetHwAcpi &FchTaskDummy
#define InstallFchInitEnvHwAcpi &FchTaskDummy
#define InstallFchInitMidHwAcpi &FchTaskDummy
#define InstallFchInitLateHwAcpi &FchTaskDummy
#endif
#ifndef FCH_NO_AB_SUPPORT
#define BLOCK_AB_SIZE sizeof (FCH_AB)
#define InstallFchInitResetAb &FchInitResetAb
#define InstallFchInitEnvAb &FchInitEnvAb
#define InstallFchInitEnvAbS &FchInitEnvAbSpecial
#define InstallFchInitMidAb &FchInitMidAb
#define InstallFchInitLateAb &FchInitLateAb
#else
#define BLOCK_AB_SIZE 0
#define InstallFchInitResetAb &FchTaskDummy
#define InstallFchInitEnvAb &FchTaskDummy
#define InstallFchInitEnvAbS &FchTaskDummy
#define InstallFchInitMidAb &FchTaskDummy
#define InstallFchInitLateAb &FchTaskDummy
#endif
#ifndef FCH_NO_SPI_SUPPORT
#define BLOCK_SPI_SIZE sizeof (FCH_SPI)
#define InstallFchInitResetSpi &FchInitResetSpi
#define InstallFchInitEnvSpi &FchInitEnvSpi
#define InstallFchInitMidSpi &FchTaskDummy
#define InstallFchInitLateSpi &FchInitLateSpi
#else
#define BLOCK_SPI_SIZE 0
#define InstallFchInitResetSpi &FchTaskDummy
#define InstallFchInitEnvSpi &FchTaskDummy
#define InstallFchInitMidSpi &FchTaskDummy
#define InstallFchInitLateSpi &FchTaskDummy
#endif
#ifndef FCH_NO_GEC_SUPPORT
#define BLOCK_GEC_SIZE sizeof (FCH_GEC)
#define InstallFchInitResetGec &FchInitResetGec
#define InstallFchInitEnvGec &FchInitEnvGec
#define InstallFchInitMidGec &FchInitMidGec
#define InstallFchInitLateGec &FchInitLateGec
#else
#define BLOCK_GEC_SIZE 0
#define InstallFchInitResetGec &FchTaskDummy
#define InstallFchInitEnvGec &FchTaskDummy
#define InstallFchInitMidGec &FchTaskDummy
#define InstallFchInitLateGec &FchTaskDummy
#endif
#ifndef FCH_NO_SATA_SUPPORT
#define BLOCK_SATA_SIZE sizeof (FCH_SATA)
#define InstallFchInitResetSata &FchInitResetSata
#define InstallFchInitEnvSata &FchInitEnvSata
#define InstallFchInitMidSata &FchInitMidSata
#define InstallFchInitLateSata &FchInitLateSata
#else
#define BLOCK_SATA_SIZE 0
#define InstallFchInitResetSata &FchTaskDummy
#define InstallFchInitEnvSata &FchTaskDummy
#define InstallFchInitMidSata &FchTaskDummy
#define InstallFchInitLateSata &FchTaskDummy
#endif
#ifndef FCH_NO_IDE_SUPPORT
#define BLOCK_IDE_SIZE sizeof (FCH_IDE)
#define InstallFchInitResetIde &FchTaskDummy
#define InstallFchInitEnvIde &FchInitEnvIde
#define InstallFchInitMidIde &FchInitMidIde
#define InstallFchInitLateIde &FchInitLateIde
#else
#define BLOCK_IDE_SIZE 0
#define InstallFchInitResetIde &FchTaskDummy
#define InstallFchInitEnvIde &FchTaskDummy
#define InstallFchInitMidIde &FchTaskDummy
#define InstallFchInitLateIde &FchTaskDummy
#endif
#ifndef FCH_NO_LPC_SUPPORT
#define BLOCK_LPC_SIZE sizeof (FCH_LPC)
#define InstallFchInitResetLpc &FchInitResetLpc
#define InstallFchInitEnvLpc &FchTaskDummy
#define InstallFchInitMidLpc &FchTaskDummy
#define InstallFchInitLateLpc &FchTaskDummy
#else
#define BLOCK_LPC_SIZE 0
#define InstallFchInitResetLpc &FchTaskDummy
#define InstallFchInitEnvLpc &FchTaskDummy
#define InstallFchInitMidLpc &FchTaskDummy
#define InstallFchInitLateLpc &FchTaskDummy
#endif
#ifndef FCH_NO_PCIB_SUPPORT
#define BLOCK_PCIB_SIZE sizeof (FCH_PCIB)
#define InstallFchInitResetPcib &FchInitResetPcib
#define InstallFchInitEnvPcib &FchInitEnvPcib
#define InstallFchInitMidPcib &FchTaskDummy
#define InstallFchInitLatePcib &FchInitLatePcib
#else
#define BLOCK_PCIB_SIZE 0
#define InstallFchInitResetPcib &FchTaskDummy
#define InstallFchInitEnvPcib &FchTaskDummy
#define InstallFchInitMidPcib &FchTaskDummy
#define InstallFchInitLatePcib &FchTaskDummy
#endif
#ifndef FCH_NO_PCIE_SUPPORT
#define InstallFchInitResetPcie &FchInitResetPcie
#define InstallFchInitEnvPcie &FchInitEnvPcie
#define InstallFchInitMidPcie &FchTaskDummy
#define InstallFchInitLatePcie &FchInitLatePcie
#else
#define InstallFchInitResetPcie &FchTaskDummy
#define InstallFchInitEnvPcie &FchTaskDummy
#define InstallFchInitMidPcie &FchTaskDummy
#define InstallFchInitLatePcie &FchTaskDummy
#endif
#ifndef FCH_NO_GPP_SUPPORT
#define BLOCK_GPP_SIZE sizeof (FCH_GPP)
#define InstallFchInitResetGpp &FchInitResetGpp
#define InstallFchInitEnvGpp &FchInitEnvGpp
#define InstallFchInitMidGpp &FchTaskDummy
#define InstallFchInitLateGpp &FchInitLateGpp
#else
#define BLOCK_GPP_SIZE 0
#define InstallFchInitResetGpp &FchTaskDummy
#define InstallFchInitEnvGpp &FchTaskDummy
#define InstallFchInitMidGpp &FchTaskDummy
#define InstallFchInitLateGpp &FchTaskDummy
#endif
#ifndef FCH_NO_USB_SUPPORT
#define BLOCK_USB_SIZE sizeof (FCH_USB)
#define InstallFchInitResetUsb &FchInitResetUsb
#define InstallFchInitEnvUsb &FchInitEnvUsb
#define InstallFchInitMidUsb &FchInitMidUsb
#define InstallFchInitLateUsb &FchInitLateUsb
#else
#define BLOCK_USB_SIZE 0
#define InstallFchInitResetUsb &FchTaskDummy
#define InstallFchInitEnvUsb &FchTaskDummy
#define InstallFchInitMidUsb &FchTaskDummy
#define InstallFchInitLateUsb &FchTaskDummy
#endif
#ifndef FCH_NO_EHCI_SUPPORT
#define InstallFchInitResetUsbEhci &FchInitResetEhci
#define InstallFchInitEnvUsbEhci &FchInitEnvUsbEhci
#define InstallFchInitMidUsbEhci &FchInitMidUsbEhci
#define InstallFchInitLateUsbEhci &FchInitLateUsbEhci
#else
#define InstallFchInitResetUsbEhci &FchTaskDummy
#define InstallFchInitEnvUsbEhci &FchTaskDummy
#define InstallFchInitMidUsbEhci &FchTaskDummy
#define InstallFchInitLateUsbEhci &FchTaskDummy
#endif
#ifndef FCH_NO_OHCI_SUPPORT
#define InstallFchInitResetUsbOhci &FchInitResetOhci
#define InstallFchInitEnvUsbOhci &FchInitEnvUsbOhci
#define InstallFchInitMidUsbOhci &FchInitMidUsbOhci
#define InstallFchInitLateUsbOhci &FchInitLateUsbOhci
#else
#define InstallFchInitResetUsbOhci &FchTaskDummy
#define InstallFchInitEnvUsbOhci &FchTaskDummy
#define InstallFchInitMidUsbOhci &FchTaskDummy
#define InstallFchInitLateUsbOhci &FchTaskDummy
#endif
#ifndef FCH_NO_XHCI_SUPPORT
#define InstallFchInitResetUsbXhci &FchInitResetXhci
#define InstallFchInitEnvUsbXhci &FchInitEnvUsbXhci
#define InstallFchInitMidUsbXhci &FchInitMidUsbXhci
#define InstallFchInitLateUsbXhci &FchInitLateUsbXhci
#else
#define InstallFchInitResetUsbXhci &FchTaskDummy
#define InstallFchInitEnvUsbXhci &FchTaskDummy
#define InstallFchInitMidUsbXhci &FchTaskDummy
#define InstallFchInitLateUsbXhci &FchTaskDummy
#endif
#ifndef FCH_NO_IMC_SUPPORT
#define BLOCK_IMC_SIZE sizeof (FCH_IMC)
#define InstallFchInitResetImc &FchInitResetImc
#define InstallFchInitEnvImc &FchInitEnvImc
#define InstallFchInitMidImc &FchInitMidImc
#define InstallFchInitLateImc &FchInitLateImc
#else
#define BLOCK_IMC_SIZE 0
#define InstallFchInitResetImc &FchTaskDummy
#define InstallFchInitEnvImc &FchTaskDummy
#define InstallFchInitMidImc &FchTaskDummy
#define InstallFchInitLateImc &FchTaskDummy
#endif
#ifndef FCH_NO_SD_SUPPORT
#define BLOCK_SD_SIZE sizeof (FCH_SD)
#define InstallFchInitResetSd &FchTaskDummy
#define InstallFchInitEnvSd &FchInitEnvSd
#define InstallFchInitMidSd &FchTaskDummy
#define InstallFchInitLateSd &FchTaskDummy
#else
#define BLOCK_SD_SIZE 0
#define InstallFchInitResetSd &FchTaskDummy
#define InstallFchInitEnvSd &FchTaskDummy
#define InstallFchInitMidSd &FchTaskDummy
#define InstallFchInitLateSd &FchTaskDummy
#endif
#ifndef FCH_NO_IR_SUPPORT
#define BLOCK_IR_SIZE sizeof (FCH_IR)
#define InstallFchInitResetIr &FchTaskDummy
#define InstallFchInitEnvIr &FchInitEnvIr
#define InstallFchInitMidIr &FchTaskDummy
#define InstallFchInitLateIr &FchTaskDummy
#else
#define BLOCK_IR_SIZE 0
#define InstallFchInitResetIr &FchTaskDummy
#define InstallFchInitEnvIr &FchTaskDummy
#define InstallFchInitMidIr &FchTaskDummy
#define InstallFchInitLateIr &FchTaskDummy
#endif
#ifndef FCH_NO_AZALIA_SUPPORT
#define BLOCK_AZALIA_SIZE sizeof (FCH_AZALIA)
#define InstallFchInitResetAzalia &FchTaskDummy
#define InstallFchInitEnvAzalia &FchInitEnvAzalia
#define InstallFchInitMidAzalia &FchInitMidAzalia
#define InstallFchInitLateAzalia &FchInitLateAzalia
#else
#define BLOCK_AZALIA_SIZE 0
#define InstallFchInitResetAzalia &FchTaskDummy
#define InstallFchInitEnvAzalia &FchTaskDummy
#define InstallFchInitMidAzalia &FchTaskDummy
#define InstallFchInitLateAzalia &FchTaskDummy
#endif
#ifndef FCH_NO_HWM_SUPPORT
#define BLOCK_HWM_SIZE sizeof (FCH_HWM)
#define InstallFchInitResetHwm &FchTaskDummy
#define InstallFchInitEnvHwm &FchInitEnvHwm
#define InstallFchInitMidHwm &FchInitMidHwm
#define InstallFchInitLateHwm &FchInitLateHwm
#else
#define InstallFchInitResetHwm &FchTaskDummy
#define InstallFchInitEnvHwm &FchTaskDummy
#define InstallFchInitMidHwm &FchTaskDummy
#define InstallFchInitLateHwm &FchTaskDummy
#endif
#define BLOCK_SMBUS_SIZE sizeof (FCH_SMBUS)
#define BLOCK_HPET_SIZE sizeof (FCH_HPET)
#define BLOCK_GCPU_SIZE sizeof (FCH_GCPU)
#define BLOCK_SDB_SIZE sizeof (FCH_SERIALDB)
#define BLOCK_MISC_SIZE sizeof (FCH_MISC)
// Optionally declare OEM hooks after each phase
#ifndef FCH_INIT_RESET_HOOK
#define InstallFchInitResetHook FchTaskDummy
#else
#define InstallFchInitResetHook OemFchInitResetHook
#endif
//
// Define FCH build time options and configurations
//
#ifdef BLDCFG_SMBUS0_BASE_ADDRESS
#define CFG_SMBUS0_BASE_ADDRESS BLDCFG_SMBUS0_BASE_ADDRESS
#else
#define CFG_SMBUS0_BASE_ADDRESS DFLT_SMBUS0_BASE_ADDRESS
#endif
#ifdef BLDCFG_SMBUS1_BASE_ADDRESS
#define CFG_SMBUS1_BASE_ADDRESS BLDCFG_SMBUS1_BASE_ADDRESS
#else
#define CFG_SMBUS1_BASE_ADDRESS DFLT_SMBUS1_BASE_ADDRESS
#endif
#ifdef BLDCFG_SIO_PME_BASE_ADDRESS
#define CFG_SIO_PME_BASE_ADDRESS BLDCFG_SIO_PME_BASE_ADDRESS
#else
#define CFG_SIO_PME_BASE_ADDRESS DFLT_SIO_PME_BASE_ADDRESS
#endif
#ifdef BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS
#define CFG_ACPI_PM1_EVT_BLOCK_ADDRESS BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS
#else
#define CFG_ACPI_PM1_EVT_BLOCK_ADDRESS DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS
#endif
#ifdef BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS
#define CFG_ACPI_PM1_CNT_BLOCK_ADDRESS BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS
#else
#define CFG_ACPI_PM1_CNT_BLOCK_ADDRESS DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS
#endif
#ifdef BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS
#define CFG_ACPI_PM_TMR_BLOCK_ADDRESS BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS
#else
#define CFG_ACPI_PM_TMR_BLOCK_ADDRESS DFLT_ACPI_PM_TMR_BLOCK_ADDRESS
#endif
#ifdef BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS
#define CFG_ACPI_CPU_CNT_BLOCK_ADDRESS BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS
#else
#define CFG_ACPI_CPU_CNT_BLOCK_ADDRESS DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS
#endif
#ifdef BLDCFG_ACPI_GPE0_BLOCK_ADDRESS
#define CFG_ACPI_GPE0_BLOCK_ADDRESS BLDCFG_ACPI_GPE0_BLOCK_ADDRESS
#else
#define CFG_ACPI_GPE0_BLOCK_ADDRESS DFLT_ACPI_GPE0_BLOCK_ADDRESS
#endif
#ifdef BLDCFG_WATCHDOG_TIMER_BASE
#define CFG_WATCHDOG_TIMER_BASE BLDCFG_WATCHDOG_TIMER_BASE
#else
#define CFG_WATCHDOG_TIMER_BASE DFLT_WATCHDOG_TIMER_BASE_ADDRESS
#endif
#ifdef BLDCFG_ACPI_PMA_BLK_ADDRESS
#define CFG_ACPI_PMA_CNTBLK_ADDRESS BLDCFG_ACPI_PMA_BLK_ADDRESS
#else
#define CFG_ACPI_PMA_CNTBLK_ADDRESS DFLT_ACPI_PMA_CNT_BLK_ADDRESS
#endif
#ifdef BLDCFG_SMI_CMD_PORT_ADDRESS
#define CFG_SMI_CMD_PORT_ADDRESS BLDCFG_SMI_CMD_PORT_ADDRESS
#else
#define CFG_SMI_CMD_PORT_ADDRESS DFLT_SMI_CMD_PORT
#endif
#ifdef BLDCFG_ROM_BASE_ADDRESS
#define CFG_SPI_ROM_BASE_ADDRESS BLDCFG_ROM_BASE_ADDRESS
#else
#define CFG_SPI_ROM_BASE_ADDRESS DFLT_SPI_BASE_ADDRESS
#endif
#ifdef BLDCFG_GEC_SHADOW_ROM_BASE
#define CFG_GEC_SHADOW_ROM_BASE BLDCFG_GEC_SHADOW_ROM_BASE
#else
#define CFG_GEC_SHADOW_ROM_BASE DFLT_GEC_BASE_ADDRESS
#endif
#ifdef BLDCFG_HPET_BASE_ADDRESS
#define CFG_HPET_BASE_ADDRESS BLDCFG_HPET_BASE_ADDRESS
#else
#define CFG_HPET_BASE_ADDRESS DFLT_HPET_BASE_ADDRESS
#endif
#ifdef BLDCFG_AZALIA_SSID
#define CFG_AZALIA_SSID BLDCFG_AZALIA_SSID
#else
#define CFG_AZALIA_SSID DFLT_AZALIA_SSID
#endif
#ifdef BLDCFG_SMBUS_SSID
#define CFG_SMBUS_SSID BLDCFG_SMBUS_SSID
#else
#define CFG_SMBUS_SSID DFLT_SMBUS_SSID
#endif
#ifdef BLDCFG_IDE_SSID
#define CFG_IDE_SSID BLDCFG_IDE_SSID
#else
#define CFG_IDE_SSID DFLT_IDE_SSID
#endif
#ifdef BLDCFG_SATA_AHCI_SSID
#define CFG_SATA_AHCI_SSID BLDCFG_SATA_AHCI_SSID
#else
#define CFG_SATA_AHCI_SSID DFLT_SATA_AHCI_SSID
#endif
#ifdef BLDCFG_SATA_IDE_SSID
#define CFG_SATA_IDE_SSID BLDCFG_SATA_IDE_SSID
#else
#define CFG_SATA_IDE_SSID DFLT_SATA_IDE_SSID
#endif
#ifdef BLDCFG_SATA_RAID5_SSID
#define CFG_SATA_RAID5_SSID BLDCFG_SATA_RAID5_SSID
#else
#define CFG_SATA_RAID5_SSID DFLT_SATA_RAID5_SSID
#endif
#ifdef BLDCFG_SATA_RAID_SSID
#define CFG_SATA_RAID_SSID BLDCFG_SATA_RAID_SSID
#else
#define CFG_SATA_RAID_SSID DFLT_SATA_RAID_SSID
#endif
#ifdef BLDCFG_EHCI_SSID
#define CFG_EHCI_SSID BLDCFG_EHCI_SSID
#else
#define CFG_EHCI_SSID DFLT_EHCI_SSID
#endif
#ifdef BLDCFG_OHCI_SSID
#define CFG_OHCI_SSID BLDCFG_OHCI_SSID
#else
#define CFG_OHCI_SSID DFLT_OHCI_SSID
#endif
#ifdef BLDCFG_LPC_SSID
#define CFG_LPC_SSID BLDCFG_LPC_SSID
#else
#define CFG_LPC_SSID DFLT_LPC_SSID
#endif
#ifdef BLDCFG_FCH_GPP_LINK_CONFIG
#define CFG_FCH_GPP_LINK_CONFIG BLDCFG_FCH_GPP_LINK_CONFIG
#else
#define CFG_FCH_GPP_LINK_CONFIG DFLT_FCH_GPP_LINK_CONFIG
#endif
#ifdef BLDCFG_FCH_GPP_PORT0_PRESENT
#define CFG_FCH_GPP_PORT0_PRESENT BLDCFG_FCH_GPP_PORT0_PRESENT
#else
#define CFG_FCH_GPP_PORT0_PRESENT DFLT_FCH_GPP_PORT0_PRESENT
#endif
#ifdef BLDCFG_FCH_GPP_PORT1_PRESENT
#define CFG_FCH_GPP_PORT1_PRESENT BLDCFG_FCH_GPP_PORT1_PRESENT
#else
#define CFG_FCH_GPP_PORT1_PRESENT DFLT_FCH_GPP_PORT1_PRESENT
#endif
#ifdef BLDCFG_FCH_GPP_PORT2_PRESENT
#define CFG_FCH_GPP_PORT2_PRESENT BLDCFG_FCH_GPP_PORT2_PRESENT
#else
#define CFG_FCH_GPP_PORT2_PRESENT DFLT_FCH_GPP_PORT2_PRESENT
#endif
#ifdef BLDCFG_FCH_GPP_PORT3_PRESENT
#define CFG_FCH_GPP_PORT3_PRESENT BLDCFG_FCH_GPP_PORT3_PRESENT
#else
#define CFG_FCH_GPP_PORT3_PRESENT DFLT_FCH_GPP_PORT3_PRESENT
#endif
#ifdef BLDCFG_FCH_GPP_PORT0_HOTPLUG
#define CFG_FCH_GPP_PORT0_HOTPLUG BLDCFG_FCH_GPP_PORT0_HOTPLUG
#else
#define CFG_FCH_GPP_PORT0_HOTPLUG DFLT_FCH_GPP_PORT0_HOTPLUG
#endif
#ifdef BLDCFG_FCH_GPP_PORT1_HOTPLUG
#define CFG_FCH_GPP_PORT1_HOTPLUG BLDCFG_FCH_GPP_PORT1_HOTPLUG
#else
#define CFG_FCH_GPP_PORT1_HOTPLUG DFLT_FCH_GPP_PORT1_HOTPLUG
#endif
#ifdef BLDCFG_FCH_GPP_PORT2_HOTPLUG
#define CFG_FCH_GPP_PORT2_HOTPLUG BLDCFG_FCH_GPP_PORT2_HOTPLUG
#else
#define CFG_FCH_GPP_PORT2_HOTPLUG DFLT_FCH_GPP_PORT2_HOTPLUG
#endif
#ifdef BLDCFG_FCH_GPP_PORT3_HOTPLUG
#define CFG_FCH_GPP_PORT3_HOTPLUG BLDCFG_FCH_GPP_PORT3_HOTPLUG
#else
#define CFG_FCH_GPP_PORT3_HOTPLUG DFLT_FCH_GPP_PORT3_HOTPLUG
#endif
#ifdef AGESA_ENTRY_INIT_RESET
#if AGESA_ENTRY_INIT_RESET == TRUE
//
// Define task list for InitReset phase
//
FCH_TASK_ENTRY ROMDATA *FchInitResetTaskTable[] = {
InstallFchInitResetHwAcpiP,
InstallFchInitResetAb,
InstallFchInitResetSpi,
InstallFchInitResetGec,
InstallFchInitResetHwAcpi,
InstallFchInitResetSata,
InstallFchInitResetLpc,
InstallFchInitResetPcib,
InstallFchInitResetPcie,
InstallFchInitResetGpp,
InstallFchInitResetUsb,
InstallFchInitResetUsbEhci,
InstallFchInitResetUsbOhci,
InstallFchInitResetUsbXhci,
InstallFchInitResetImc,
NULL
};
#endif
#endif
#ifdef AGESA_ENTRY_INIT_ENV
#if AGESA_ENTRY_INIT_ENV == TRUE
//
// Define task list for InitEnv phase
//
FCH_TASK_ENTRY ROMDATA *FchInitEnvTaskTable[] = {
InstallFchInitEnvHwAcpiP,
InstallFchInitEnvPcib,
InstallFchInitEnvPcie,
InstallFchInitEnvIr,
InstallFchInitEnvHwAcpi,
InstallFchInitEnvSpi,
InstallFchInitEnvSd,
InstallFchInitEnvImc,
InstallFchInitEnvUsb,
InstallFchInitEnvUsbEhci,
InstallFchInitEnvUsbOhci,
InstallFchInitEnvUsbXhci,
InstallFchInitEnvSata,
InstallFchInitEnvIde,
InstallFchInitEnvGec,
InstallFchInitEnvAzalia,
InstallFchInitEnvAb,
InstallFchInitEnvGpp,
InstallFchInitEnvAbS,
InstallFchInitEnvHwm,
NULL
};
#endif
#endif
#ifdef AGESA_ENTRY_INIT_MID
#if AGESA_ENTRY_INIT_MID == TRUE
//
// Define task list for InitMid phase
//
FCH_TASK_ENTRY ROMDATA *FchInitMidTaskTable[] = {
InstallFchInitMidImc,
InstallFchInitMidUsb,
InstallFchInitMidUsbEhci,
InstallFchInitMidUsbOhci,
InstallFchInitMidUsbXhci,
InstallFchInitMidSata,
InstallFchInitMidIde,
InstallFchInitMidGec,
InstallFchInitMidAzalia,
InstallFchInitMidHwm,
NULL
};
#endif
#endif
#ifdef AGESA_ENTRY_INIT_LATE
#if AGESA_ENTRY_INIT_LATE == TRUE
//
// Define task list for InitLate phase
//
FCH_TASK_ENTRY ROMDATA *FchInitLateTaskTable[] = {
InstallFchInitLatePcie,
InstallFchInitLatePcib,
InstallFchInitLateSpi,
InstallFchInitLateUsb,
InstallFchInitLateUsbEhci,
InstallFchInitLateUsbOhci,
InstallFchInitLateUsbXhci,
InstallFchInitLateSata,
InstallFchInitLateIde,
InstallFchInitLateGec,
InstallFchInitLateAzalia,
InstallFchInitLateImc,
InstallFchInitLateHwm,
InstallFchInitLateGpp,
InstallFchInitLateHwAcpi,
NULL
};
#endif
#endif
#ifdef AGESA_ENTRY_INIT_ENV
#if AGESA_ENTRY_INIT_ENV == TRUE
//
// Define task list for S3 resume before PCI phase
//
FCH_TASK_ENTRY ROMDATA *FchInitS3EarlyTaskTable[] = {
InstallFchInitEnvPcie,
InstallFchInitEnvPcib,
InstallFchInitEnvIr,
InstallFchInitEnvHwAcpi,
InstallFchInitEnvSpi,
InstallFchInitEnvSd,
InstallFchInitEnvUsb,
InstallFchInitEnvSata,
InstallFchInitEnvIde,
InstallFchInitEnvGec,
InstallFchInitEnvAzalia,
InstallFchInitEnvAb,
InstallFchInitEnvGpp,
InstallFchInitEnvAbS,
NULL
};
#endif
#endif
#ifdef AGESA_ENTRY_INIT_LATE
#if AGESA_ENTRY_INIT_LATE == TRUE
//
// Define task list for S3 resume after PCI phase
//
FCH_TASK_ENTRY ROMDATA *FchInitS3LateTaskTable[] = {
InstallFchInitLatePcie,
InstallFchInitLatePcib,
InstallFchInitLateSpi,
InstallFchInitLateUsb,
InstallFchInitLateUsbEhci,
InstallFchInitLateUsbOhci,
InstallFchInitLateUsbXhci,
InstallFchInitMidSata,
InstallFchInitMidIde,
InstallFchInitMidGec,
InstallFchInitMidAzalia,
InstallFchInitLateSata,
InstallFchInitLateIde,
InstallFchInitLateHwAcpi,
InstallFchInitEnvHwm,
InstallFchInitLateHwm,
NULL
};
#endif
#endif
#else // FCH_SUPPORT == FALSE
/* FCH Interface entries */
extern FCH_INIT CommonFchInitStub;
#define FP_FCH_INIT_RESET &CommonFchInitStub
#define FP_FCH_INIT_RESET_CONSTRUCT &CommonFchInitStub
#define FP_FCH_INIT_ENV &CommonFchInitStub
#define FP_FCH_INIT_ENV_CONSTRUCT &CommonFchInitStub
#define FP_FCH_INIT_MID &CommonFchInitStub
#define FP_FCH_INIT_MID_CONSTRUCT &CommonFchInitStub
#define FP_FCH_INIT_LATE &CommonFchInitStub
#define FP_FCH_INIT_LATE_CONSTRUCT &CommonFchInitStub
#define CFG_SMBUS0_BASE_ADDRESS 0
#define CFG_SMBUS1_BASE_ADDRESS 0
#define CFG_SIO_PME_BASE_ADDRESS 0
#define CFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0
#define CFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0
#define CFG_ACPI_PM_TMR_BLOCK_ADDRESS 0
#define CFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0
#define CFG_ACPI_GPE0_BLOCK_ADDRESS 0
#define CFG_SPI_ROM_BASE_ADDRESS 0
#define CFG_WATCHDOG_TIMER_BASE 0
#define CFG_HPET_BASE_ADDRESS 0
#define CFG_SMI_CMD_PORT_ADDRESS 0
#define CFG_ACPI_PMA_CNTBLK_ADDRESS 0
#define CFG_GEC_SHADOW_ROM_BASE 0
#define CFG_AZALIA_SSID 0
#define CFG_SMBUS_SSID 0
#define CFG_IDE_SSID 0
#define CFG_SATA_AHCI_SSID 0
#define CFG_SATA_IDE_SSID 0
#define CFG_SATA_RAID5_SSID 0
#define CFG_SATA_RAID_SSID 0
#define CFG_EHCI_SSID 0
#define CFG_OHCI_SSID 0
#define CFG_LPC_SSID 0
#define CFG_FCH_GPP_LINK_CONFIG 0
#define CFG_FCH_GPP_PORT0_PRESENT 0
#define CFG_FCH_GPP_PORT1_PRESENT 0
#define CFG_FCH_GPP_PORT2_PRESENT 0
#define CFG_FCH_GPP_PORT3_PRESENT 0
#define CFG_FCH_GPP_PORT0_HOTPLUG 0
#define CFG_FCH_GPP_PORT1_HOTPLUG 0
#define CFG_FCH_GPP_PORT2_HOTPLUG 0
#define CFG_FCH_GPP_PORT3_HOTPLUG 0
#endif
CONST BLDOPT_FCH_FUNCTION ROMDATA BldoptFchFunction = {
FP_FCH_INIT_RESET,
FP_FCH_INIT_RESET_CONSTRUCT,
FP_FCH_INIT_ENV,
FP_FCH_INIT_ENV_CONSTRUCT,
FP_FCH_INIT_MID,
FP_FCH_INIT_MID_CONSTRUCT,
FP_FCH_INIT_LATE,
FP_FCH_INIT_LATE_CONSTRUCT,
};
#endif // _OPTION_FCH_INSTALL_H_

53
src/vendorcode/amd/agesa/f12/Config/OptionGfxRecoveryInstall.h
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@ -1,53 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: GfxRecovery
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_GFX_RECOVERY_INSTALL_H_
#define _OPTION_GFX_RECOVERY_INSTALL_H_
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#endif // _OPTION_GFX_RECOVERY_INSTALL_H_

592
src/vendorcode/amd/agesa/f12/Config/OptionGnbInstall.h
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@ -1,592 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: GNB
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 49877 $ @e \$Date: 2011-03-30 13:15:18 +0800 (Wed, 30 Mar 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_GNB_INSTALL_H_
#define _OPTION_GNB_INSTALL_H_
#include "S3SaveState.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
//---------------------------------------------------------------------------------------------------
// Family installation
//---------------------------------------------------------------------------------------------------
#define GNB_TYPE_KR FALSE
#define GNB_TYPE_TN FALSE
#define GNB_TYPE_LN FALSE
#define GNB_TYPE_ON FALSE
#if (OPTION_FAMILY14H_ON == TRUE)
#undef GNB_TYPE_ON
#define GNB_TYPE_ON TRUE
#endif
#if (OPTION_FAMILY12H_LN == TRUE)
#undef GNB_TYPE_LN
#define GNB_TYPE_LN TRUE
#endif
#if (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
//---------------------------------------------------------------------------------------------------
// Service installation
//---------------------------------------------------------------------------------------------------
#include "Gnb.h"
#include "GnbPcie.h"
#define SERVICES_POINTER NULL
GNB_SERVICE *ServiceTable = SERVICES_POINTER;
//---------------------------------------------------------------------------------------------------
// BUILD options
//---------------------------------------------------------------------------------------------------
#ifndef CFG_IGFX_AS_PCIE_EP
#define CFG_IGFX_AS_PCIE_EP TRUE
#endif
#ifndef CFG_LCLK_DEEP_SLEEP_EN
#define CFG_LCLK_DEEP_SLEEP_EN TRUE
#endif
#ifndef CFG_LCLK_DPM_EN
#define CFG_LCLK_DPM_EN TRUE
#endif
#ifndef CFG_GMC_POWER_GATE_STUTTER_ONLY
#define CFG_GMC_POWER_GATE_STUTTER_ONLY FALSE
#endif
#ifndef CFG_SMU_SCLK_CLOCK_GATING_ENABLE
#if (GNB_TYPE_ON == TRUE)
#define CFG_SMU_SCLK_CLOCK_GATING_ENABLE TRUE
#else
#define CFG_SMU_SCLK_CLOCK_GATING_ENABLE FALSE
#endif
#endif
#ifndef CFG_PCIE_ASPM_BLACK_LIST_ENABLE
#define CFG_PCIE_ASPM_BLACK_LIST_ENABLE TRUE
#endif
#ifndef CFG_GNB_IVRS_RELATIVE_ADDR_NAMES_SUPPORT
#define CFG_GNB_IVRS_RELATIVE_ADDR_NAMES_SUPPORT FALSE
#endif
#ifndef CFG_GNB_LOAD_REAL_FUSE
#define CFG_GNB_LOAD_REAL_FUSE TRUE
#endif
#ifndef CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING
#define CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING (60 * 1000)
#endif
#ifndef CFG_GNB_PCIE_LINK_L0_POOLING
#define CFG_GNB_PCIE_LINK_L0_POOLING (60 * 1000)
#endif
#ifndef CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME
#define CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME (2 * 1000)
#endif
#ifndef CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME
#define CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME (2 * 1000)
#endif
#ifdef BLDCFG_PCIE_TRAINING_ALGORITHM
#define CFG_GNB_PCIE_TRAINING_ALGORITHM BLDCFG_PCIE_TRAINING_ALGORITHM
#else
#define CFG_GNB_PCIE_TRAINING_ALGORITHM PcieTrainingStandard
#endif
#ifndef CFG_GNB_FORCE_CABLESAFE_OFF
#define CFG_GNB_FORCE_CABLESAFE_OFF FALSE
#endif
#ifndef CFG_ORB_CLOCK_GATING_ENABLE
#define CFG_ORB_CLOCK_GATING_ENABLE TRUE
#endif
#ifndef CFG_GNB_PCIE_POWERGATING_FLAGS
#define CFG_GNB_PCIE_POWERGATING_FLAGS 0x0
#endif
#ifndef CFG_IOC_LCLK_CLOCK_GATING_ENABLE
#define CFG_IOC_LCLK_CLOCK_GATING_ENABLE FALSE
#endif
#ifndef CFG_IOC_SCLK_CLOCK_GATING_ENABLE
#define CFG_IOC_SCLK_CLOCK_GATING_ENABLE FALSE
#endif
#ifndef CFG_IOMMU_L1_CLOCK_GATING_ENABLE
#define CFG_IOMMU_L1_CLOCK_GATING_ENABLE FALSE
#endif
#ifndef CFG_IOMMU_L2_CLOCK_GATING_ENABLE
#define CFG_IOMMU_L2_CLOCK_GATING_ENABLE FALSE
#endif
#ifndef CFG_GNB_ALTVDDNB_SUPPORT
#define CFG_GNB_ALTVDDNB_SUPPORT TRUE
#endif
GNB_BUILD_OPTIONS ROMDATA GnbBuildOptions = {
CFG_IGFX_AS_PCIE_EP,
CFG_LCLK_DEEP_SLEEP_EN,
CFG_LCLK_DPM_EN,
CFG_GMC_POWER_GATE_STUTTER_ONLY,
CFG_SMU_SCLK_CLOCK_GATING_ENABLE,
CFG_PCIE_ASPM_BLACK_LIST_ENABLE,
CFG_GNB_IVRS_RELATIVE_ADDR_NAMES_SUPPORT,
CFG_GNB_LOAD_REAL_FUSE,
CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING,
CFG_GNB_PCIE_LINK_L0_POOLING,
CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME,
CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME,
CFG_GNB_PCIE_TRAINING_ALGORITHM,
CFG_GNB_FORCE_CABLESAFE_OFF,
CFG_ORB_CLOCK_GATING_ENABLE,
CFG_GNB_PCIE_POWERGATING_FLAGS,
CFG_IOC_LCLK_CLOCK_GATING_ENABLE,
CFG_IOC_SCLK_CLOCK_GATING_ENABLE,
CFG_IOMMU_L1_CLOCK_GATING_ENABLE,
CFG_IOMMU_L2_CLOCK_GATING_ENABLE,
CFG_GNB_ALTVDDNB_SUPPORT
};
//---------------------------------------------------------------------------------------------------
// Module entries
//---------------------------------------------------------------------------------------------------
#if (AGESA_ENTRY_INIT_EARLY == TRUE)
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_NB_EARLY_INIT
#define OPTION_NB_EARLY_INIT TRUE
#endif
#if (OPTION_NB_EARLY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE NbInitAtEarly;
#define OPTION_NBINITATEARLY_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtEarly},
#else
#define OPTION_NBINITATEARLY_ENTRY
#endif
#define OPTION_GNBEARLYINTERFACETN_ENTRY
//---------------------------------------------------------------------------------------------------
// SMU init
#ifndef OPTION_SMU
#define OPTION_SMU TRUE
#endif
#if (OPTION_SMU == TRUE) && (GNB_TYPE_LN == TRUE)
OPTION_GNB_FEATURE F12NbSmuInitFeature;
#define OPTION_F12NBSMUINITFEATURE_ENTRY {AMD_FAMILY_LN, F12NbSmuInitFeature},
#else
#define OPTION_F12NBSMUINITFEATURE_ENTRY
#endif
#if (OPTION_SMU == TRUE) && (GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE F14NbSmuInitFeature;
#define OPTION_F14NBSMUINITFEATURE_ENTRY {AMD_FAMILY_ON, F14NbSmuInitFeature},
#else
#define OPTION_F14NBSMUINITFEATURE_ENTRY
#endif
#define OPTION_KRNBSMUINITFEATURE_ENTRY
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_PCIE_CONFIG_INIT
#define OPTION_PCIE_CONFIG_INIT TRUE
#endif
#if (OPTION_PCIE_CONFIG_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE PcieConfigurationInit;
#define OPTION_PCIECONFIGURATIONINIT_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieConfigurationInit},
#else
#define OPTION_PCIECONFIGURATIONINIT_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_PCIE_EARLY_INIT
#define OPTION_PCIE_EARLY_INIT TRUE
#endif
#if (OPTION_PCIE_EARLY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE PcieInitAtEarly;
#define OPTION_PCIEINITATEARLY_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtEarly},
#else
#define OPTION_PCIEINITATEARLY_ENTRY
#endif
#define OPTION_PCIEEARLYINTERFACETN_ENTRY
//---------------------------------------------------------------------------------------------------
OPTION_GNB_CONFIGURATION GnbEarlyFeatureTable[] = {
OPTION_NBINITATEARLY_ENTRY
OPTION_GNBEARLYINTERFACETN_ENTRY
OPTION_F12NBSMUINITFEATURE_ENTRY
OPTION_F14NBSMUINITFEATURE_ENTRY
OPTION_KRNBSMUINITFEATURE_ENTRY
OPTION_PCIECONFIGURATIONINIT_ENTRY
OPTION_PCIEINITATEARLY_ENTRY
OPTION_PCIEEARLYINTERFACETN_ENTRY
{0, NULL}
};
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_NB_EARLIER_INIT
#define OPTION_NB_EARLIER_INIT TRUE
#endif
#define OPTION_GNBEARLIERINTERFACETN_ENTRY
OPTION_GNB_CONFIGURATION GnbEarlierFeatureTable[] = {
OPTION_GNBEARLIERINTERFACETN_ENTRY
{0, NULL}
};
#endif
#if (AGESA_ENTRY_INIT_POST == TRUE)
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_GFX_CONFIG_POST_INIT
#define OPTION_GFX_CONFIG_POST_INIT TRUE
#endif
#if (OPTION_GFX_CONFIG_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE GfxConfigPostInterface;
#define OPTION_GFXCONFIGPOSTINTERFACE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxConfigPostInterface},
#else
#define OPTION_GFXCONFIGPOSTINTERFACE_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_GFX_POST_INIT
#define OPTION_GFX_POST_INIT TRUE
#endif
#if (OPTION_GFX_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE GfxInitAtPost;
#define OPTION_GFXINITATPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxInitAtPost},
#else
#define OPTION_GFXINITATPOST_ENTRY
#endif
#define OPTION_GFXPOSTINTERFACETN_ENTRY
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_NB_POST_INIT
#define OPTION_NB_POST_INIT TRUE
#endif
#if (OPTION_NB_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE NbInitAtPost;
#define OPTION_NBINITATPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtPost},
#else
#define OPTION_NBINITATPOST_ENTRY
#endif
#define OPTION_GNBPOSTINTERFACETN_ENTRY
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_PCIE_POST_EALRY_INIT
#define OPTION_PCIE_POST_EALRY_INIT TRUE
#endif
#if (OPTION_PCIE_POST_EALRY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE PcieInitAtPostEarly;
#define OPTION_PCIEINITATPOSTEARLY_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtPostEarly},
#else
#define OPTION_PCIEINITATPOSTEARLY_ENTRY
#endif
#define OPTION_PCIEPOSTEARLYINTERFACETN_ENTRY
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_PCIE_POST_INIT
#define OPTION_PCIE_POST_INIT TRUE
#endif
#if (OPTION_PCIE_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE PcieInitAtPost;
#define OPTION_PCIEINITATPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtPost},
#else
#define OPTION_PCIEINITATPOST_ENTRY
#endif
#define OPTION_PCIEPOSTINTERFACETN_ENTRY
//---------------------------------------------------------------------------------------------------
OPTION_GNB_CONFIGURATION GnbPostFeatureTable[] = {
OPTION_PCIEINITATPOSTEARLY_ENTRY
OPTION_PCIEPOSTEARLYINTERFACETN_ENTRY
OPTION_GFXCONFIGPOSTINTERFACE_ENTRY
OPTION_GFXINITATPOST_ENTRY
OPTION_GFXPOSTINTERFACETN_ENTRY
{0, NULL}
};
OPTION_GNB_CONFIGURATION GnbPostAfterDramFeatureTable[] = {
OPTION_NBINITATPOST_ENTRY
OPTION_GNBPOSTINTERFACETN_ENTRY
OPTION_PCIEINITATPOST_ENTRY
OPTION_PCIEPOSTINTERFACETN_ENTRY
{0, NULL}
};
#endif
#if (AGESA_ENTRY_INIT_ENV == TRUE)
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_FUSE_TABLE_INIT
#define OPTION_FUSE_TABLE_INIT TRUE
#endif
#if (OPTION_FUSE_TABLE_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE NbFuseTableFeature;
#define OPTION_NBFUSETABLEFEATURE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbFuseTableFeature},
#else
#define OPTION_NBFUSETABLEFEATURE_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_NB_ENV_INIT
#define OPTION_NB_ENV_INIT TRUE
#endif
#if (OPTION_NB_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE NbInitAtEnv;
#define OPTION_NBINITATENVT_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtEnv},
#else
#define OPTION_NBINITATENVT_ENTRY
#endif
#define OPTION_GNBENVINTERFACETN_ENTRY
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_GFX_CONFIG_ENV_INIT
#define OPTION_GFX_CONFIG_ENV_INIT TRUE
#endif
#if (OPTION_GFX_CONFIG_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE GfxConfigEnvInterface;
#define OPTION_GFXCONFIGENVINTERFACE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxConfigEnvInterface},
#else
#define OPTION_GFXCONFIGENVINTERFACE_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_GFX_ENV_INIT
#define OPTION_GFX_ENV_INIT TRUE
#endif
#if (OPTION_GFX_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE GfxInitAtEnvPost;
#define OPTION_GFXINITATENVPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxInitAtEnvPost},
#else
#define OPTION_GFXINITATENVPOST_ENTRY
#endif
#define OPTION_GFXENVINTERFACETN_ENTRY
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_POWER_GATE
#define OPTION_POWER_GATE TRUE
#endif
#if (OPTION_POWER_GATE == TRUE) && (GNB_TYPE_LN == TRUE)
OPTION_GNB_FEATURE F12NbPowerGateFeature;
#define OPTION_F12NBPOWERGATEFEATURE_ENTRY {AMD_FAMILY_LN, F12NbPowerGateFeature},
#else
#define OPTION_F12NBPOWERGATEFEATURE_ENTRY
#endif
#if (OPTION_POWER_GATE == TRUE) && (GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE F14NbPowerGateFeature;
#define OPTION_F14NBPOWERGATEFEATURE_ENTRY {AMD_FAMILY_ON, F14NbPowerGateFeature},
#else
#define OPTION_F14NBPOWERGATEFEATURE_ENTRY
#endif
#define OPTION_KRNBPOWERGATEFEATURE_ENTRY
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_PCIE_ENV_INIT
#define OPTION_PCIE_ENV_INIT TRUE
#endif
#if (OPTION_PCIE_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE PcieInitAtEnv;
#define OPTION_PCIEINITATENV_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtEnv},
#else
#define OPTION_PCIEINITATENV_ENTRY
#endif
#define OPTION_PCIEENVINTERFACETN_ENTRY
//---------------------------------------------------------------------------------------------------
OPTION_GNB_CONFIGURATION GnbEnvFeatureTable[] = {
OPTION_NBFUSETABLEFEATURE_ENTRY
OPTION_NBINITATENVT_ENTRY
OPTION_GNBENVINTERFACETN_ENTRY
OPTION_PCIEINITATENV_ENTRY
OPTION_PCIEENVINTERFACETN_ENTRY
OPTION_GFXCONFIGENVINTERFACE_ENTRY
OPTION_GFXINITATENVPOST_ENTRY
OPTION_GFXENVINTERFACETN_ENTRY
OPTION_F12NBPOWERGATEFEATURE_ENTRY
OPTION_F14NBPOWERGATEFEATURE_ENTRY
OPTION_KRNBPOWERGATEFEATURE_ENTRY
{0, NULL}
};
#endif
#if (AGESA_ENTRY_INIT_MID == TRUE)
//---------------------------------------------------------------------------------------------------
#ifndef OPTOIN_GNB_CABLESAFE
#define OPTOIN_GNB_CABLESAFE TRUE
#endif
#if (OPTOIN_GNB_CABLESAFE == TRUE) && (GNB_TYPE_LN == TRUE)
OPTION_GNB_FEATURE GnbCableSafeEntry;
#define OPTION_GNBCABLESAFEENTRY_ENTRY {AMD_FAMILY_LN, GnbCableSafeEntry},
#else
#define OPTION_GNBCABLESAFEENTRY_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTOIN_NB_LCLK_NCLK_RATIO
#define OPTOIN_NB_LCLK_NCLK_RATIO TRUE
#endif
#if (OPTOIN_NB_LCLK_NCLK_RATIO == TRUE) && (GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE F14NbLclkNclkRatioFeature;
#define OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY {AMD_FAMILY_ON, F14NbLclkNclkRatioFeature},
#else
#define OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY
#endif
#define OPTION_KRNBLCLKNCLKRATIOFEATURE_ENTRY
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_NB_LCLK_DPM_INIT
#define OPTION_NB_LCLK_DPM_INIT TRUE
#endif
#if (OPTION_NB_LCLK_DPM_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE NbLclkDpmFeature;
#define OPTION_NBLCLKDPMFEATURE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbLclkDpmFeature},
#else
#define OPTION_NBLCLKDPMFEATURE_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_PCIE_POWER_GATE
#define OPTION_PCIE_POWER_GATE TRUE
#endif
#if (OPTION_PCIE_POWER_GATE == TRUE) && (GNB_TYPE_LN == TRUE)
OPTION_GNB_FEATURE PciePowerGateFeature;
#define OPTION_PCIEPOWERGATEFEATURE_ENTRY {AMD_FAMILY_LN, PciePowerGateFeature},
#else
#define OPTION_PCIEPOWERGATEFEATURE_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_GFX_MID_INIT
#define OPTION_GFX_MID_INIT TRUE
#endif
#if (OPTION_GFX_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE GfxInitAtMidPost;
#define OPTION_GFXINITATMIDPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxInitAtMidPost},
#else
#define OPTION_GFXINITATMIDPOST_ENTRY
#endif
#define OPTION_GFXMIDINTERFACETN_ENTRY
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_GFX_INTEGRATED_TABLE_INIT
#define OPTION_GFX_INTEGRATED_TABLE_INIT TRUE
#endif
#if (OPTION_GFX_INTEGRATED_TABLE_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE GfxIntegratedInfoTableEntry;
#define OPTION_GFXINTEGRATEDINFOTABLE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxIntegratedInfoTableEntry},
#else
#define OPTION_GFXINTEGRATEDINFOTABLE_ENTRY
#endif
#define OPTION_GFXINTINFOTABLEINTERFACETN_ENTRY
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_PCIe_MID_INIT
#define OPTION_PCIe_MID_INIT TRUE
#endif
#if (OPTION_PCIe_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE PcieInitAtMid;
#define OPTION_PCIEINITATMID_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtMid},
#else
#define OPTION_PCIEINITATMID_ENTRY
#endif
#define OPTION_PCIEMIDINTERFACETN_ENTRY
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_NB_MID_INIT
#define OPTION_NB_MID_INIT TRUE
#endif
#if (OPTION_NB_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE NbInitAtLatePost;
#define OPTION_NBINITATLATEPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtLatePost},
#else
#define OPTION_NBINITATLATEPOST_ENTRY
#endif
#define OPTION_GNBMIDINTERFACETN_ENTRY
//---------------------------------------------------------------------------------------------------
OPTION_GNB_CONFIGURATION GnbMidFeatureTable[] = {
OPTION_GFXINITATMIDPOST_ENTRY
OPTION_GFXMIDINTERFACETN_ENTRY
OPTION_GFXINTEGRATEDINFOTABLE_ENTRY
OPTION_GFXINTINFOTABLEINTERFACETN_ENTRY
OPTION_GNBCABLESAFEENTRY_ENTRY
OPTION_PCIEINITATMID_ENTRY
OPTION_PCIEMIDINTERFACETN_ENTRY
OPTION_NBINITATLATEPOST_ENTRY
OPTION_GNBMIDINTERFACETN_ENTRY
OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY
OPTION_KRNBLCLKNCLKRATIOFEATURE_ENTRY
OPTION_NBLCLKDPMFEATURE_ENTRY
OPTION_PCIEPOWERGATEFEATURE_ENTRY
{0, NULL}
};
#endif
#if (AGESA_ENTRY_INIT_LATE == TRUE)
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_ALIB
#define OPTION_ALIB FALSE
#endif
#if (OPTION_ALIB == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE PcieAlibFeature;
#define OPTION_PCIEALIBFEATURE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieAlibFeature},
#else
#define OPTION_PCIEALIBFEATURE_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_IOMMU_ACPI_IVRS
#define OPTION_IOMMU_ACPI_IVRS TRUE
#endif
#define OPTIONIOMMUACPIIVRSLATE_ENTRY
//---------------------------------------------------------------------------------------------------
OPTION_GNB_CONFIGURATION GnbLateFeatureTable[] = {
OPTION_PCIEALIBFEATURE_ENTRY
OPTIONIOMMUACPIIVRSLATE_ENTRY
{0, NULL}
};
#endif
#if (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
S3_DISPATCH_FUNCTION NbSmuServiceRequestS3Script;
S3_DISPATCH_FUNCTION PcieLateRestoreS3Script;
S3_DISPATCH_FUNCTION NbSmuIndirectWriteS3Script;
#define GNB_S3_DISPATCH_FUNCTION_TABLE \
{NbSmuIndirectWriteS3Script_ID, NbSmuIndirectWriteS3Script}, \
{NbSmuServiceRequestS3Script_ID, NbSmuServiceRequestS3Script}, \
{PcieLateRestoreS3Script_ID, PcieLateRestoreS3Script},
#endif
#endif
#endif // _OPTION_GNB_INSTALL_H_

304
src/vendorcode/amd/agesa/f12/Config/OptionHtInstall.h
View File

@ -1,304 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: Ht
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_HT_INSTALL_H_
#define _OPTION_HT_INSTALL_H_
#include "Topology.h"
#include "htFeat.h"
#include "htInterface.h"
#include "htNb.h"
#include "htTopologies.h"
/*
* Advanced Option only, hardware socket naming is the preferred method.
*/
#ifdef BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP
#define CFG_SYSTEM_PHYSICAL_SOCKET_MAP (BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP)
#else
#define CFG_SYSTEM_PHYSICAL_SOCKET_MAP (NULL)
#endif
/*
* OPTION_IS_RECOVERY_HT is true if Basic API is being used.
*/
#ifndef OPTION_IS_RECOVERY_HT
#define OPTION_IS_RECOVERY_HT TRUE
#endif
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition.
*/
#ifndef OPTION_MULTISOCKET
#error BLDOPT: Option not defined: "OPTION_MULTISOCKET"
#endif
/*
* Based on user level options, set Ht internal options.
* For now, Family 10h support will assume single module. For multi module,
* this will have to be changed to not set non-coherent only.
*/
#define OPTION_HT_NON_COHERENT_ONLY FALSE
#if ((OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE) || (OPTION_FAMILY16H == TRUE))
/* Fusion Families do not need a non-coherent only option. */
#else
// Process Family 10h and 15h by socket, applying the MultiSocket option where it is allowable.
#if OPTION_G34_SOCKET_SUPPORT == FALSE
// Hydra has coherent support, other Family 10h should follow MultiSocket support.
#if OPTION_MULTISOCKET == FALSE
#undef OPTION_HT_NON_COHERENT_ONLY
#define OPTION_HT_NON_COHERENT_ONLY TRUE
#endif
#endif
#endif
/*
* Macros will generate the correct item reference based on options
*/
#if AGESA_ENTRY_INIT_EARLY == TRUE
// Select the interface and features
#if ((OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE) || (OPTION_FAMILY16H == TRUE))
#define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL
#define INTERNAL_HT_OPTION_FEATURES &HtFeaturesNone
#define INTERNAL_HT_OPTION_INTERFACE &HtInterfaceMapsOnly
#else
// Family 10h and 15h Models 00h-0Fh
#if OPTION_HT_NON_COHERENT_ONLY == FALSE
#define INTERNAL_HT_OPTION_FEATURES &HtFeaturesDefault
#define INTERNAL_HT_OPTION_INTERFACE &HtInterfaceDefault
#else
#define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL
#define INTERNAL_HT_OPTION_FEATURES &HtFeaturesNonCoherentOnly
#define INTERNAL_HT_OPTION_INTERFACE &HtInterfaceNonCoherentOnly
#endif
#endif
// Select Northbridge components
#if OPTION_FAMILY10H == TRUE
#if OPTION_HT_NON_COHERENT_ONLY == TRUE
#define INTERNAL_HT_OPTION_FAM10_NB &HtFam10NbNonCoherentOnly, &HtFam10RevDNbNonCoherentOnly,
#else
#define INTERNAL_HT_OPTION_FAM10_NB &HtFam10NbDefault, &HtFam10RevDNbDefault,
#endif
#else
#define INTERNAL_HT_OPTION_FAM10_NB
#endif
#if OPTION_FAMILY12H == TRUE
#define INTERNAL_HT_OPTION_FAM12_NB &HtFam12Nb,
#else
#define INTERNAL_HT_OPTION_FAM12_NB
#endif
#if OPTION_FAMILY14H == TRUE
#define INTERNAL_HT_OPTION_FAM14_NB &HtFam14Nb,
#else
#define INTERNAL_HT_OPTION_FAM14_NB
#endif
#if OPTION_FAMILY15H == TRUE
#if OPTION_HT_NON_COHERENT_ONLY == TRUE
#define INTERNAL_HT_OPTION_FAM15_NB &HtFam15NbNonCoherentOnly,
#else
#define INTERNAL_HT_OPTION_FAM15_NB &HtFam15NbDefault,
#endif
#else
#define INTERNAL_HT_OPTION_FAM15_NB
#endif
#define INTERNAL_ONLY_NB_LIST_ITEM INTERNAL_ONLY_HT_OPTION_SUPPORTED_NBS,
#ifndef INTERNAL_ONLY_HT_OPTION_SUPPORTED_NBS
#undef INTERNAL_ONLY_NB_LIST_ITEM
#define INTERNAL_ONLY_NB_LIST_ITEM
#endif
/* Install the correct set of northbridge implementations. Each item provides its own comma, the last item
* is ok to have a comma because the final item (NULL) is added below.
*/
#define INTERNAL_HT_OPTION_SUPPORTED_NBS \
INTERNAL_ONLY_NB_LIST_ITEM \
INTERNAL_HT_OPTION_FAM10_NB \
INTERNAL_HT_OPTION_FAM15_NB \
INTERNAL_HT_OPTION_FAM12_NB \
INTERNAL_HT_OPTION_FAM14_NB
#else
// Not Init Early
#define INTERNAL_HT_OPTION_FEATURES NULL
#define INTERNAL_HT_OPTION_INTERFACE NULL
#define INTERNAL_HT_OPTION_SUPPORTED_NBS NULL
#define HT_OPTIONS_PLATFORM NULL
#define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL
#endif
#ifdef AGESA_ENTRY_INIT_EARLY
#if AGESA_ENTRY_INIT_EARLY == TRUE
extern HT_FEATURES HtFeaturesDefault;
extern HT_FEATURES HtFeaturesNonCoherentOnly;
extern HT_FEATURES HtFeaturesNone;
extern HT_INTERFACE HtInterfaceDefault;
extern HT_INTERFACE HtInterfaceNonCoherentOnly;
extern HT_INTERFACE HtInterfaceMapsOnly;
extern HT_INTERFACE HtInterfaceNone;
extern NORTHBRIDGE HtFam10NbDefault;
extern NORTHBRIDGE HtFam10RevDNbDefault;
extern NORTHBRIDGE HtFam10NbNonCoherentOnly;
extern NORTHBRIDGE HtFam10RevDNbNonCoherentOnly;
extern NORTHBRIDGE HtFam12Nb;
extern NORTHBRIDGE HtFam14Nb;
extern NORTHBRIDGE HtFam10NbNone;
extern NORTHBRIDGE HtFam15NbDefault;
extern NORTHBRIDGE HtFam15NbNonCoherentOnly;
CONST VOID * CONST ROMDATA HtInstalledFamilyNorthbridgeList[] = {
INTERNAL_HT_OPTION_SUPPORTED_NBS
NULL
};
STATIC CONST AMD_HT_INTERFACE ROMDATA HtOptionsPlatform =
{
CFG_STARTING_BUSNUM, CFG_MAXIMUM_BUSNUM, CFG_ALLOCATED_BUSNUM,
(MANUAL_BUID_SWAP_LIST *)CFG_BUID_SWAP_LIST,
(DEVICE_CAP_OVERRIDE *)CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST,
(CPU_TO_CPU_PCB_LIMITS *)CFG_HTFABRIC_LIMITS_LIST,
(IO_PCB_LIMITS *)CFG_HTCHAIN_LIMITS_LIST,
(OVERRIDE_BUS_NUMBERS *)CFG_BUS_NUMBERS_LIST,
(IGNORE_LINK *)CFG_IGNORE_LINK_LIST,
(SKIP_REGANG *)CFG_LINK_SKIP_REGANG_LIST,
(UINT8 **)CFG_ADDITIONAL_TOPOLOGIES_LIST,
(SYSTEM_PHYSICAL_SOCKET_MAP *)CFG_SYSTEM_PHYSICAL_SOCKET_MAP
};
#ifndef HT_OPTIONS_PLATFORM
#define HT_OPTIONS_PLATFORM &HtOptionsPlatform
#endif
/**
* A list of all the supported topologies.
*
*/
#ifndef INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES
CONST UINT8 *CONST ROMDATA AmdTopolist[] =
{
amdHtTopologySingleNode,
amdHtTopologyDualNode,
amdHtTopologyThreeLine,
amdHtTopologyTriangle,
amdHtTopologyFourLine,
amdHtTopologyFourStar,
amdHtTopologyFourDegenerate,
amdHtTopologyFourSquare,
amdHtTopologyFourKite,
amdHtTopologyFourFully,
amdHtTopologyFiveFully,
amdHtTopologyFiveTwistedLadder,
amdHtTopologySixFully,
amdHtTopologySixDoubloonLower,
amdHtTopologySixDoubloonUpper,
amdHtTopologySixTwistedLadder,
amdHtTopologySevenFully,
amdHtTopologySevenTwistedLadder,
amdHtTopologyEightFully,
amdHtTopologyEightDoubloon,
amdHtTopologyEightTwistedLadder,
amdHtTopologyEightStraightLadder,
amdHtTopologySixTwinTriangles,
amdHtTopologyEightTwinFullyFourWays,
NULL
};
#define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES AmdTopolist
#endif
/**
* Declare the instance of the Ht option configuration structure
*/
CONST OPTION_HT_CONFIGURATION ROMDATA OptionHtConfiguration = {
OPTION_IS_RECOVERY_HT,
CFG_SET_HTCRC_SYNC_FLOOD,
CFG_USE_UNIT_ID_CLUMPING,
HT_OPTIONS_PLATFORM,
INTERNAL_HT_OPTION_INTERFACE,
INTERNAL_HT_OPTION_FEATURES,
&HtInstalledFamilyNorthbridgeList,
INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES
};
#endif
#endif
#ifndef OPTION_HT_INIIT_RESET_ENTRY
#define OPTION_HT_INIIT_RESET_ENTRY AmdHtInitReset
#define OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY AmdHtResetConstructor
#if (OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE)
#undef OPTION_HT_INIIT_RESET_ENTRY
#undef OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY
#define OPTION_HT_INIIT_RESET_ENTRY NULL
#define OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY NULL
#endif
#if ((OPTION_FAMILY10H == TRUE) || (OPTION_FAMILY15H_OR == TRUE))
#undef OPTION_HT_INIIT_RESET_ENTRY
#undef OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY
#define OPTION_HT_INIIT_RESET_ENTRY AmdHtInitReset
#define OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY AmdHtResetConstructor
#endif
#endif
#ifdef AGESA_ENTRY_INIT_RESET
#if AGESA_ENTRY_INIT_RESET == TRUE
CONST AMD_HT_RESET_INTERFACE ROMDATA HtOptionResetDefaults = {
(MANUAL_BUID_SWAP_LIST *)CFG_BUID_SWAP_LIST,
0 // Unused by options
};
CONST OPTION_HT_INIT_RESET ROMDATA HtOptionInitReset = {
OPTION_HT_INIIT_RESET_ENTRY,
OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY
};
#endif
#endif
#endif // _OPTION_HT_INSTALL_H_

80
src/vendorcode/amd/agesa/f12/Config/OptionHwC1eInstall.h
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@ -1,80 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: HW C1e
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_HW_C1E_INSTALL_H_
#define _OPTION_HW_C1E_INSTALL_H_
#include "cpuHwC1e.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_HW_C1E_FEAT
#define F10_HW_C1E_SUPPORT
#if AGESA_ENTRY_INIT_EARLY == TRUE
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
#if (OPTION_FAMILY10H_BL == TRUE) || (OPTION_FAMILY10H_DA == TRUE) || (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_PH == TRUE)
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureHwC1e;
#undef OPTION_HW_C1E_FEAT
#define OPTION_HW_C1E_FEAT &CpuFeatureHwC1e,
extern CONST HW_C1E_FAMILY_SERVICES ROMDATA F10HwC1e;
#undef F10_HW_C1E_SUPPORT
#define F10_HW_C1E_SUPPORT {(AMD_FAMILY_10_BL | AMD_FAMILY_10_DA | AMD_FAMILY_10_RB | AMD_FAMILY_10_PH), &F10HwC1e},
#endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA HwC1eFamilyServiceArray[] =
{
F10_HW_C1E_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA HwC1eFamilyServiceTable =
{
(sizeof (HwC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&HwC1eFamilyServiceArray[0]
};
#endif
#endif // _OPTION_HW_C1E_INSTALL_H_

407
src/vendorcode/amd/agesa/f12/Config/OptionIdsInstall.h
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@ -1,407 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* IDS Option Install File
*
* This file generates the defaults tables for family 10h model 5 processors.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 47940 $ @e \$Date: 2011-03-02 14:25:35 +0800 (Wed, 02 Mar 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_IDS_INSTALL_H_
#define _OPTION_IDS_INSTALL_H_
#include "Ids.h"
#include "IdsHt.h"
#include "IdsLib.h"
#ifdef __IDS_EXTENDED__
#include OPTION_IDS_EXT_INSTALL_FILE
#endif
#define IDS_LATE_RUN_AP_TASK
#define M_HTIDS_PORT_OVERRIDE_HOOK (PF_HtIdsGetPortOverride)CommonVoid
#if (IDSOPT_IDS_ENABLED == TRUE)
#if (IDSOPT_CONTROL_ENABLED == TRUE)
// Check for all families which include HT Features.
#if (OPTION_FAMILY10H == TRUE) && (AGESA_ENTRY_INIT_POST == TRUE)
#undef M_HTIDS_PORT_OVERRIDE_HOOK
#define M_HTIDS_PORT_OVERRIDE_HOOK HtIdsGetPortOverride
#endif
#endif
#endif // OPTION_IDS_LEVEL
CONST PF_HtIdsGetPortOverride ROMDATA pf_HtIdsGetPortOverride = M_HTIDS_PORT_OVERRIDE_HOOK;
#if (IDSOPT_IDS_ENABLED == TRUE)
#if (AGESA_ENTRY_INIT_LATE == TRUE)
#undef IDS_LATE_RUN_AP_TASK
#define IDS_LATE_RUN_AP_TASK
#endif
#endif // OPTION_IDS_LEVEL
#if (IDSOPT_TRACING_ENABLED == TRUE)
#if (AGESA_ENTRY_INIT_POST == TRUE)
#include <mu.h>
CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
{ (UINTN) MemUWriteCachelines, "WriteCl(PhyAddrLo,BufferAddr,ClCnt)"},
{ (UINTN) MemUReadCachelines, "ReadCl(BufferAddr,PhyAddrLo,ClCnt)"},
{ (UINTN) MemUFlushPattern, "FlushCl(PhyAddrLo,ClCnt)"}
};
#else
CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
{ (UINTN) CommonReturnFalse, "DefRet()"},
{ (UINTN) CommonReturnFalse, "DefRet()"},
{ (UINTN) CommonReturnFalse, "DefRet()"}
};
#endif
#endif
///Ids Feat Options
#if (IDSOPT_IDS_ENABLED == TRUE)
#if (IDSOPT_CONTROL_ENABLED == TRUE)
#ifndef OPTION_IDS_EXTEND_FEATS
#define OPTION_IDS_EXTEND_FEATS
#endif
#define OPTION_IDS_FEAT_ECCCTRL\
OPTION_IDS_FEAT_ECCCTRL_F10 \
OPTION_IDS_FEAT_ECCCTRL_F12 \
OPTION_IDS_FEAT_ECCCTRL_F15_OR
#define OPTION_IDS_FEAT_GNB_PLATFORMCFG\
OPTION_IDS_FEAT_GNB_PLATFORMCFGF12 \
OPTION_IDS_FEAT_GNB_PLATFORMCFGF14
#define OPTION_IDS_FEAT_CPB_CTRL\
OPTION_IDS_FEAT_CPB_CTRL_F12
#define OPTION_IDS_FEAT_HTC_CTRL\
OPTION_IDS_FEAT_HTC_CTRL_F15
#define OPTION_IDS_FEAT_MEMORY_MAPPING\
OPTION_IDS_FEAT_MEMORY_MAPPING_F12 \
OPTION_IDS_FEAT_MEMORY_MAPPING_F15_OR
#define OPTION_IDS_FEAT_HT_ASSIST\
OPTION_IDS_FEAT_HT_ASSIST_F10HY \
OPTION_IDS_FEAT_HT_ASSIST_F15_OR
#define OPTION_IDS_FEAT_ECCSYMBOLSIZE\
OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10 \
OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15_OR
/*----------------------------------------------------------------------------
* Family 10 feat blocks
*
*----------------------------------------------------------------------------
*/
#define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10
#define OPTION_IDS_FEAT_ECCCTRL_F10
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
//Ecc symbol size
extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccSymbolSizeBlockF10;
#undef OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10
#define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10 &IdsFeatEccSymbolSizeBlockF10,
//ECC scrub control
extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF10;
#undef OPTION_IDS_FEAT_ECCCTRL_F10
#define OPTION_IDS_FEAT_ECCCTRL_F10 &IdsFeatEccCtrlBlockF10,
#endif
#endif
//Misc Features
#define OPTION_IDS_FEAT_HT_ASSIST_F10HY
#ifdef OPTION_FAMILY10H_HY
#if OPTION_FAMILY10H_HY == TRUE
#undef OPTION_IDS_FEAT_HT_ASSIST_F10HY
extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtAssistBlockPlatformCfgF10Hy;
#define OPTION_IDS_FEAT_HT_ASSIST_F10HY \
&IdsFeatHtAssistBlockPlatformCfgF10Hy,
#endif
#endif
/*----------------------------------------------------------------------------
* Family 12 feat blocks
*
*----------------------------------------------------------------------------
*/
#define OPTION_IDS_FEAT_GNB_PLATFORMCFGF12
#define OPTION_IDS_FEAT_ECCCTRL_F12
#define OPTION_IDS_FEAT_CPB_CTRL_F12
#ifdef OPTION_FAMILY12H
#if OPTION_FAMILY12H == TRUE
extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatGnbPlatformCfgBlockF12;
#undef OPTION_IDS_FEAT_GNB_PLATFORMCFGF12
#define OPTION_IDS_FEAT_GNB_PLATFORMCFGF12 &IdsFeatGnbPlatformCfgBlockF12,
//ECC scrub control
extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF12;
#undef OPTION_IDS_FEAT_ECCCTRL_F12
#define OPTION_IDS_FEAT_ECCCTRL_F12 &IdsFeatEccCtrlBlockF12,
#undef OPTION_IDS_FEAT_CPB_CTRL_F12
extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatCpbCtrlBlockF12;
#define OPTION_IDS_FEAT_CPB_CTRL_F12 &IdsFeatCpbCtrlBlockF12,
#endif
#endif
/*----------------------------------------------------------------------------
* Family 14 feat blocks
*
*----------------------------------------------------------------------------
*/
#define OPTION_IDS_FEAT_GNB_PLATFORMCFGF14
#ifdef OPTION_FAMILY14H
#if OPTION_FAMILY14H == TRUE
extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatGnbPlatformCfgBlockF14;
#undef OPTION_IDS_FEAT_GNB_PLATFORMCFGF14
#define OPTION_IDS_FEAT_GNB_PLATFORMCFGF14 &IdsFeatGnbPlatformCfgBlockF14,
#endif
#endif
/*----------------------------------------------------------------------------
* Family 15 OR feat blocks
*
*----------------------------------------------------------------------------
*/
#define OPTION_IDS_FEAT_HTC_CTRL_F15_OR
#define OPTION_IDS_FEAT_MEMORY_MAPPING_F15_OR
#define OPTION_IDS_FEAT_HT_ASSIST_F15_OR
#define OPTION_IDS_FEAT_ECCCTRL_F15_OR
#define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15_OR
#ifdef OPTION_FAMILY15H_OR
#if OPTION_FAMILY15H_OR == TRUE
extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtcControlBlockF15Or;
extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtcControlLateBlockF15Or;
#undef OPTION_IDS_FEAT_HTC_CTRL_F15_OR
#define OPTION_IDS_FEAT_HTC_CTRL_F15_OR\
&IdsFeatHtcControlBlockF15Or,\
&IdsFeatHtcControlLateBlockF15Or,
extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingPostBeforeBlockF15Or;
extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingChIntlvBlockF15Or;
#undef OPTION_IDS_FEAT_MEMORY_MAPPING_F15_OR
#define OPTION_IDS_FEAT_MEMORY_MAPPING_F15_OR\
&IdsFeatMemoryMappingPostBeforeBlockF15Or,\
&IdsFeatMemoryMappingChIntlvBlockF15Or,
extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtAssistBlockPlatformCfgF15Or;
#undef OPTION_IDS_FEAT_HT_ASSIST_F15_OR
#define OPTION_IDS_FEAT_HT_ASSIST_F15_OR\
&IdsFeatHtAssistBlockPlatformCfgF15Or,
extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF15Or;
#undef OPTION_IDS_FEAT_ECCCTRL_F15_OR
#define OPTION_IDS_FEAT_ECCCTRL_F15_OR &IdsFeatEccCtrlBlockF15Or,
extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccSymbolSizeBlockF15Or;
#undef OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15_OR
#define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15_OR &IdsFeatEccSymbolSizeBlockF15Or,
#endif
#endif
CONST IDS_FEAT_STRUCT ROMDATA IdsFeatUcodeBlock =
{
IDS_FEAT_UCODE_UPDATE,
IDS_ALL_CORES,
IDS_UCODE,
IDS_FAMILY_ALL,
IdsSubUCode
};
CONST IDS_FEAT_STRUCT ROMDATA IdsFeatPowerPolicyBlock =
{
IDS_FEAT_POWER_POLICY,
IDS_ALL_CORES,
IDS_PLATFORMCFG_OVERRIDE,
IDS_FAMILY_ALL,
IdsSubPowerPolicyOverride
};
CONST IDS_FEAT_STRUCT ROMDATA IdsFeatTargetPstateBlock =
{
IDS_FEAT_TARGET_PSTATE,
IDS_BSP_ONLY,
IDS_INIT_LATE_AFTER,
IDS_FAMILY_ALL,
IdsSubTargetPstate
};
CONST IDS_FEAT_STRUCT ROMDATA IdsFeatPostPstateBlock =
{
IDS_FEAT_POSTPSTATE,
IDS_ALL_CORES,
IDS_CPU_Early_Override,
IDS_FAMILY_ALL,
IdsSubPostPState
};
//Dram controller Features
CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctAllMemClkBlock =
{
IDS_FEAT_DCT_ALLMEMCLK,
IDS_BSP_ONLY,
IDS_ALL_MEMORY_CLOCK,
IDS_FAMILY_ALL,
IdsSubAllMemClkEn
};
CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctGangModeBlock =
{
IDS_FEAT_DCT_GANGMODE,
IDS_BSP_ONLY,
IDS_GANGING_MODE,
IDS_FAMILY_ALL,
IdsSubGangingMode
};
CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctBurstLengthBlock =
{
IDS_FEAT_DCT_BURSTLENGTH,
IDS_BSP_ONLY,
IDS_BURST_LENGTH32,
AMD_FAMILY_10,
IdsSubBurstLength32
};
CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctPowerDownCtrlBlock =
{
IDS_FEAT_DCT_POWERDOWN,
IDS_BSP_ONLY,
IDS_INIT_POST_BEFORE,
IDS_FAMILY_ALL,
IdsSubPowerDownCtrl
};
CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctDllShutDownBlock =
{
IDS_FEAT_DCT_DLLSHUTDOWN,
IDS_BSP_ONLY,
IDS_DLL_SHUT_DOWN,
IDS_FAMILY_ALL,
IdsSubDllShutDownSR
};
CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctPowerDownModeBlock =
{
IDS_FEAT_DCT_POWERDOWN,
IDS_BSP_ONLY,
IDS_POWERDOWN_MODE,
IDS_FAMILY_ALL,
IdsSubPowerDownMode
};
CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHdtOutBlock =
{
IDS_FEAT_HDTOUT,
IDS_BSP_ONLY,
IDS_INIT_EARLY_BEFORE,
IDS_FAMILY_ALL,
IdsSubHdtOut
};
CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtSettingBlock =
{
IDS_FEAT_HT_SETTING,
IDS_BSP_ONLY,
IDS_HT_CONTROL,
IDS_FAMILY_ALL,
IdsSubHtLinkControl
};
CONST IDS_FEAT_STRUCT* ROMDATA IdsCommonFeats[] =
{
&IdsFeatUcodeBlock,
&IdsFeatPowerPolicyBlock,
&IdsFeatTargetPstateBlock,
&IdsFeatPostPstateBlock,
OPTION_IDS_FEAT_ECCSYMBOLSIZE
OPTION_IDS_FEAT_ECCCTRL
&IdsFeatDctAllMemClkBlock,
&IdsFeatDctGangModeBlock,
&IdsFeatDctBurstLengthBlock,
&IdsFeatDctPowerDownCtrlBlock,
&IdsFeatDctPowerDownModeBlock,
&IdsFeatDctPowerDownModeBlock,
OPTION_IDS_FEAT_HT_ASSIST
&IdsFeatHdtOutBlock,
&IdsFeatHtSettingBlock,
OPTION_IDS_FEAT_GNB_PLATFORMCFG
OPTION_IDS_FEAT_CPB_CTRL
OPTION_IDS_FEAT_HTC_CTRL
OPTION_IDS_FEAT_MEMORY_MAPPING
OPTION_IDS_EXTEND_FEATS
NULL
};
#else
CONST IDS_FEAT_STRUCT* ROMDATA IdsCommonFeats[] =
{
NULL
};
#endif//IDSOPT_CONTROL_ENABLED
#else
CONST IDS_FEAT_STRUCT* ROMDATA IdsCommonFeats[] =
{
NULL
};
#endif// IDSOPT_IDS_ENABLED
#endif

132
src/vendorcode/amd/agesa/f12/Config/OptionIoCstateInstall.h
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@ -1,132 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: IO C-state
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_IO_CSTATE_INSTALL_H_
#define _OPTION_IO_CSTATE_INSTALL_H_
#include "cpuIoCstate.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_IO_CSTATE_FEAT
#define F10_IO_CSTATE_SUPPORT
#define F12_IO_CSTATE_SUPPORT
#define F14_IO_CSTATE_SUPPORT
#define F15_OR_IO_CSTATE_SUPPORT
#if OPTION_IO_CSTATE == TRUE
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
#if OPTION_FAMILY10H_PH == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate;
#undef OPTION_IO_CSTATE_FEAT
#define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate,
extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F10IoCstateSupport;
#undef F10_IO_CSTATE_SUPPORT
#define F10_IO_CSTATE_SUPPORT {AMD_FAMILY_10_PH, &F10IoCstateSupport},
#endif
#endif
#endif
#ifdef OPTION_FAMILY12H
#if OPTION_FAMILY12H == TRUE
#if OPTION_FAMILY12H_LN == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate;
#undef OPTION_IO_CSTATE_FEAT
#define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate,
extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F12IoCstateSupport;
#undef F12_IO_CSTATE_SUPPORT
#define F12_IO_CSTATE_SUPPORT {AMD_FAMILY_12_LN, &F12IoCstateSupport},
#endif
#endif
#endif
#ifdef OPTION_FAMILY14H
#if OPTION_FAMILY14H == TRUE
#if OPTION_FAMILY14H_ON == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate;
#undef OPTION_IO_CSTATE_FEAT
#define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate,
extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F14IoCstateSupport;
#undef F14_IO_CSTATE_SUPPORT
#define F14_IO_CSTATE_SUPPORT {AMD_FAMILY_14, &F14IoCstateSupport},
#endif
#endif
#endif
#ifdef OPTION_FAMILY15H
#if OPTION_FAMILY15H == TRUE
#if OPTION_FAMILY15H_OR == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate;
#undef OPTION_IO_CSTATE_FEAT
#define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate,
extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F15OrIoCstateSupport;
#undef F15_OR_IO_CSTATE_SUPPORT
#define F15_OR_IO_CSTATE_SUPPORT {AMD_FAMILY_15_OR, &F15OrIoCstateSupport},
#endif
#endif
#endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA IoCstateFamilyServiceArray[] =
{
F10_IO_CSTATE_SUPPORT
F12_IO_CSTATE_SUPPORT
F14_IO_CSTATE_SUPPORT
F15_OR_IO_CSTATE_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA IoCstateFamilyServiceTable =
{
(sizeof (IoCstateFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&IoCstateFamilyServiceArray[0]
};
#endif // _OPTION_IO_CSTATE_INSTALL_H_

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: L3 Dependent Features
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_L3_FEATURES_INSTALL_H_
#define _OPTION_L3_FEATURES_INSTALL_H_
#include "cpuL3Features.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_L3_FEAT
#define F10_L3_FEAT_SUPPORT
#define F15_L3_FEAT_SUPPORT
#define L3_FEAT_AP_DISABLE_CACHE
#define L3_FEAT_AP_ENABLE_CACHE
#if (OPTION_HT_ASSIST == TRUE || OPTION_ATM_MODE == TRUE)
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
#if OPTION_FAMILY10H_HY == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuL3Features;
#undef OPTION_L3_FEAT
#define OPTION_L3_FEAT &CpuL3Features,
extern CONST L3_FEATURE_FAMILY_SERVICES ROMDATA F10L3Features;
#undef F10_L3_FEAT_SUPPORT
#define F10_L3_FEAT_SUPPORT {AMD_FAMILY_10_HY, &F10L3Features},
#endif
#endif
#endif
#ifdef OPTION_FAMILY15H
#if OPTION_FAMILY15H == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuL3Features;
#undef OPTION_L3_FEAT
#define OPTION_L3_FEAT &CpuL3Features,
extern CONST L3_FEATURE_FAMILY_SERVICES ROMDATA F15OrL3Features;
#undef F15_L3_FEAT_SUPPORT
#define F15_L3_FEAT_SUPPORT {AMD_FAMILY_15, &F15OrL3Features},
#endif
#endif
#undef L3_FEAT_AP_DISABLE_CACHE
#define L3_FEAT_AP_DISABLE_CACHE {AP_LATE_TASK_DISABLE_CACHE, (IMAGE_ENTRY) DisableAllCaches},
#undef L3_FEAT_AP_ENABLE_CACHE
#define L3_FEAT_AP_ENABLE_CACHE {AP_LATE_TASK_ENABLE_CACHE, (IMAGE_ENTRY) EnableAllCaches},
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA L3FeatureFamilyServiceArray[] =
{
F10_L3_FEAT_SUPPORT
F15_L3_FEAT_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA L3FeatureFamilyServiceTable =
{
(sizeof (L3FeatureFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&L3FeatureFamilyServiceArray[0]
};
#endif // _OPTION_L3_FEATURES_INSTALL_H_

86
src/vendorcode/amd/agesa/f12/Config/OptionLowPwrPstateInstall.h
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@ -1,86 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: Low Power Pstate for PROCHOT_L Throttling.
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_LOW_PWR_PSTATE_INSTALL_H_
#define _OPTION_LOW_PWR_PSTATE_INSTALL_H_
#include "cpuLowPwrPstate.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT
#define F15_LOW_PWR_PSTATE_SUPPORT
#if OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT == TRUE
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
// Family 15h
#ifdef OPTION_FAMILY15H
#if OPTION_FAMILY15H == TRUE
#if OPTION_FAMILY15H_OR == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureLowPwrPstate;
#undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT
#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT &CpuFeatureLowPwrPstate,
extern CONST LOW_PWR_PSTATE_FAMILY_SERVICES ROMDATA F15OrLowPwrPstateSupport;
#undef F15_LOW_PWR_PSTATE_SUPPORT
#define F15_LOW_PWR_PSTATE_SUPPORT {AMD_FAMILY_15_OR, &F15OrLowPwrPstateSupport},
#endif
#endif
#endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA LowPwrPstateFamilyServiceArray[] =
{
F15_LOW_PWR_PSTATE_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA LowPwrPstateFamilyServiceTable =
{
(sizeof (LowPwrPstateFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&LowPwrPstateFamilyServiceArray[0]
};
#endif // _OPTION_LOW_PWR_PSTATE_INSTALL_H_

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src/vendorcode/amd/agesa/f12/Config/OptionMemoryInstall.h
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116
src/vendorcode/amd/agesa/f12/Config/OptionMsgBasedC1eInstall.h
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@ -1,116 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: Message-Based C1e
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_MSG_BASED_C1E_INSTALL_H_
#define _OPTION_MSG_BASED_C1E_INSTALL_H_
#include "cpuMsgBasedC1e.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_MSG_BASED_C1E_FEAT
#define F10_MSG_BASED_C1E_SUPPORT
#define F15_MSG_BASED_C1E_SUPPORT
#if OPTION_MSG_BASED_C1E == TRUE
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE)
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
#if OPTION_FAMILY10H_HY == TRUE
#if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE)
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureMsgBasedC1e;
#undef OPTION_MSG_BASED_C1E_FEAT
#define OPTION_MSG_BASED_C1E_FEAT &CpuFeatureMsgBasedC1e,
#endif
#endif
#endif
#endif
#ifdef OPTION_FAMILY15H
#if OPTION_FAMILY15H == TRUE
#if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE || OPTION_AM3_SOCKET_SUPPORT == TRUE)
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureMsgBasedC1e;
#undef OPTION_MSG_BASED_C1E_FEAT
#define OPTION_MSG_BASED_C1E_FEAT &CpuFeatureMsgBasedC1e,
#endif
#endif
#endif
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
#if OPTION_FAMILY10H_HY == TRUE
#if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE)
extern CONST MSG_BASED_C1E_FAMILY_SERVICES ROMDATA F10MsgBasedC1e;
#undef F10_MSG_BASED_C1E_SUPPORT
#define F10_MSG_BASED_C1E_SUPPORT {AMD_FAMILY_10_HY, &F10MsgBasedC1e},
#endif
#endif
#endif
#endif
#ifdef OPTION_FAMILY15H
#if OPTION_FAMILY15H == TRUE
#if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE || OPTION_AM3_SOCKET_SUPPORT == TRUE)
extern CONST MSG_BASED_C1E_FAMILY_SERVICES ROMDATA F15OrMsgBasedC1e;
#undef F15_MSG_BASED_C1E_SUPPORT
#define F15_MSG_BASED_C1E_SUPPORT {AMD_FAMILY_15, &F15OrMsgBasedC1e},
#endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA MsgBasedC1eFamilyServiceArray[] =
{
F10_MSG_BASED_C1E_SUPPORT
F15_MSG_BASED_C1E_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA MsgBasedC1eFamilyServiceTable =
{
(sizeof (MsgBasedC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&MsgBasedC1eFamilyServiceArray[0]
};
#endif
#endif
#endif // _OPTION_MSG_BASED_C1E_INSTALL_H_

94
src/vendorcode/amd/agesa/f12/Config/OptionMultiSocketInstall.h
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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: Multiple Socket Support
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 48937 $ @e \$Date: 2011-03-15 03:37:15 +0800 (Tue, 15 Mar 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_MULTISOCKET_INSTALL_H_
#define _OPTION_MULTISOCKET_INSTALL_H_
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#ifndef OPTION_MULTISOCKET
#error BLDOPT: Option not defined: "OPTION_MULTISOCKET"
#endif
#if OPTION_MULTISOCKET == TRUE
OPTION_MULTISOCKET_PM_STEPS GetNumberOfSystemPmStepsPtrMulti;
#define GET_NUM_PM_STEPS GetNumberOfSystemPmStepsPtrMulti
OPTION_MULTISOCKET_PM_CORE0_TASK RunCodeOnAllSystemCore0sMulti;
#define CORE0_PM_TASK RunCodeOnAllSystemCore0sMulti
OPTION_MULTISOCKET_PM_NB_COF GetSystemNbCofMulti;
#define GET_SYS_NB_COF GetSystemNbCofMulti
OPTION_MULTISOCKET_PM_NB_COF_UPDATE GetSystemNbCofVidUpdateMulti;
#define GET_SYS_NB_COF_UPDATE GetSystemNbCofVidUpdateMulti
OPTION_MULTISOCKET_PM_GET_EVENTS GetEarlyPmErrorsMulti;
#define GET_EARLY_PM_ERRORS GetEarlyPmErrorsMulti
OPTION_MULTISOCKET_PM_NB_MIN_COF GetMinNbCofMulti;
#define GET_MIN_NB_COF GetMinNbCofMulti
#else
OPTION_MULTISOCKET_PM_STEPS GetNumberOfSystemPmStepsPtrSingle;
#define GET_NUM_PM_STEPS GetNumberOfSystemPmStepsPtrSingle
OPTION_MULTISOCKET_PM_CORE0_TASK RunCodeOnAllSystemCore0sSingle;
#define CORE0_PM_TASK RunCodeOnAllSystemCore0sSingle
OPTION_MULTISOCKET_PM_NB_COF GetSystemNbCofSingle;
#define GET_SYS_NB_COF GetSystemNbCofSingle
OPTION_MULTISOCKET_PM_NB_COF_UPDATE GetSystemNbCofVidUpdateSingle;
#define GET_SYS_NB_COF_UPDATE GetSystemNbCofVidUpdateSingle
OPTION_MULTISOCKET_PM_GET_EVENTS GetEarlyPmErrorsSingle;
#define GET_EARLY_PM_ERRORS GetEarlyPmErrorsSingle
OPTION_MULTISOCKET_PM_NB_MIN_COF GetMinNbCofSingle;
#define GET_MIN_NB_COF GetMinNbCofSingle
#endif
/* Declare the instance of the DMI option configuration structure */
OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration = {
MULTISOCKET_STRUCT_VERSION,
GET_NUM_PM_STEPS,
CORE0_PM_TASK,
GET_SYS_NB_COF,
GET_SYS_NB_COF_UPDATE,
GET_EARLY_PM_ERRORS,
GET_MIN_NB_COF
};
#endif // _OPTION_MULTISOCKET_INSTALL_H_

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src/vendorcode/amd/agesa/f12/Config/OptionPreserveMailboxInstall.h
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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: Preserve Mailbox
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 50096 $ @e \$Date: 2011-04-02 06:17:10 +0800 (Sat, 02 Apr 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_PRESERVE_MAILBOX_INSTALL_H_
#define _OPTION_PRESERVE_MAILBOX_INSTALL_H_
#include "PreserveMailbox.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_PRESERVE_MAILBOX_FEAT
#define F10_PRESERVE_MAILBOX_SUPPORT
#define F15_PRESERVE_MAILBOX_SUPPORT
#if ((AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE))
#if ((OPTION_FAMILY10H == TRUE) || (OPTION_FAMILY15H == TRUE))
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeaturePreserveAroundMailbox;
#undef OPTION_PRESERVE_MAILBOX_FEAT
#define OPTION_PRESERVE_MAILBOX_FEAT &CpuFeaturePreserveAroundMailbox,
#endif
#if OPTION_FAMILY10H == TRUE
CONST PRESERVE_MAILBOX_FAMILY_REGISTER ROMDATA F10PreserveMailboxRegisters [] = {
{
MAKE_SBDFO (0, 0, 0, 3, 0x168),
0x00000FFF
},
{
MAKE_SBDFO (0, 0, 0, 3, 0x170),
0x00000FFF
},
{
ILLEGAL_SBDFO,
0
}
};
CONST PRESERVE_MAILBOX_FAMILY_SERVICES ROMDATA F10PreserveMailboxServices = {
0,
TRUE,
(PRESERVE_MAILBOX_FAMILY_REGISTER *)&F10PreserveMailboxRegisters
};
#undef F10_PRESERVE_MAILBOX_SUPPORT
#define F10_PRESERVE_MAILBOX_SUPPORT {AMD_FAMILY_10, &F10PreserveMailboxServices},
#endif
#if OPTION_FAMILY15H == TRUE
CONST PRESERVE_MAILBOX_FAMILY_REGISTER ROMDATA F15PreserveMailboxRegisters [] = {
{
MAKE_SBDFO (0, 0, 0, 3, 0x168),
0x00000FFF
},
{
MAKE_SBDFO (0, 0, 0, 3, 0x170),
0x00000FFF
},
{
ILLEGAL_SBDFO,
0
}
};
CONST PRESERVE_MAILBOX_FAMILY_SERVICES ROMDATA F15PreserveMailboxServices = {
0,
TRUE,
(PRESERVE_MAILBOX_FAMILY_REGISTER *)&F15PreserveMailboxRegisters
};
#undef F15_PRESERVE_MAILBOX_SUPPORT
#define F15_PRESERVE_MAILBOX_SUPPORT {AMD_FAMILY_15, &F15PreserveMailboxServices},
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PreserveMailboxFamilyServiceArray[] =
{
F10_PRESERVE_MAILBOX_SUPPORT
F15_PRESERVE_MAILBOX_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PreserveMailboxFamilyServiceTable =
{
(sizeof (PreserveMailboxFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&PreserveMailboxFamilyServiceArray[0]
};
#endif
#endif // _OPTION_PRESERVE_MAILBOX_INSTALL_H_

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@ -1,254 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: PState
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_PSTATE_INSTALL_H_
#define _OPTION_PSTATE_INSTALL_H_
#include "cpuPstateTables.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define F10_PSTATE_SERVICE_SUPPORT
#define F12_PSTATE_SERVICE_SUPPORT
#define F14_PSTATE_SERVICE_SUPPORT
#define F15_OR_PSTATE_SERVICE_SUPPORT
#define F15_TN_PSTATE_SERVICE_SUPPORT
#if ((AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE))
//
//Define Pstate CPU Family service
//
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F10PstateServices;
#undef F10_PSTATE_SERVICE_SUPPORT
#define F10_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_10, &F10PstateServices},
#endif
#endif
#ifdef OPTION_FAMILY12H
#if OPTION_FAMILY12H == TRUE
extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F12PstateServices;
#undef F12_PSTATE_SERVICE_SUPPORT
#define F12_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_12, &F12PstateServices},
#endif
#endif
#ifdef OPTION_FAMILY14H
#if OPTION_FAMILY14H == TRUE
extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F14PstateServices;
#undef F14_PSTATE_SERVICE_SUPPORT
#define F14_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_14, &F14PstateServices},
#endif
#endif
#ifdef OPTION_FAMILY15H
#if OPTION_FAMILY15H == TRUE
#ifdef OPTION_FAMILY15H_OR
#if OPTION_FAMILY15H_OR == TRUE
extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F15OrPstateServices;
#undef F15_OR_PSTATE_SERVICE_SUPPORT
#define F15_OR_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_15_OR, &F15OrPstateServices},
#endif
#endif
#ifdef OPTION_FAMILY15H_TN
#if OPTION_FAMILY15H_TN == TRUE
extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F15TnPstateServices;
#undef F15_TN_PSTATE_SERVICE_SUPPORT
#define F15_TN_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_15_TN, &F15TnPstateServices},
#endif
#endif
#endif
#endif
//
//Define ACPI Pstate objects.
//
#ifndef OPTION_ACPI_PSTATES
#error BLDOPT: Option not defined: "OPTION_ACPI_PSTATES"
#endif
#if (OPTION_ACPI_PSTATES == TRUE)
// OPTION_SSDT_FEATURE GenerateSsdt;
#define USER_SSDT_MAIN GenerateSsdt
#ifndef OPTION_MULTISOCKET
#error BLDOPT: Option not defined: "OPTION_MULTISOCKET"
#endif
// OPTION_ACPI_FEATURE CreatePStateAcpiTables;
OPTION_PSTATE_GATHER PStateGatherMain;
#if ((OPTION_MULTISOCKET == TRUE) && (AGESA_ENTRY_INIT_POST == TRUE))
OPTION_PSTATE_LEVELING PStateLevelingMain;
#define USER_PSTATE_OPTION_LEVEL PStateLevelingMain
#else
OPTION_PSTATE_LEVELING PStateLevelingStub;
#define USER_PSTATE_OPTION_LEVEL PStateLevelingStub
#endif
#if AGESA_ENTRY_INIT_LATE == TRUE
#define USER_PSTATE_OPTION_MAIN CreatePStateAcpiTables
#else
// OPTION_ACPI_FEATURE CreateAcpiTablesStub;
#define USER_PSTATE_OPTION_MAIN CreateAcpiTablesStub
#endif
#if AGESA_ENTRY_INIT_POST == TRUE
#define USER_PSTATE_OPTION_GATHER PStateGatherMain
#else
OPTION_PSTATE_GATHER PStateGatherStub;
#define USER_PSTATE_OPTION_GATHER PStateGatherStub
#endif
#if CFG_ACPI_PSTATES_PPC == TRUE
#define USER_PSTATE_CFG_PPC TRUE
#else
#define USER_PSTATE_CFG_PPC FALSE
#endif
#if CFG_ACPI_PSTATES_PCT == TRUE
#define USER_PSTATE_CFG_PCT TRUE
#else
#define USER_PSTATE_CFG_PCT FALSE
#endif
#if CFG_ACPI_PSTATES_PSD == TRUE
#define USER_PSTATE_CFG_PSD TRUE
#else
#define USER_PSTATE_CFG_PSD FALSE
#endif
#if CFG_ACPI_PSTATES_PSS == TRUE
#define USER_PSTATE_CFG_PSS TRUE
#else
#define USER_PSTATE_CFG_PSS FALSE
#endif
#if CFG_ACPI_PSTATES_XPSS == TRUE
#define USER_PSTATE_CFG_XPSS TRUE
#else
#define USER_PSTATE_CFG_XPSS FALSE
#endif
#if OPTION_IO_CSTATE == TRUE
// OPTION_ACPI_FEATURE CreateCStateAcpiTables;
#define USER_CSTATE_OPTION_MAIN CreateCStateAcpiTables
#else
OPTION_ACPI_FEATURE CreateAcpiTablesStub;
#define USER_CSTATE_OPTION_MAIN CreateAcpiTablesStub
#endif
#else
OPTION_SSDT_FEATURE GenerateSsdtStub;
OPTION_ACPI_FEATURE CreateAcpiTablesStub;
OPTION_PSTATE_GATHER PStateGatherStub;
OPTION_PSTATE_LEVELING PStateLevelingStub;
#define USER_SSDT_MAIN GenerateSsdtStub
#define USER_PSTATE_OPTION_MAIN CreateAcpiTablesStub
#define USER_CSTATE_OPTION_MAIN CreateAcpiTablesStub
#define USER_PSTATE_OPTION_GATHER PStateGatherStub
#define USER_PSTATE_OPTION_LEVEL PStateLevelingStub
#define USER_PSTATE_CFG_PPC FALSE
#define USER_PSTATE_CFG_PCT FALSE
#define USER_PSTATE_CFG_PSD FALSE
#define USER_PSTATE_CFG_PSS FALSE
#define USER_PSTATE_CFG_XPSS FALSE
// If ACPI Objects are disabled for PStates, we still need to check
// whether ACPI Objects are enabled for CStates
#if OPTION_IO_CSTATE == TRUE
OPTION_SSDT_FEATURE GenerateSsdt;
OPTION_PSTATE_GATHER PStateGatherMain;
OPTION_ACPI_FEATURE CreateCStateAcpiTables;
#undef USER_SSDT_MAIN
#define USER_SSDT_MAIN GenerateSsdt
#undef USER_PSTATE_OPTION_GATHER
#define USER_PSTATE_OPTION_GATHER PStateGatherMain
#undef USER_CSTATE_OPTION_MAIN
#define USER_CSTATE_OPTION_MAIN CreateCStateAcpiTables
#endif
#endif
#else
OPTION_SSDT_FEATURE GenerateSsdtStub;
OPTION_ACPI_FEATURE CreateAcpiTablesStub;
OPTION_PSTATE_GATHER PStateGatherStub;
OPTION_PSTATE_LEVELING PStateLevelingStub;
#define USER_SSDT_MAIN GenerateSsdtStub
#define USER_PSTATE_OPTION_MAIN CreateAcpiTablesStub
#define USER_CSTATE_OPTION_MAIN CreateAcpiTablesStub
#define USER_PSTATE_OPTION_GATHER PStateGatherStub
#define USER_PSTATE_OPTION_LEVEL PStateLevelingStub
#define USER_PSTATE_CFG_PPC FALSE
#define USER_PSTATE_CFG_PCT FALSE
#define USER_PSTATE_CFG_PSD FALSE
#define USER_PSTATE_CFG_PSS FALSE
#define USER_PSTATE_CFG_XPSS FALSE
#endif
/* Declare the instance of the PSTATE option configuration structure */
OPTION_PSTATE_POST_CONFIGURATION OptionPstatePostConfiguration = {
PSTATE_STRUCT_VERSION,
USER_PSTATE_OPTION_GATHER,
USER_PSTATE_OPTION_LEVEL
};
OPTION_PSTATE_LATE_CONFIGURATION OptionPstateLateConfiguration = {
PSTATE_STRUCT_VERSION,
USER_SSDT_MAIN,
USER_PSTATE_OPTION_MAIN,
USER_CSTATE_OPTION_MAIN,
USER_PSTATE_CFG_PPC,
USER_PSTATE_CFG_PCT,
USER_PSTATE_CFG_PSD,
USER_PSTATE_CFG_PSS,
USER_PSTATE_CFG_XPSS
};
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PstateCpuFamilyServiceArray[] =
{
F10_PSTATE_SERVICE_SUPPORT
F12_PSTATE_SERVICE_SUPPORT
F14_PSTATE_SERVICE_SUPPORT
F15_OR_PSTATE_SERVICE_SUPPORT
F15_TN_PSTATE_SERVICE_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PstateFamilyServiceTable =
{
(sizeof (PstateCpuFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&PstateCpuFamilyServiceArray[0]
};
#endif // _OPTION_PSTATE_INSTALL_H_

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: S3SCRIPT
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_S3SCRIPT_INSTALL_H_
#define _OPTION_S3SCRIPT_INSTALL_H_
#include "S3SaveState.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#ifndef OPTION_S3SCRIPT
#define OPTION_S3SCRIPT FALSE //if not define assume PI not use script
#endif
#if (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_ENV == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE)
#if OPTION_S3SCRIPT == TRUE
#define P_S3_SCRIPT_INIT S3ScriptInitState
#endif
#endif
#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
#if OPTION_S3SCRIPT == TRUE
#define P_S3_SCRIPT_RESTORE S3ScriptRestoreState
#endif
#endif
#ifndef P_S3_SCRIPT_INIT
#define P_S3_SCRIPT_INIT S3ScriptInitStateStub
#endif
#ifndef P_S3_SCRIPT_RESTORE
#define P_S3_SCRIPT_RESTORE S3ScriptInitStateStub
#undef GNB_S3_DISPATCH_FUNCTION_TABLE
#endif
#ifndef GNB_S3_DISPATCH_FUNCTION_TABLE
#define GNB_S3_DISPATCH_FUNCTION_TABLE
#endif
/* Declare the instance of the S3SCRIPT option configuration structure */
S3_SCRIPT_CONFIGURATION OptionS3ScriptConfiguration = {
P_S3_SCRIPT_INIT,
P_S3_SCRIPT_RESTORE
};
S3_DISPATCH_FUNCTION_ENTRY S3DispatchFunctionTable [] = {
GNB_S3_DISPATCH_FUNCTION_TABLE
{0, NULL}
};
#endif // _OPTION_S3SCRIPT_INSTALL_H_

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: SLIT
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_SLIT_INSTALL_H_
#define _OPTION_SLIT_INSTALL_H_
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#if AGESA_ENTRY_INIT_LATE == TRUE
#ifndef OPTION_SLIT
#error BLDOPT: Option not defined: "OPTION_SLIT"
#endif
#if OPTION_SLIT == TRUE
OPTION_SLIT_FEATURE GetAcpiSlitMain;
OPTION_SLIT_RELEASE_BUFFER ReleaseSlitBuffer;
#define USER_SLIT_OPTION GetAcpiSlitMain
#define USER_SLIT_RELEASE_BUFFER ReleaseSlitBuffer
#else
OPTION_SLIT_FEATURE GetAcpiSlitStub;
OPTION_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub;
#define USER_SLIT_OPTION GetAcpiSlitStub
#define USER_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub
#endif
#else
OPTION_SLIT_FEATURE GetAcpiSlitStub;
OPTION_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub;
#define USER_SLIT_OPTION GetAcpiSlitStub
#define USER_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub
#endif
/* Declare the instance of the SLIT option configuration structure */
OPTION_SLIT_CONFIGURATION OptionSlitConfiguration = {
SLIT_STRUCT_VERSION,
USER_SLIT_OPTION,
USER_SLIT_RELEASE_BUFFER
};
#endif // _OPTION_SLIT_INSTALL_H_

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: SRAT
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_SRAT_INSTALL_H_
#define _OPTION_SRAT_INSTALL_H_
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#if AGESA_ENTRY_INIT_LATE == TRUE
#ifndef OPTION_SRAT
#error BLDOPT: Option not defined: "OPTION_SRAT"
#endif
#if OPTION_SRAT == TRUE
OPTION_SRAT_FEATURE GetAcpiSratMain;
#define USER_SRAT_OPTION GetAcpiSratMain
#else
OPTION_SRAT_FEATURE GetAcpiSratStub;
#define USER_SRAT_OPTION GetAcpiSratStub
#endif
#else
OPTION_SRAT_FEATURE GetAcpiSratStub;
#define USER_SRAT_OPTION GetAcpiSratStub
#endif
/* Declare the instance of the WHEA option configuration structure */
OPTION_SRAT_CONFIGURATION OptionSratConfiguration = {
SRAT_STRUCT_VERSION,
USER_SRAT_OPTION
};
#endif // _OPTION_WHEA_INSTALL_H_

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: SW C1e
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_SW_C1E_INSTALL_H_
#define _OPTION_SW_C1E_INSTALL_H_
#include "cpuSwC1e.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_SW_C1E_FEAT
#define F10_SW_C1E_SUPPORT
#if AGESA_ENTRY_INIT_EARLY == TRUE
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
#if (OPTION_FAMILY10H_BL == TRUE) || (OPTION_FAMILY10H_DA == TRUE) || (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_PH == TRUE)
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureSwC1e;
#undef OPTION_SW_C1E_FEAT
#define OPTION_SW_C1E_FEAT &CpuFeatureSwC1e,
extern CONST SW_C1E_FAMILY_SERVICES ROMDATA F10SwC1e;
#undef F10_SW_C1E_SUPPORT
#define F10_SW_C1E_SUPPORT {(AMD_FAMILY_10_BL | AMD_FAMILY_10_DA | AMD_FAMILY_10_RB | AMD_FAMILY_10_PH), &F10SwC1e},
#endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA SwC1eFamilyServiceArray[] =
{
F10_SW_C1E_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA SwC1eFamilyServiceTable =
{
(sizeof (SwC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&SwC1eFamilyServiceArray[0]
};
#endif
#endif // _OPTION_SW_C1E_INSTALL_H_

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: WHEA
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_WHEA_INSTALL_H_
#define _OPTION_WHEA_INSTALL_H_
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#if AGESA_ENTRY_INIT_LATE == TRUE
#ifndef OPTION_WHEA
#error BLDOPT: Option not defined: "OPTION_WHEA"
#endif
#if OPTION_WHEA == TRUE
OPTION_WHEA_FEATURE GetAcpiWheaMain;
#define USER_WHEA_OPTION GetAcpiWheaMain
#else
OPTION_WHEA_FEATURE GetAcpiWheaStub;
#define USER_WHEA_OPTION GetAcpiWheaStub
#endif
#else
OPTION_WHEA_FEATURE GetAcpiWheaStub;
#define USER_WHEA_OPTION GetAcpiWheaStub
#endif
/* Declare the instance of the WHEA option configuration structure */
OPTION_WHEA_CONFIGURATION OptionWheaConfiguration = {
WHEA_STRUCT_VERSION,
USER_WHEA_OPTION
};
#endif // _OPTION_WHEA_INSTALL_H_

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src/vendorcode/amd/agesa/f12/Config/PlatformInstall.h
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src/vendorcode/amd/agesa/f12/Dispatcher.h
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/* $NoKeywords:$ */
/**
* @file
*
* AMD Pushhigh Interface
*
* Contains interface to Pushhigh entry
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Legacy
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ***************************************************************************
*/
#ifndef _DISPATCHER_H_
#define _DISPATCHER_H_
// AGESA function prototypes
AGESA_STATUS CALLCONV AmdAgesaDispatcher ( IN OUT VOID *ConfigPtr );
AGESA_STATUS CALLCONV AmdAgesaCallout ( IN UINT32 Func, IN UINTN Data, IN OUT VOID *ConfigPtr );
#endif // _DISPATCHER_H_

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src/vendorcode/amd/agesa/f12/Include/AdvancedApi.h
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/* $NoKeywords:$ */
/**
* @file
*
* Advanced API Interface for HT, Memory and CPU
*
* Contains additional declarations need to use HT, Memory and CPU Advanced interface, such as
* would be required by the basic interface implementations.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Include
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _ADVANCED_API_H_
#define _ADVANCED_API_H_
/*----------------------------------------------------------------------------
* HT FUNCTIONS PROTOTYPE
*
*----------------------------------------------------------------------------
*/
/**
* A constructor for the HyperTransport input structure.
*
* Sets inputs to valid, basic level, defaults.
*
* @param[in] StdHeader Opaque handle to standard config header
* @param[in] AmdHtInterface HT Interface structure to initialize.
*
* @retval AGESA_SUCCESS Constructors are not allowed to fail
*/
AGESA_STATUS
AmdHtInterfaceConstructor (
IN AMD_CONFIG_PARAMS *StdHeader,
IN AMD_HT_INTERFACE *AmdHtInterface
);
/**
* The top level external interface for Hypertransport Initialization.
*
* Create our initial internal state, initialize the coherent fabric,
* initialize the non-coherent chains, and perform any required fabric tuning or
* optimization.
*
* @param[in] StdHeader Opaque handle to standard config header
* @param[in] PlatformConfiguration The platform configuration options.
* @param[in] AmdHtInterface HT Interface structure.
*
* @retval AGESA_SUCCESS Only information events logged.
* @retval AGESA_ALERT Sync Flood or CRC error logged.
* @retval AGESA_WARNING Example: expected capability not found
* @retval AGESA_ERROR logged events indicating some devices may not be available
* @retval AGESA_FATAL Mixed Family or MP capability mismatch
*
*/
AGESA_STATUS
AmdHtInitialize (
IN AMD_CONFIG_PARAMS *StdHeader,
IN PLATFORM_CONFIGURATION *PlatformConfiguration,
IN AMD_HT_INTERFACE *AmdHtInterface
);
/*----------------------------------------------------------------------------
* HT Recovery FUNCTIONS PROTOTYPE
*
*----------------------------------------------------------------------------
*/
/**
* A constructor for the HyperTransport input structure.
*
*/
AGESA_STATUS
AmdHtResetConstructor (
IN AMD_CONFIG_PARAMS *StdHeader,
IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface
);
/**
* Initialize HT at Reset for both Normal and Recovery.
*
*/
AGESA_STATUS
AmdHtInitReset (
IN AMD_CONFIG_PARAMS *StdHeader,
IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface
);
/**
* Initialize the Node and Socket maps for an AP Core.
*
*/
AGESA_STATUS
AmdHtInitRecovery (
IN AMD_CONFIG_PARAMS *StdHeader
);
///----------------------------------------------------------------------------
/// MEMORY FUNCTIONS PROTOTYPE
///
///----------------------------------------------------------------------------
AGESA_STATUS
AmdMemRecovery (
IN OUT MEM_DATA_STRUCT *MemPtr
);
AGESA_STATUS
AmdMemAuto (
IN OUT MEM_DATA_STRUCT *MemPtr
);
VOID
AmdMemInitDataStructDef (
IN OUT MEM_DATA_STRUCT *MemPtr,
IN OUT PLATFORM_CONFIGURATION *PlatFormConfig
);
VOID
memDefRet ( VOID );
BOOLEAN
memDefTrue ( VOID );
BOOLEAN
memDefFalse ( VOID );
VOID
MemRecDefRet ( VOID );
BOOLEAN
MemRecDefTrue ( VOID );
#endif // _ADVANCED_API_H_

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src/vendorcode/amd/agesa/f12/Include/CommonReturns.h
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/* $NoKeywords:$ */
/**
* @file
*
* Common Return routines.
*
* Routines which do nothing, returning a result (preferably some version of zero) which
* is consistent with "do nothing" or "default". Useful for function pointer tables.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Common
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ***************************************************************************
*
*/
#ifndef _COMMON_RETURNS_H_
#define _COMMON_RETURNS_H_
/**
* Return True
*
* @retval True Default case, no special action
*/
BOOLEAN
CommonReturnTrue ( VOID );
/**
* Return False.
*
* @retval FALSE Default case, no special action
*/
BOOLEAN
CommonReturnFalse ( VOID );
/**
* Return (UINT8)zero.
*
*
* @retval zero None, or only case zero.
*/
UINT8
CommonReturnZero8 ( VOID );
/**
* Return (UINT32)zero.
*
*
* @retval zero None, or only case zero.
*/
UINT32
CommonReturnZero32 ( VOID );
/**
* Return (UINT64)zero.
*
*
* @retval zero None, or only case zero.
*/
UINT64
CommonReturnZero64 ( VOID );
/**
* Return NULL
*
* @retval NULL pointer to nothing
*/
VOID *
CommonReturnNULL ( VOID );
/**
* Return AGESA_SUCCESS.
*
* @retval AGESA_SUCCESS Success.
*/
AGESA_STATUS
CommonReturnAgesaSuccess ( VOID );
/**
* Do Nothing.
*
*/
VOID
CommonVoid ( VOID );
/**
* ASSERT if this routine is called.
*
*/
VOID
CommonAssert ( VOID );
#endif // _COMMON_RETURNS_H_

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src/vendorcode/amd/agesa/f12/Include/Filecode.h
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src/vendorcode/amd/agesa/f12/Include/GeneralServices.h
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/* $NoKeywords:$ */
/**
* @file
*
* General Services
*
* Provides Services similar to the external General Services API, except
* suited to use within AGESA components. Socket, Core and PCI identification.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Common
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _GENERAL_SERVICES_H_
#define _GENERAL_SERVICES_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
#define NUMBER_OF_EVENT_DATA_PARAMS 4
/**
* AMD Device id for MMIO check.
*/
#define AMD_DEV_VEN_ID 0x1022
#define AMD_DEV_VEN_ID_ADDRESS 0
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
/**
* An AGESA Event Log entry.
*/
typedef struct {
AGESA_STATUS EventClass; ///< The severity of the event, its associated AGESA_STATUS.
UINT32 EventInfo; ///< Uniquely identifies the event.
UINT32 DataParam1; ///< Event specific additional data
UINT32 DataParam2; ///< Event specific additional data
UINT32 DataParam3; ///< Event specific additional data
UINT32 DataParam4; ///< Event specific additional data
} AGESA_EVENT;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
/**
* Get a specified Core's APIC ID.
*
* @param[in] StdHeader Header for library and services.
* @param[in] Socket The Core's Socket.
* @param[in] Core The Core id.
* @param[out] ApicAddress The Core's APIC ID.
* @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds.
*
* @retval TRUE The core is present, APIC Id valid
* @retval FALSE The core is not present, APIC Id not valid.
*/
BOOLEAN
GetApicId (
IN AMD_CONFIG_PARAMS *StdHeader,
IN UINT32 Socket,
IN UINT32 Core,
OUT UINT8 *ApicAddress,
OUT AGESA_STATUS *AgesaStatus
);
/**
* Get Processor Module's PCI Config Space address.
*
* @param[in] StdHeader Header for library and services.
* @param[in] Socket The Core's Socket.
* @param[in] Module The Module in that Processor
* @param[out] PciAddress The Processor's PCI Config Space address (Function 0, Register 0)
* @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds.
*
* @retval TRUE The core is present, PCI Address valid
* @retval FALSE The core is not present, PCI Address not valid.
*/
BOOLEAN
GetPciAddress (
IN AMD_CONFIG_PARAMS *StdHeader,
IN UINT32 Socket,
IN UINT32 Module,
OUT PCI_ADDR *PciAddress,
OUT AGESA_STATUS *AgesaStatus
);
/**
* "Who am I" for the current running core.
*
* @param[in] StdHeader Header for library and services.
* @param[out] Socket The current Core's Socket
* @param[out] Module The current Core's Processor Module
* @param[out] Core The current Core's core id.
* @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds.
*
*/
VOID
IdentifyCore (
IN AMD_CONFIG_PARAMS *StdHeader,
OUT UINT32 *Socket,
OUT UINT32 *Module,
OUT UINT32 *Core,
OUT AGESA_STATUS *AgesaStatus
);
/**
* A boolean function determine executed CPU is BSP core.
*/
BOOLEAN
IsBsp (
IN OUT AMD_CONFIG_PARAMS *StdHeader,
OUT AGESA_STATUS *AgesaStatus
);
/**
* This function logs AGESA events into the event log.
*/
VOID
PutEventLog (
IN AGESA_STATUS EventClass,
IN UINT32 EventInfo,
IN UINT32 DataParam1,
IN UINT32 DataParam2,
IN UINT32 DataParam3,
IN UINT32 DataParam4,
IN AMD_CONFIG_PARAMS *StdHeader
);
/**
* This function gets event logs from the circular buffer.
*/
AGESA_STATUS
GetEventLog (
OUT AGESA_EVENT *EventRecord,
IN AMD_CONFIG_PARAMS *StdHeader
);
/**
* This function gets event logs from the circular buffer without flushing the entry.
*/
BOOLEAN
PeekEventLog (
OUT AGESA_EVENT *EventRecord,
IN UINT16 Index,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*---------------------------------------------------------------------------------------*/
/**
* This routine programs the registers necessary to get the PCI MMIO mechanism
* up and functioning.
*/
VOID
InitializePciMmio (
IN AMD_CONFIG_PARAMS *StdHeader
);
#endif // _GENERAL_SERVICES_H_

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src/vendorcode/amd/agesa/f12/Include/GnbInterface.h
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/* $NoKeywords:$ */
/**
* @file
*
* GNB API definition.
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: GNB
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ***************************************************************************
*
*/
#ifndef _GNBINTERFACE_H_
#define _GNBINTERFACE_H_
AGESA_STATUS
GnbInitAtReset (
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
GnbInitAtEarly (
IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr
);
AGESA_STATUS
GnbInitAtPost (
IN OUT AMD_POST_PARAMS *PostParamsPtr
);
VOID
GnbInitDataStructAtEnvDef (
IN OUT GNB_ENV_CONFIGURATION *GnbEnvConfigPtr,
IN AMD_ENV_PARAMS *EnvParamsPtr
);
AGESA_STATUS
GnbInitAtEnv (
IN AMD_ENV_PARAMS *EnvParamsPtr
);
AGESA_STATUS
GnbInitAtMid (
IN OUT AMD_MID_PARAMS *MidParamsPtr
);
AGESA_STATUS
GnbInitAtLate (
IN OUT AMD_LATE_PARAMS *LateParamsPtr
);
AGESA_STATUS
GnbInitAtPostAfterDram (
IN OUT AMD_POST_PARAMS *PostParamsPtr
);
AGESA_STATUS
AmdGnbRecovery (
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
GnbInitAtEarlier (
IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr
);
#endif

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src/vendorcode/amd/agesa/f12/Include/GnbInterfaceStub.h
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/* $NoKeywords:$ */
/**
* @file
*
*
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: GNB
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ***************************************************************************
*
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------*/
/**
* Init GNB at Reset Stub
*
*
*
* @param[in] StdHeader Standard configuration header
* @retval AGESA_SUCCESS Always succeeds
*/
AGESA_STATUS
GnbInitAtReset (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------*/
/**
* Init GNB at Early Stub
*
*
*
* @param[in,out] EarlyParamsPtr Pointer to early configuration params.
* @retval AGESA_SUCCESS Always succeeds
*/
AGESA_STATUS
GnbInitAtEarly (
IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr
)
{
return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------*/
/**
* Default constructor of GNB configuration at Env
*
*
*
* @param[in] GnbEnvConfigPtr Pointer to gnb env configuration params.
* @param[in] EnvParamsPtr Pointer to env configuration params.
*/
VOID
GnbInitDataStructAtEnvDef (
IN OUT GNB_ENV_CONFIGURATION *GnbEnvConfigPtr,
IN AMD_ENV_PARAMS *EnvParamsPtr
)
{
}
/*----------------------------------------------------------------------------------------*/
/**
* Init GNB at Env
*
*
*
* @param[in] EnvParamsPtr Pointer to env configuration params.
* @retval AGESA_SUCCESS Always succeeds
*/
AGESA_STATUS
GnbInitAtEnv (
IN AMD_ENV_PARAMS *EnvParamsPtr
)
{
return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------*/
/**
* Init GNB at Post
*
*
*
* @param[in,out] PostParamsPtr Pointer to Post configuration params.
* @retval AGESA_SUCCESS Always succeeds
*/
AGESA_STATUS
GnbInitAtPost (
IN OUT AMD_POST_PARAMS *PostParamsPtr
)
{
return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------*/
/**
* Init GNB at Mid post
*
*
*
* @param[in,out] MidParamsPtr Pointer to mid configuration params.
* @retval AGESA_SUCCESS Always succeeds
*/
AGESA_STATUS
GnbInitAtMid (
IN OUT AMD_MID_PARAMS *MidParamsPtr
)
{
return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------*/
/**
* Init GNB at Late post
*
*
*
* @param[in,out] LateParamsPtr Pointer to late configuration params.
* @retval AGESA_SUCCESS Always succeeds
*/
AGESA_STATUS
GnbInitAtLate (
IN OUT AMD_LATE_PARAMS *LateParamsPtr
)
{
return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------*/
/**
* AmdGnbRecovery
*
*
*
* @param[in] StdHeader Standard configuration header
* @retval AGESA_SUCCESS Always succeeds
*/
AGESA_STATUS
AmdGnbRecovery (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------*/
/**
* Init GNB at Post after DRAM init
*
*
*
* @param[in] PostParamsPtr Pointer to post configuration parameters
* @retval AGESA_SUCCESS Always succeeds
*/
AGESA_STATUS
GnbInitAtPostAfterDram (
IN OUT AMD_POST_PARAMS *PostParamsPtr
)
{
return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------*/
/**
* Init GNB at Early Before CPU Stub
*
*
*
* @param[in,out] EarlyParamsPtr Pointer to early configuration params.
* @retval AGESA_SUCCESS Always succeeds
*/
AGESA_STATUS
GnbInitAtEarlier (
IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr
)
{
return AGESA_SUCCESS;
}

960
src/vendorcode/amd/agesa/f12/Include/Ids.h
View File

@ -1,960 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD IDS Routines
*
* Contains AMD AGESA Integrated Debug Macros
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: IDS
* @e \$Revision: 49994 $ @e \$Date: 2011-03-31 15:44:04 +0800 (Thu, 31 Mar 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
/* Macros to aid debugging */
/* These definitions expand to zero (0) bytes of code when disabled */
#ifndef _IDS_H_
#define _IDS_H_
#undef FALSE
#undef TRUE
#define FALSE 0
#define TRUE 1
// Proto type for optionsids.h
typedef UINT32 IDS_STATUS; ///< Status of IDS function.
#define IDS_SUCCESS ((IDS_STATUS) 0x00000000) ///< IDS Function is Successful.
#define IDS_UNSUPPORTED ((IDS_STATUS) 0xFFFFFFFF) ///< IDS Function is not existed.
#define IDS_STRINGIZE(a) #a ///< for define stringize macro
/**
* IDS Option Hook Points
*
* These are the values to indicate hook point in AGESA for IDS Options.
*
*/
typedef enum { //vv- for debug reference only
IDS_INIT_EARLY_BEFORE, ///< 00 Option Hook Point before AGESA function AMD_INIT_EARLY.
///< IDS Object is initialized.
///< Override CPU Core Leveling Mode.
///< Set P-State in Post
IDS_INIT_EARLY_AFTER, ///< 01 Option Hook Point after AGESA function AMD_INIT_EARLY.
IDS_INIT_LATE_BEFORE, ///< 02 Option Hook Point before AGESA function AMD_INIT_LATE.
///< It will be used to control the following tables.
///< ACPI P-State Table (_PSS, XPSS, _PCT, _PSD, _PPC)
///< ACPI SRAT Table
///< ACPI SLIT Table
///< ACPI WHEA Table
///< DMI Table
IDS_INIT_LATE_AFTER, ///< 03 Option Hook Point after AGESA function AMD_INIT_LATE.
IDS_INIT_MID_BEFORE, ///< 04 Option Hook Point before AGESA function AMD_INIT_MID.
IDS_INIT_MID_AFTER, ///< 05 Option Hook Point after AGESA function AMD_INIT_MID.
IDS_INIT_POST_BEFORE, ///< 06 Option Hook Point before AGESA function AMD_INIT_POST.
///< Control Interleaving and DRAM memory hole
///< Override the setting of ECC Control
///< Override the setting of Online Spare Rank
IDS_INIT_POST_AFTER, ///< 07 Option Hook Point after AGESA function AMD_INIT_POST.
IDS_INIT_RESET_BEFORE, ///< 08 Option Hook Point before AGESA function AMD_INIT_RESET.
IDS_INIT_RESET_AFTER, ///< 09 Option Hook Point after AGESA function AMD_INIT_RESET.
IDS_INIT_POST_MID, ///< 0a Option Hook Point after AGESA function AMD_INIT_POST.
IDS_BEFORE_S3_SAVE, ///< 0b override any settings before S3 save.
IDS_BEFORE_S3_RESTORE, ///< 0c override any settings before S3 restore
IDS_AFTER_S3_SAVE, ///< 0d Override any settings after S3 save
IDS_AFTER_S3_RESTORE, ///< 0e Override any settings after S3 restore
IDS_BEFORE_DQS_TRAINING, ///< 0f override any settings before DQS training
IDS_BEFORE_DRAM_INIT, ///< 10 override any settings before Dram initialization
IDS_BEFORE_MEM_FREQ_CHG, ///< 11 override settings before MemClk frequency change
IDS_BEFORE_WARM_RESET , ///< 12 Override PCI or MSR Registers Before Warm Reset
IDS_BEFORE_MEM_INIT, ///< 13 Override PCI or MSR Registers Before Memory Init
IDS_BEFORE_PCI_INIT, ///< 14 Override PCI or MSR Registers Before PCI Init
IDS_BEFORE_OS, ///< 15 Override PCI or MSR Registers Before booting to OS
IDS_UCODE, ///< 16 Enable or Disable microcode patching
IDS_BEFORE_AP_EARLY_HALT, ///< 17 Option Hook Point before AP early halt
IDS_BEFORE_S3_RESUME, ///< 18 Option Hook Point before s3 resume
IDS_AFTER_S3_RESUME, ///< 19 Option Hook Point after s3 resume
IDS_BEFORE_PM_INIT, ///< 20 Option Hook Point Before Pm Init
IDS_PLATFORM_RSVD1 = 0x38, ///< from 0x38 to 0x3f will reserved for platform used
IDS_PLATFORM_RSVD2 = 0x39, ///< from 0x38 to 0x3f will reserved for platform used
IDS_PLATFORM_RSVD3 = 0x3a, ///< from 0x38 to 0x3f will reserved for platform used
IDS_PLATFORM_RSVD4 = 0x3b, ///< from 0x38 to 0x3f will reserved for platform used
IDS_PLATFORM_RSVD5 = 0x3c, ///< from 0x38 to 0x3f will reserved for platform used
IDS_PLATFORM_RSVD6 = 0x3d, ///< from 0x38 to 0x3f will reserved for platform used
IDS_PLATFORM_RSVD7 = 0x3e, ///< from 0x38 to 0x3f will reserved for platform used
IDS_PLATFORM_RSVD8 = 0x3f, ///< from 0x38 to 0x3f will reserved for platform used
// All the above timing point is used by BVM, their value should never be changed
IDS_HT_CONTROL, ///< 40 Override the setting of HT Link Control
IDS_HT_TRISTATE, ///< 41 Enable or Disable HT Tri-state during an LDTSTP#
IDS_INIT_DRAM_TABLE, ///< 42 Generate override table for Dram Timing
///< Dram Controller, Drive Strength and DQS Timing
IDS_GET_DRAM_TABLE, ///< 43 Generate override table for Dram Timing
IDS_GANGING_MODE, ///< 44 override Memory Mode Unganged
IDS_POWERDOWN_MODE, ///< 45 override Power Down Mode
IDS_BURST_LENGTH32, ///< 46 override Burst Length32
IDS_ALL_MEMORY_CLOCK, ///< 47 override All Memory Clks Enable
IDS_ECC, ///< 48 override ECC parameter
IDS_ECCSYMBOLSIZE, ///< 49 override ECC symbol size
IDS_CPU_Early_Override, ///< 4a override CPU early parameter
IDS_CACHE_FLUSH_HLT, ///< 4b override Cache Flush Hlt
IDS_CHANNEL_INTERLEAVE, ///< 4c override Channel Interleave
IDS_MEM_ERROR_RECOVERY, ///< 4d override memory error recovery
IDS_MEM_RETRAIN_TIMES, ///< 4e override memory retrain times
IDS_MEM_SIZE_OVERLAY, ///< 4f Override the syslimit
IDS_HT_ASSIST, ///< 50 Override Probe Filter
IDS_CHECK_NEGATIVE_WL, ///< 51 Check for negative write leveling result
IDS_DLL_SHUT_DOWN, ///< 52 Check for Dll Shut Down
IDS_POR_MEM_FREQ, ///< 53 Entry to enable/disable MemClk frequency enforcement
IDS_PHY_DLL_STANDBY_CTRL, ///< 54 Enable/Disable Phy DLL standby feature
IDS_PLATFORMCFG_OVERRIDE, ///< 55 Hook for Override PlatformConfig structure
IDS_LOADCARD_ERROR_RECOVERY, ///< 56 Special error handling for load card support
IDS_MEM_IGNORE_ERROR, ///< 57 Ignore error and do not do fatal exit in memory
IDS_GNB_SMU_SERVICE_CONFIG, ///< 58 Config GNB SMU service
IDS_GNB_ORBDYNAMIC_WAKE, ///< 59 config GNB dynamic wake
IDS_GNB_PLATFORMCFG_OVERRIDE, ///< 5a override ids gnb platform config
IDS_GNB_LCLK_DPM_EN, ///< 5b override GNB LCLK DPM configuration
IDS_GNB_LCLK_DEEP_SLEEP, ///< 5c override GNB LCLK DPM deep sleep
IDS_GNB_CLOCK_GATING, ///< 5d Override GNB Clock gating config
IDS_NB_PSTATE_DIDVID, ///< 5e Override NB P-state settings
IDS_CPB_CTRL, ///< 5f Config the Core peformance boost feature
IDS_HTC_CTRL, ///< 60 Hook for Hardware Thermal Control
IDS_CC6_WORKAROUND, ///< 61 Hook for skip CC6 work around
IDS_MEM_MR0, ///< 62 Hook for override Memory Mr0 register
IDS_REG_TABLE, ///< 63 Hook for add IDS register table to the loop
IDS_NBBUFFERALLOCATIONATEARLY, ///< 64 Hook for override North bridge bufer allocation
IDS_BEFORE_S3_SPECIAL, ///< 65 Hook to bypass S3 special functions
IDS_SET_PCI_REGISTER_ENTRY, ///< 66 Hook to SetRegisterForPciEntry
IDS_ERRATUM463_WORKAROUND, ///< 67 Hook to Erratum 463 workaround
IDS_BEFORE_MEMCLR, ///< 68 Hook before set Memclr bit
IDS_OVERRIDE_IO_CSTATE, ///< 69 Hook for override io C-state setting
IDS_NBPSDIS_OVERRIDE, ///< 6a Hook for override NB pstate disable setting
IDS_NBPS_REG_OVERRIDE, ///< 6b Hook for override Memory NBps reg
IDS_LOW_POWER_PSTATE, ///< 6c Hook for disalbe Low power_Pstates feature
IDS_CST_CREATE, ///< 6d Hook for create _CST
IDS_CST_SIZE, ///< 6e Hook for get _CST size
IDS_ENFORCE_VDDIO, ///< 6f Hook to override VDDIO
IDS_SKIP_PERFORMANCE_OPT, ///< 70 Hook to skip performance optimization
IDS_INIT_MEM_REG_TABLE, ///< 71 Hook for init memory register table
IDS_SKIP_FUSED_MAX_RATE, ///< 72 Hook to skip fused max rate cap
IDS_FCH_INIT_AT_RESET, ///< 73 Hook for FCH reset parameter
IDS_FCH_INIT_AT_ENV, ///< 74 Hook for FCH ENV parameter
IDS_ENFORCE_PLAT_TABLES, ///< 75 Hook to enforce platform specific tables
IDS_NBPS_MIN_FREQ, ///< 76 Hook for override MIN nb ps freq
IDS_GNB_FORCE_CABLESAFE, ///< 77 Hook for override Force Cable Safe
IDS_SKIP_PM_TRANSITION_STEP, ///< 78 Hook for provide IDS ability to skip this PM step
IDS_GNB_PROPERTY, ///< 79 Hook for GNB Property
IDS_GNB_PCIE_POWER_GATING, ///< 7A Hook for GNB PCIe Power Gating
IDS_MEM_DYN_DRAM_TERM, ///< 7B Hook for Override Dynamic Dram Term
IDS_MEM_DRAM_TERM, ///< 7C Hook for Override Dram Term
IDS_TRACE_MODE, ///< 7D Trace Mode
IDS_GNB_ALTVDDNB, ///< 7E Hook for Override AltVddNB
} AGESA_IDS_OPTION;
#include "OptionsIds.h"
#include "Filecode.h"
/* Initialize IDS controls */
#ifndef IDSOPT_IDS_ENABLED
#define IDSOPT_IDS_ENABLED FALSE
#endif
#ifndef IDSOPT_CONTROL_ENABLED
#define IDSOPT_CONTROL_ENABLED FALSE
#endif
#ifndef IDSOPT_CONTROL_NV_TO_CMOS
#define IDSOPT_CONTROL_NV_TO_CMOS FALSE
#endif
#ifndef IDSOPT_TRACING_ENABLED
#define IDSOPT_TRACING_ENABLED FALSE
#endif
#ifndef IDSOPT_TRACE_USER_OPTIONS
#define IDSOPT_TRACE_USER_OPTIONS TRUE
#endif
#ifndef IDSOPT_PERF_ANALYSIS
#define IDSOPT_PERF_ANALYSIS FALSE
#endif
#ifndef IDSOPT_HEAP_CHECKING
#define IDSOPT_HEAP_CHECKING FALSE
#endif
#ifndef IDSOPT_ASSERT_ENABLED
#define IDSOPT_ASSERT_ENABLED FALSE
#endif
#ifndef IDSOPT_ERROR_TRAP_ENABLED
#define IDSOPT_ERROR_TRAP_ENABLED FALSE
#endif
#ifndef IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
#define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE
#endif
#ifndef IDSOPT_DEBUG_CODE_ENABLED
#define IDSOPT_DEBUG_CODE_ENABLED FALSE
#endif
#ifndef IDSOPT_IDT_EXCEPTION_TRAP
#define IDSOPT_IDT_EXCEPTION_TRAP FALSE
#endif
#ifndef IDSOPT_C_OPTIMIZATION_DISABLED
#define IDSOPT_C_OPTIMIZATION_DISABLED FALSE
#endif
#if IDSOPT_IDS_ENABLED == FALSE
#undef IDSOPT_CONTROL_ENABLED
#undef IDSOPT_TRACING_ENABLED
#undef IDSOPT_PERF_ANALYSIS
#undef IDSOPT_HEAP_CHECKING
#undef IDSOPT_ASSERT_ENABLED
#undef IDSOPT_ERROR_TRAP_ENABLED
#undef IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
#undef IDSOPT_DEBUG_CODE_ENABLED
#undef IDSOPT_TRACE_USER_OPTIONS
#define IDSOPT_CONTROL_ENABLED FALSE
#define IDSOPT_TRACING_ENABLED FALSE
#define IDSOPT_PERF_ANALYSIS FALSE
#define IDSOPT_HEAP_CHECKING FALSE
#define IDSOPT_ASSERT_ENABLED FALSE
#define IDSOPT_ERROR_TRAP_ENABLED FALSE
#define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE
#define IDSOPT_DEBUG_CODE_ENABLED FALSE
#define IDSOPT_TRACE_USER_OPTIONS FALSE
#endif
/**
* Make a Progress Report to the User.
*
* This Macro is always enabled. The default action is to write the TestPoint value
* to an I/O port. The I/O port is 8 bits in size and the default address is 0x80.
* IBVs can change AGESA's default port by defining IDS_DEBUG_PORT to desired port
* in OptionsIds.h in their build tip.
*
* @param[in] TestPoint The value for display indicating progress
* @param[in,out] StdHeader Pointer of AMD_CONFIG_PARAMS
*
**/
#define AGESA_TESTPOINT(TestPoint, StdHeader)
#ifndef IDS_DEBUG_PORT
#define IDS_DEBUG_PORT 0x80
#endif
/**
* @def STOP_HERE
* (macro) - Causes program to halt. This is @b only for use during active debugging .
*
* Causes the program to halt and display the file number of the source of the
* halt (displayed in decimal).
*
**/
#if IDSOPT_IDS_ENABLED == TRUE
#ifdef STOP_CODE
#undef STOP_CODE
#endif
#define STOP_CODE (((UINT32)FILECODE)*0x10000 + \
((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
(((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
#define STOP_HERE
#else
#define STOP_HERE
#endif
/**
* @def ASSERT
* Test an assertion that the given statement is True.
*
* The statement is evaluated to a boolean value. If the statement is True,
* then no action is taken (no error). If the statement is False, a error stop
* is generated to halt the program. Used for testing for fatal errors that
* must be resolved before production. This is used to do parameter checks,
* bounds checking, range checks and 'sanity' checks.
*
* @param[in] conditional Assert that evaluating this conditional results in TRUE.
*
**/
#ifndef ASSERT
#if IDSOPT_ASSERT_ENABLED == TRUE
#ifdef STOP_CODE
#undef STOP_CODE
#endif
#define STOP_CODE (((UINT32)FILECODE)*0x10000 + \
((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
(((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
#define ASSERT(conditional)
#else
#define ASSERT(conditional)
#endif
#endif
#if IDSOPT_CAR_CORRUPTION_CHECK_ENABLED == TRUE
#undef IDSOPT_ERROR_TRAP_ENABLED
#define IDSOPT_ERROR_TRAP_ENABLED TRUE
#define IDS_CAR_CORRUPTION_CHECK(StdHeader)
#else
#define IDS_CAR_CORRUPTION_CHECK(StdHeader)
#endif
/**
* @def DEBUG_CODE
* Make the code active when IDSOPT_DEBUG_CODE_ENABLED enable
*
*/
#ifndef DEBUG_CODE
#if IDSOPT_DEBUG_CODE_ENABLED == TRUE
#define DEBUG_CODE(Code)
#else
#define DEBUG_CODE(Code)
#endif
#endif
/**
* @def IDS_ERROR_TRAP
* Trap AGESA Error events with stop code display.
*
* Works similarly to use of "ASSERT (FALSE);"
*
*/
#if IDSOPT_ERROR_TRAP_ENABLED == TRUE
#ifdef STOP_CODE
#undef STOP_CODE
#endif
#define STOP_CODE (((UINT32)FILECODE)*0x10000 + \
((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
(((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
#define IDS_ERROR_TRAP
#else
#define IDS_ERROR_TRAP
#endif
///give the extended Macro default value
#ifndef __IDS_EXTENDED__
#define IDS_EXTENDED_HOOK(idsoption, dataptr, idsnvptr, stdheader) IDS_SUCCESS
#define IDS_INITIAL_F10_PM_STEP
#define IDS_INITIAL_F12_PM_STEP
#define IDS_INITIAL_F14_PM_STEP
#define IDS_INITIAL_F15_PM_STEP
#define IDS_EXTENDED_GET_DATA_EARLY(data, StdHeader)
#define IDS_EXTENDED_GET_DATA_LATE(data, StdHeader)
#define IDS_EXTENDED_HEAP_SIZE 0
#define IDS_EXT_INCLUDE_F10(file)
#define IDS_EXT_INCLUDE_F12(file)
#define IDS_EXT_INCLUDE_F14(file)
#define IDS_EXT_INCLUDE_F15(file)
#define IDS_EXT_INCLUDE(file)
#endif
#ifndef IDS_NUM_NV_ITEM
#define IDS_NUM_NV_ITEM (IDS_NUM_EXT_NV_ITEM)
#endif
#if IDSOPT_CONTROL_ENABLED == TRUE
#define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader)
#define IDS_OPTION_CALLOUT(CallOutId, DataPtr, StdHeader)
#else
#define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader)
#define IDS_OPTION_CALLOUT(CallOutId, DataPtr, StdHeader)
#endif
/**
* Macro to add a *skip* hook for IDS options
*
* The default minimal action is to do nothing and there is no any code to increase.
* For debug environments, IDS dispatcher function will be called to perform
* the detailed action and to skip AGESA code if necessary.
*
* @param[in] IdsOption IDS Option ID for this hook point
* @param[in, out] DataPtr Data Pointer to override
* @param[in, out] StdHeader Pointer of AMD_CONFIG_PARAMS
*
*
**/
#if IDSOPT_CONTROL_ENABLED == TRUE
#define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader)
#else
#define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader)
#endif
/**
* Macro to add a heap manager routine
*
* when memory is allocated the heap manager actually allocates two extra dwords of data,
* one dword buffer before the actual memory, and one dword afterwards.
* a complete heap walk and check to be performed at any time.
* it would ASSERT if the heap is corrupt
*
* @param[in] StdHeader Pointer of AMD_CONFIG_PARAMS
*
*
**/
// Heap debug feature
#define SENTINEL_BEFORE_VALUE 0x64616548 // "Head"
#define SENTINEL_AFTER_VALUE 0x6C696154 // "Tail"
#if IDSOPT_IDS_ENABLED == TRUE
#if IDSOPT_HEAP_CHECKING == TRUE
#define SIZE_OF_SENTINEL 0
#define NUM_OF_SENTINEL 0
#define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte)
#define SET_SENTINEL_AFTER(NodePtr)
#define Heap_Check(stdheader)
#else
#define SIZE_OF_SENTINEL 0
#define NUM_OF_SENTINEL 0
#define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte)
#define SET_SENTINEL_AFTER(NodePtr)
#define Heap_Check(stdheader)
#endif
#else
#define SIZE_OF_SENTINEL 0
#define NUM_OF_SENTINEL 0
#define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte)
#define SET_SENTINEL_AFTER(NodePtr)
#define Heap_Check(stdheader)
#endif
//Note a is from 0 to 63
#define DEBUG_PRINT_SHIFT(a) ((UINT64)1 << a)
//If you change the Bitmap definition below, please change the Hash in ParseFilter of hdtout2008.pl accordingly
//Memory Masks
#define MEM_SETREG DEBUG_PRINT_SHIFT (0)
#define MEM_GETREG DEBUG_PRINT_SHIFT (1)
#define MEM_FLOW DEBUG_PRINT_SHIFT (2)
#define MEM_STATUS DEBUG_PRINT_SHIFT (3)
#define MEMORY_TRACE_RSV1 DEBUG_PRINT_SHIFT (4)
#define MEMORY_TRACE_RSV2 DEBUG_PRINT_SHIFT (5)
#define MEMORY_TRACE_RSV3 DEBUG_PRINT_SHIFT (6)
#define MEMORY_TRACE_RSV4 DEBUG_PRINT_SHIFT (7)
#define MEMORY_TRACE_RSV5 DEBUG_PRINT_SHIFT (8)
#define MEMORY_TRACE_RSV6 DEBUG_PRINT_SHIFT (9)
//CPU Masks
#define CPU_TRACE DEBUG_PRINT_SHIFT (10)
#define CPU_TRACE_RSV1 DEBUG_PRINT_SHIFT (11)
#define CPU_TRACE_RSV2 DEBUG_PRINT_SHIFT (12)
#define CPU_TRACE_RSV3 DEBUG_PRINT_SHIFT (13)
#define CPU_TRACE_RSV4 DEBUG_PRINT_SHIFT (14)
#define CPU_TRACE_RSV5 DEBUG_PRINT_SHIFT (15)
#define CPU_TRACE_RSV6 DEBUG_PRINT_SHIFT (16)
#define CPU_TRACE_RSV7 DEBUG_PRINT_SHIFT (17)
#define CPU_TRACE_RSV8 DEBUG_PRINT_SHIFT (18)
#define CPU_TRACE_RSV9 DEBUG_PRINT_SHIFT (19)
//GNB Masks
#define GNB_TRACE DEBUG_PRINT_SHIFT (20)
#define PCIE_MISC DEBUG_PRINT_SHIFT (21)
#define PCIE_PORTREG_TRACE DEBUG_PRINT_SHIFT (22)
#define PCIE_HOSTREG_TRACE DEBUG_PRINT_SHIFT (23)
#define GNB_TRACE_RSV2 DEBUG_PRINT_SHIFT (24)
#define NB_MISC DEBUG_PRINT_SHIFT (25)
#define GNB_TRACE_RSV3 DEBUG_PRINT_SHIFT (26)
#define GFX_MISC DEBUG_PRINT_SHIFT (27)
#define NB_SMUREG_TRACE DEBUG_PRINT_SHIFT (28)
#define GNB_TRACE_RSV1 DEBUG_PRINT_SHIFT (29)
//HT Masks
#define HT_TRACE DEBUG_PRINT_SHIFT (30)
#define HT_TRACE_RSV1 DEBUG_PRINT_SHIFT (31)
#define HT_TRACE_RSV2 DEBUG_PRINT_SHIFT (32)
#define HT_TRACE_RSV3 DEBUG_PRINT_SHIFT (33)
#define HT_TRACE_RSV4 DEBUG_PRINT_SHIFT (34)
#define HT_TRACE_RSV5 DEBUG_PRINT_SHIFT (35)
#define HT_TRACE_RSV6 DEBUG_PRINT_SHIFT (36)
#define HT_TRACE_RSV7 DEBUG_PRINT_SHIFT (37)
#define HT_TRACE_RSV8 DEBUG_PRINT_SHIFT (38)
#define HT_TRACE_RSV9 DEBUG_PRINT_SHIFT (39)
//FCH Masks
#define FCH_TRACE DEBUG_PRINT_SHIFT (40)
#define FCH_TRACE_RSV1 DEBUG_PRINT_SHIFT (41)
#define FCH_TRACE_RSV2 DEBUG_PRINT_SHIFT (42)
#define FCH_TRACE_RSV3 DEBUG_PRINT_SHIFT (43)
#define FCH_TRACE_RSV4 DEBUG_PRINT_SHIFT (44)
#define FCH_TRACE_RSV5 DEBUG_PRINT_SHIFT (45)
#define FCH_TRACE_RSV6 DEBUG_PRINT_SHIFT (46)
#define FCH_TRACE_RSV7 DEBUG_PRINT_SHIFT (47)
#define FCH_TRACE_RSV8 DEBUG_PRINT_SHIFT (48)
#define FCH_TRACE_RSV9 DEBUG_PRINT_SHIFT (49)
//Other Masks
#define MAIN_FLOW DEBUG_PRINT_SHIFT (50)
#define EVENT_LOG DEBUG_PRINT_SHIFT (51)
#define PERFORMANCE_ANALYSE DEBUG_PRINT_SHIFT (52)
//Ids Masks
#define IDS_TRACE DEBUG_PRINT_SHIFT (53)
#define IDS_REG DEBUG_PRINT_SHIFT (54)
#define IDS_TRACE_RSV2 DEBUG_PRINT_SHIFT (55)
#define IDS_TRACE_RSV3 DEBUG_PRINT_SHIFT (56)
//S3
#define S3_TRACE DEBUG_PRINT_SHIFT (57)
//Library function to read/write PCI/MSR registers
#define LIB_PCI_RD DEBUG_PRINT_SHIFT (58)
#define LIB_PCI_WR DEBUG_PRINT_SHIFT (59)
//Reserved
#define TRACE_RSV3 DEBUG_PRINT_SHIFT (60)
#define TRACE_RSV4 DEBUG_PRINT_SHIFT (61)
#define TRACE_RSV5 DEBUG_PRINT_SHIFT (62)
#define TRACE_RSV6 DEBUG_PRINT_SHIFT (63)
#define GNB_TRACE_DEFAULT 0
#define GNB_TRACE_REG 0
#define GNB_TRACE_ALL 0
#define CPU_TRACE_ALL 0
#define MEMORY_TRACE_ALL 0
#define HT_TRACE_ALL 0
#define FCH_TRACE_ALL 0
#define IDS_TRACE_ALL 0
#define OTHER_TRACE_ALL 0
#define TRACE_MASK_ALL (0ull)
#ifndef IDS_DEBUG_PRINT_MASK
#define IDS_DEBUG_PRINT_MASK 0
#endif
/**
* Macro to add HDT OUT
*
* The default minimal action is to do nothing and there is no any code to increase.
* For debug environments, the debug information can be displayed in HDT or other
* devices.
*
**/
#if IDSOPT_IDS_ENABLED == TRUE
#if IDSOPT_TRACING_ENABLED == TRUE
#define IDS_HDT_CONSOLE_INIT(x)
#define IDS_HDT_CONSOLE_EXIT(x)
#define IDS_HDT_CONSOLE_S3_EXIT(x)
#define IDS_HDT_CONSOLE_S3_AP_EXIT(x)
#if IDSOPT_C_OPTIMIZATION_DISABLED == TRUE
#ifdef __GNUC__
#define IDS_HDT_CONSOLE(f, s, ...)
#else
#define IDS_HDT_CONSOLE(f, s, ...)
#endif
#else
#pragma warning(disable: 4127)
#ifdef __GNUC__
#define IDS_HDT_CONSOLE(f, s, ...)
#else
#define IDS_HDT_CONSOLE(f, s, ...)
#endif
#endif
#define IDS_HDT_CONSOLE_FLUSH_BUFFER(x)
#define IDS_HDT_CONSOLE_ASSERT(x)
#define IDS_FUNCLIST_ADDR NULL
#define IDS_FUNCLIST_EXTERN()
#define IDS_TIMEOUT_CTL(t)
#define IDS_HDT_CONSOLE_DEBUG_CODE(Code)
#define CONSOLE(s, ...)
#else
#define IDS_HDT_CONSOLE_INIT(x)
#define IDS_HDT_CONSOLE_EXIT(x)
#define IDS_HDT_CONSOLE_S3_EXIT(x)
#define IDS_HDT_CONSOLE_S3_AP_EXIT(x)
#define IDS_HDT_CONSOLE(f, s, ...)
#define IDS_HDT_CONSOLE_FLUSH_BUFFER(x)
#define IDS_HDT_CONSOLE_ASSERT(x)
#define IDS_FUNCLIST_ADDR NULL
#define IDS_FUNCLIST_EXTERN()
#define IDS_TIMEOUT_CTL(t)
#define IDS_HDT_CONSOLE_DEBUG_CODE(Code)
#define CONSOLE(s, ...)
#endif
#else
#define IDS_HDT_CONSOLE_INIT(x)
#define IDS_HDT_CONSOLE_EXIT(x)
#define IDS_HDT_CONSOLE_S3_EXIT(x)
#define IDS_HDT_CONSOLE_S3_AP_EXIT(x)
#define IDS_HDT_CONSOLE(f, s, ...)
#define IDS_HDT_CONSOLE_FLUSH_BUFFER(x)
#define IDS_HDT_CONSOLE_ASSERT(x)
#define IDS_FUNCLIST_ADDR NULL
#define IDS_FUNCLIST_EXTERN()
#define IDS_TIMEOUT_CTL(t)
#define IDS_HDT_CONSOLE_DEBUG_CODE(Code)
#define CONSOLE(s, ...)
#endif
#define IDS_TRACE_SHOW_BLD_OPT_CFG IDSOPT_TRACE_USER_OPTIONS
#if IDSOPT_PERF_ANALYSIS == TRUE
#define IDS_PERF_TIMESTAMP(StdHeader, TestPoint)
#define IDS_PERF_ANALYSE(StdHeader)
#define IDS_PERF_TIME_MEASURE(StdHeader)
#else
#define IDS_PERF_TIMESTAMP(StdHeader, TestPoint)
#define IDS_PERF_ANALYSE(StdHeader)
#define IDS_PERF_TIME_MEASURE(StdHeader)
#endif
///For IDS feat use
#define IDS_FAMILY_ALL 0x0ull
#define IDS_BSP_ONLY TRUE
#define IDS_ALL_CORES FALSE
#define IDS_LATE_RUN_AP_TASK_ID PROC_IDS_CONTROL_IDSLIB_FILECODE
#define IDS_CALLOUT_INIT 0x00 ///< The function data of IDS callout function of initialization.
#define IDS_CALLOUT_GNB_PPFUSE_OVERRIDE 0x00 ///< The function data of IDS callout function of GNB pp fuse table.
#define IDS_CALLOUT_GNB_INTEGRATED_TABLE_CONFIG 0x00 ///< The function data of IDS callout function of GNB integrated table.
#define IDS_CALLOUT_GNB_NB_POWERGATE_CONFIG 0x00 ///< The function data of IDS callout function of GNB NB power gate config.
#define IDS_CALLOUT_GNB_PCIE_POWERGATE_CONFIG 0x00 ///< The function data of IDS callout function of GNB PCIE power gateconfig.
#define IDS_CALLOUT_GNB_PCIE_PLATFORM_CONFIG 0x00 ///< The function data of IDS callout function of GNB pcie platform config.
#define IDS_CALLOUT_GNB_PCIE_PHY_CONFIG 0x00 ///< The function data of IDS callout function of GNB pcie PHY config.
#define IDS_CALLOUT_GNB_GMM_REGISTER_OVERRIDE 0x00 ///< The function data of IDS callout function of GNB GMM register override
#define IDS_CALLOUT_MTC1E_PLATFORM_CONFIG 0x00 ///< The function data of IDS callout function of Message Triggered C1e platform config.
#define IDS_CALLOUT_FCH_INIT_RESET 0x00 ///< The function data of IDS callout function of FchInitReset
#define IDS_CALLOUT_FCH_INIT_ENV 0x00 ///< The function data of IDS callout function of FchInitEnv.
/// Function entry for HDT script to call
typedef struct _SCRIPT_FUNCTION {
UINTN FuncAddr; ///< Function address in ROM
CHAR8 FuncName[40]; ///< Function name
} SCRIPT_FUNCTION;
/// Data Structure for Mem ECC parameter override
typedef struct {
IN BOOLEAN CfgEccRedirection; ///< ECC Redirection
IN UINT16 CfgScrubDramRate; ///< Scrub Dram Rate
IN UINT16 CfgScrubL2Rate; ///< Scrub L2Rate
IN UINT16 CfgScrubL3Rate; ///< Scrub L3Rate
IN UINT16 CfgScrubIcRate; ///< Scrub Ic Rate
IN UINT16 CfgScrubDcRate; ///< Scrub Dc Rate
IN BOOLEAN CfgEccSyncFlood; ///< ECC Sync Flood
} ECC_OVERRIDE_STRUCT;
/**
* AGESA Test Points
*
* These are the values displayed to the user to indicate progress through boot.
* These can be used in a debug environment to stop the debugger at a specific
* test point:
* For SimNow!, this command
* bi 81 w vb 49
* will stop the debugger on one of the TracePoints (49 is the TP value in this example).
*
*/
typedef enum {
StartProcessorTestPoints, ///< 00 Entry used for range testing for @b Processor related TPs
// Memory test points
TpProcMemBeforeMemDataInit, ///< 01 .. Memory structure initialization (Public interface)
TpProcMemBeforeSpdProcessing, ///< 02 .. SPD Data processing (Public interface)
TpProcMemAmdMemAuto, ///< 03 .. Memory configuration (Public interface)
TpProcMemDramInit, ///< 04 .. DRAM initialization
TpProcMemSPDChecking, ///< 05 ..
TpProcMemModeChecking, ///< 06 ..
TpProcMemSpeedTclConfig, ///< 07 .. Speed and TCL configuration
TpProcMemSpdTiming, ///< 08 ..
TpProcMemDramMapping, ///< 09 ..
TpProcMemPlatformSpecificConfig, ///< 0A ..
TPProcMemPhyCompensation, ///< 0B ..
TpProcMemStartDcts, ///< 0C ..
TpProcMemBeforeDramInit, ///< 0D .. (Public interface)
TpProcMemPhyFenceTraining, ///< 0E ..
TpProcMemSynchronizeDcts, ///< 0F ..
TpProcMemSystemMemoryMapping, ///< 10 ..
TpProcMemMtrrConfiguration, ///< 11 ..
TpProcMemDramTraining, ///< 12 ..
TpProcMemBeforeAnyTraining, ///< 13 .. (Public interface)
TpProcMemWriteLevelizationTraining, ///< 14 ..
TpProcMemWlFirstPass, ///< 15 .. Below 800Mhz first pass start
TpProcMemWlSecondPass, ///< 16 .. Above 800Mhz second pass start
TpProcMemWlTrainTargetDimm, ///< 17 .. Target DIMM configured
TpProcMemWlPrepDimms, ///< 18 .. Prepare DIMMS for WL
TpProcMemWlConfigDimms, ///< 19 .. Configure DIMMS for WL
TpProcMemReceiverEnableTraining, ///< 1A ..
TpProcMemRcvrStartSweep, ///< 1B .. Start sweep loop
TpProcMemRcvrSetDelay, ///< 1C .. Set receiver Delay
TpProcMemRcvrWritePattern, ///< 1D .. Write test pattern
TpProcMemRcvrReadPattern, ///< 1E .. Read test pattern
TpProcMemRcvrTestPattern, ///< 1F .. Compare test pattern
TpProcMemRcvrCalcLatency, ///< 20 .. Calculate MaxRdLatency per channel
TpProcMemReceiveDqsTraining, ///< 21 ..
TpProcMemRcvDqsSetDelay, ///< 22 .. Set Write Data delay
TpProcMemRcvDqsWritePattern, ///< 23 .. Write test pattern
TpProcMemRcvDqsStartSweep, ///< 24 .. Start read sweep
TpProcMemRcvDqsSetRcvDelay, ///< 25 .. Set Receive DQS delay
TpProcMemRcvDqsReadPattern, ///< 26 .. Read Test pattern
TpProcMemRcvDqsTstPattern, ///< 27 .. Compare Test pattern
TpProcMemRcvDqsResults, ///< 28 .. Update results
TpProcMemRcvDqsFindWindow, ///< 29 .. Start Find passing window
TpProcMemTransmitDqsTraining, ///< 2A ..
TpProcMemTxDqStartSweep, ///< 2B .. Start write sweep
TpProcMemTxDqSetDelay, ///< 2C .. Set Transmit DQ delay
TpProcMemTxDqWritePattern, ///< 2D .. Write test pattern
TpProcMemTxDqReadPattern, ///< 2E .. Read Test pattern
TpProcMemTxDqTestPattern, ///< 2F .. Compare Test pattern
TpProcMemTxDqResults, ///< 30 .. Update results
TpProcMemTxDqFindWindow, ///< 31 .. Start Find passing window
TpProcMemMaxRdLatencyTraining, ///< 32 ..
TpProcMemMaxRdLatStartSweep, ///< 33 .. Start sweep
TpProcMemMaxRdLatSetDelay, ///< 34 .. Set delay
TpProcMemMaxRdLatWritePattern, ///< 35 .. Write test pattern
TpProcMemMaxRdLatReadPattern, ///< 36 .. Read Test pattern
TpProcMemMaxRdLatTestPattern, ///< 37 .. Compare Test pattern
TpProcMemOnlineSpareInit, ///< 38 .. Online Spare init
TpProcMemBankInterleaveInit, ///< 39 .. Bank Interleave Init
TpProcMemNodeInterleaveInit, ///< 3A .. Node Interleave Init
TpProcMemChannelInterleaveInit, ///< 3B .. Channel Interleave Init
TpProcMemEccInitialization, ///< 3C .. ECC initialization
TpProcMemPlatformSpecificInit, ///< 3D .. Platform Specific Init
TpProcMemBeforeAgesaReadSpd, ///< 3E .. Before callout for "AgesaReadSpd"
TpProcMemAfterAgesaReadSpd, ///< 3F .. After callout for "AgesaReadSpd"
TpProcMemBeforeAgesaHookBeforeDramInit, ///< 40 .. Before optional callout "AgesaHookBeforeDramInit"
TpProcMemAfterAgesaHookBeforeDramInit, ///< 41 .. After optional callout "AgesaHookBeforeDramInit"
TpProcMemBeforeAgesaHookBeforeDQSTraining, ///< 42 .. Before optional callout "AgesaHookBeforeDQSTraining"
TpProcMemAfterAgesaHookBeforeDQSTraining, ///< 43 .. After optional callout "AgesaHookBeforeDQSTraining"
TpProcMemBeforeAgesaHookBeforeExitSelfRef, ///< 44 .. Before optional callout "AgesaHookBeforeDramInit"
TpProcMemAfterAgesaHookBeforeExitSelfRef, ///< 45 .. After optional callout "AgesaHookBeforeDramInit"
TpProcMemAfterMemDataInit, ///< 46 .. After MemDataInit
TpProcMemInitializeMCT, ///< 47 .. Before InitializeMCT
TpProcMemLvDdr3, ///< 48 .. Before LV DDR3
TpProcMemInitMCT, ///< 49 .. Before InitMCT
TpProcMemOtherTiming, ///< 4A.. Before OtherTiming
TpProcMemUMAMemTyping, ///< 4B .. Before UMAMemTyping
TpProcMemSetDqsEccTmgs, ///< 4C .. Before SetDqsEccTmgs
TpProcMemMemClr, ///< 4D .. Before MemClr
TpProcMemOnDimmThermal, ///< 4E .. Before On DIMM Thermal
TpProcMemDmi, ///< 4F .. Before DMI
TpProcMemEnd, ///< 50 .. End of memory code
// CPU test points
TpProcCpuEntryDmi, ///< 51 .. Entry point CreateDmiRecords
TpProcCpuEntryPstate, ///< 52 .. Entry point GenerateSsdt
TpProcCpuEntryPstateLeveling, ///< 53 .. Entry point PStateLeveling
TpProcCpuEntryPstateGather, ///< 54 .. Entry point PStateGatherData
TpProcCpuEntryWhea, ///< 55 .. Entry point CreateAcpiWhea
TpProcCpuEntrySrat, ///< 56 .. Entry point CreateAcpiSrat
TpProcCpuEntrySlit, ///< 57 .. Entry point CreateAcpiSlit
TpProcCpuProcessRegisterTables, ///< 58 .. Register table processing
TpProcCpuSetBrandID, ///< 59 .. Set brand ID
TpProcCpuLocalApicInit, ///< 5A .. Initialize local APIC
TpProcCpuLoadUcode, ///< 5B .. Load microcode patch
TpProcCpuBeforePMFeatureInit, ///< 5C .. BeforePM feature dispatch point
TpProcCpuPowerMgmtInit, ///< 5D .. Power Management table processing
TpProcCpuEarlyFeatureInit, ///< 5E .. Early feature dispatch point
TpProcCpuCoreLeveling, ///< 5F .. Core Leveling
TpProcCpuApMtrrSync, ///< 60 .. AP MTRR sync up
TpProcCpuPostFeatureInit, ///< 61 .. POST feature dispatch point
TpProcCpuFeatureLeveling, ///< 62 .. CPU Feature Leveling
TpProcCpuBeforeRelinquishAPsFeatureInit, ///< 63 .. Before Relinquishing control of APs feature dispatch point
TpProcCpuBeforeAllocateWheaBuffer, ///< 64 .. Before the WHEA init code calls out to allocate a buffer
TpProcCpuAfterAllocateWheaBuffer, ///< 65 .. After the WHEA init code calls out to allocate a buffer
TpProcCpuBeforeAllocateSratBuffer, ///< 66 .. Before the SRAT init code calls out to allocate a buffer
TpProcCpuAfterAllocateSratBuffer, ///< 67 .. After the SRAT init code calls out to allocate a buffer
TpProcCpuBeforeLocateSsdtBuffer, ///< 68 .. Before the P-state init code calls out to locate a buffer
TpProcCpuAfterLocateSsdtBuffer, ///< 69 .. After the P-state init code calls out to locate a buffer
TpProcCpuBeforeAllocateSsdtBuffer, ///< 6A .. Before the P-state init code calls out to allocate a buffer
TpProcCpuAfterAllocateSsdtBuffer, ///< 6B .. After the P-state init code calls out to allocate a buffer
// HT test points
TpProcHtEntry = 0x71, ///< 71 .. Coherent Discovery begin (Public interface)
TpProcHtTopology, ///< 72 .. Topology match, routing, begin
TpProcHtManualNc, ///< 73 .. Manual Non-coherent Init begin
TpProcHtAutoNc, ///< 74 .. Automatic Non-coherent init begin
TpProcHtOptGather, ///< 75 .. Optimization: Gather begin
TpProcHtOptRegang, ///< 76 .. Optimization: Regang begin
TpProcHtOptLinks, ///< 77 .. Optimization: Link Begin
TpProcHtOptSubLinks, ///< 78 .. Optimization: Sublinks begin
TpProcHtOptFinish, ///< 79 .. Optimization: Set begin
TpProcHtTrafficDist, ///< 7A .. Traffic Distribution begin
TpProcHtTuning, ///< 7B .. Misc Tuning Begin
TpProcHtDone, ///< 7C .. HT Init complete
TpProcHtApMapEntry, ///< 7D .. AP HT: Init Maps begin
TpProcHtApMapDone, ///< 7E .. AP HT: Complete
// Extended memory test point
TpProcMemSendMRS2 = 0x80, ///< 80 .. Sending MRS2
TpProcMemSendMRS3, ///< 81 .. Sedding MRS3
TpProcMemSendMRS1, ///< 82 .. Sending MRS1
TpProcMemSendMRS0, ///< 83 .. Sending MRS0
TpProcMemContinPatternGenRead, ///< 84 .. Continuous Pattern Read
TpProcMemContinPatternGenWrite, ///< 85 .. Continuous Pattern Write
StartNbTestPoints = 0x90, ///< 90 Entry used for range testing for @b NorthBridge related TPs
TpNbxxx, ///< 91 .
EndNbTestPoints, ///< 92 End of TP range for NB
StartSbTestPoints = 0xB0, ///< B0 Entry used for range testing for @b SouthBridge related TPs
TpSbxxx, ///< B1 .
EndSbTestPoints, ///< B2 End of TP range for SB
// Interface test points
TpIfAmdInitResetEntry = 0xC0, ///< C0 .. Entry to AmdInitReset
TpIfAmdInitResetExit, ///< C1 .. Exiting from AmdInitReset
TpIfAmdInitRecoveryEntry, ///< C2 .. Entry to AmdInitRecovery
TpIfAmdInitRecoveryExit, ///< C3 .. Exiting from AmdInitRecovery
TpIfAmdInitEarlyEntry, ///< C4 .. Entry to AmdInitEarly
TpIfAmdInitEarlyExit, ///< C5 .. Exiting from AmdInitEarly
TpIfAmdInitPostEntry, ///< C6 .. Entry to AmdInitPost
TpIfAmdInitPostExit, ///< C7 .. Exiting from AmdInitPost
TpIfAmdInitEnvEntry, ///< C8 .. Entry to AmdInitEnv
TpIfAmdInitEnvExit, ///< C9 .. Exiting from AmdInitEnv
TpIfAmdInitMidEntry, ///< CA .. Entry to AmdInitMid
TpIfAmdInitMidExit, ///< CB .. Exiting from AmdInitMid
TpIfAmdInitLateEntry, ///< CC .. Entry to AmdInitLate
TpIfAmdInitLateExit, ///< CD .. Exiting from AmdInitLate
TpIfAmdS3SaveEntry, ///< CE .. Entry to AmdS3Save
TpIfAmdS3SaveExit, ///< CF .. Exiting from AmdS3Save
TpIfAmdInitResumeEntry, ///< D0 .. Entry to AmdInitResume
TpIfAmdInitResumeExit, ///< D1 .. Exiting from AmdInitResume
TpIfAmdS3LateRestoreEntry, ///< D2 .. Entry to AmdS3LateRestore
TpIfAmdS3LateRestoreExit, ///< D3 .. Exiting from AmdS3LateRestore
TpIfAmdLateRunApTaskEntry, ///< D4 .. Entry to AmdS3LateRestore
TpIfAmdLateRunApTaskExit, ///< D5 .. Exiting from AmdS3LateRestore
TpIfAmdReadEventLogEntry, ///< D6 .. Entry to AmdReadEventLog
TpIfAmdReadEventLogExit, ///< D7 .. Exiting from AmdReadEventLog
TpIfAmdGetApicIdEntry, ///< D8 .. Entry to AmdGetApicId
TpIfAmdGetApicIdExit, ///< D9 .. Exiting from AmdGetApicId
TpIfAmdGetPciAddressEntry, ///< DA .. Entry to AmdGetPciAddress
TpIfAmdGetPciAddressExit, ///< DB .. Exiting from AmdGetPciAddress
TpIfAmdIdentifyCoreEntry, ///< DC .. Entry to AmdIdentifyCore
TpIfAmdIdentifyCoreExit, ///< DD .. Exiting from AmdIdentifyCore
TpIfBeforeRunApFromIds, ///< DE .. After IDS calls out to run code on an AP
TpIfAfterRunApFromIds, ///< DF .. After IDS calls out to run code on an AP
TpIfBeforeGetIdsData, ///< E0 .. Before IDS calls out to get IDS data
TpIfAfterGetIdsData, ///< E1 .. After IDS calls out to get IDS data
TpIfBeforeAllocateHeapBuffer, ///< E2 .. Before the heap manager calls out to allocate a buffer
TpIfAfterAllocateHeapBuffer, ///< E3 .. After the heap manager calls out to allocate a buffer
TpIfBeforeDeallocateHeapBuffer, ///< E4 .. Before the heap manager calls out to deallocate a buffer
TpIfAfterDeallocateHeapBuffer, ///< E5 .. After the heap manager calls out to deallocate a buffer
TpIfBeforeLocateHeapBuffer, ///< E6 .. Before the heap manager calls out to locate a buffer
TpIfAfterLocateHeapBuffer, ///< E7 .. After the heap manager calls out to locate a buffer
TpIfBeforeRunApFromAllAps, ///< E8 .. Before the BSP calls out to run code on an AP
TpIfAfterRunApFromAllAps, ///< E9 .. After the BSP calls out to run code on an AP
TpIfBeforeRunApFromAllCore0s, ///< EA .. Before the BSP calls out to run code on an AP
TpIfAfterRunApFromAllCore0s, ///< EB .. After the BSP calls out to run code on an AP
TpIfBeforeAllocateS3SaveBuffer, ///< EC .. Before the S3 save code calls out to allocate a buffer
TpIfAfterAllocateS3SaveBuffer, ///< ED .. After the S3 save code calls out to allocate a buffer
TpIfBeforeAllocateMemoryS3SaveBuffer, ///< EE .. Before the memory S3 save code calls out to allocate a buffer
TpIfAfterAllocateMemoryS3SaveBuffer, ///< EF .. After the memory S3 save code calls out to allocate a buffer
TpIfBeforeLocateS3PciBuffer, ///< F0 .. Before the memory code calls out to locate a buffer
TpIfAfterLocateS3PciBuffer, ///< F1 .. After the memory code calls out to locate a buffer
TpIfBeforeLocateS3CPciBuffer, ///< F2 .. Before the memory code calls out to locate a buffer
TpIfAfterLocateS3CPciBuffer, ///< F3 .. After the memory code calls out to locate a buffer
TpIfBeforeLocateS3MsrBuffer, ///< F4 .. Before the memory code calls out to locate a buffer
TpIfAfterLocateS3MsrBuffer, ///< F5 .. After the memory code calls out to locate a buffer
TpIfBeforeLocateS3CMsrBuffer, ///< F6 .. Before the memory code calls out to locate a buffer
TpIfAfterLocateS3CMsrBuffer, ///< F7 .. After the memory code calls out to locate a buffer
TpPerfUnit, ///< F8 .. The Unit of performance measure.
EndAgesaTps = 0xFF, ///< Last defined AGESA TP
} AGESA_TP;
///Ids Feat description
typedef enum {
IDS_FEAT_UCODE_UPDATE = 0x0000, ///< Feat for Ucode Update
IDS_FEAT_TARGET_PSTATE, ///< Feat for Target Pstate
IDS_FEAT_POSTPSTATE, ///< Feat for Post Pstate
IDS_FEAT_ECC_CTRL, ///< Feat for Ecc Control
IDS_FEAT_ECC_SYMBOL_SIZE, ///< Feat for Ecc symbol size
IDS_FEAT_DCT_ALLMEMCLK, ///< Feat for all memory clock
IDS_FEAT_DCT_GANGMODE, ///< Feat for Dct gang mode
IDS_FEAT_DCT_BURSTLENGTH, ///< Feat for dct burst length
IDS_FEAT_DCT_POWERDOWN, ///< Feat for dct power down
IDS_FEAT_DCT_DLLSHUTDOWN, ///< Feat for dct dll shut down
IDS_FEAT_PROBE_FILTER, ///< Feat for probe filter
IDS_FEAT_HDTOUT, ///< Feat for hdt out
IDS_FEAT_HT_SETTING, ///< Feat for Ht setting
IDS_FEAT_GNB_PLATFORMCFG, ///< Feat for override GNB platform config
IDS_FEAT_CPB_CTRL, ///< Feat for Config the Core peformance boost feature
IDS_FEAT_HTC_CTRL, ///< Feat for Hardware Thermal Control
IDS_FEAT_MEMORY_MAPPING, ///< Feat for Memory Mapping
IDS_FEAT_POWER_POLICY, ///< Feat for Power Policy
IDS_FEAT_NV_TO_CMOS, ///< Feat for Save BSP Nv to CMOS
IDS_FEAT_END = 0xFF ///< End of Common feat
} IDS_FEAT;
typedef IDS_STATUS IDS_COMMON_FUNC (
IN OUT VOID *DataPtr,
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN IDS_NV_ITEM *IdsNvPtr
);
typedef IDS_COMMON_FUNC *PIDS_COMMON_FUNC;
/// Data Structure of IDS Feature block
typedef struct _IDS_FEAT_STRUCT {
IDS_FEAT IdsFeat; ///< Ids Feat ID
BOOLEAN IsBsp; ///< swith for Bsp check
AGESA_IDS_OPTION IdsOption; ///< IDS option
UINT64 CpuFamily; ///<
PIDS_COMMON_FUNC pf_idsoption; ///<pointer to function
} IDS_FEAT_STRUCT;
/// Data Structure of IDS option
typedef struct _IDS_OPTION_STRUCT {
AGESA_IDS_OPTION idsoption; ///< IDS option
PIDS_COMMON_FUNC pf_idsoption; ///<pointer to function
} IDS_OPTION_STRUCT;
/// Data Structure of IDS option table
typedef struct _IDS_OPTION_STRUCT_TBL {
UINT8 version; ///<Version of IDS option table
UINT16 size; ///<Size of IDS option table
CONST IDS_OPTION_STRUCT *pIdsOptionStruct; ///<pointer to array of structure
} IDS_OPTION_STRUCT_TBL;
#endif // _IDS_H_

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src/vendorcode/amd/agesa/f12/Include/IdsHt.h
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@ -1,123 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD IDS HyperTransport Definitions
*
* Contains AMD AGESA Integrated Debug HT related items.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: IDS
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _IDS_HT_H_
#define _IDS_HT_H_
// Frequency equates for call backs which take an actual frequency setting
#define HT_FREQUENCY_200M 0
#define HT_FREQUENCY_400M 2
#define HT_FREQUENCY_600M 4
#define HT_FREQUENCY_800M 5
#define HT_FREQUENCY_1000M 6
#define HT_FREQUENCY_1200M 7
#define HT_FREQUENCY_1400M 8
#define HT_FREQUENCY_1600M 9
#define HT_FREQUENCY_1800M 10
#define HT_FREQUENCY_2000M 11
#define HT_FREQUENCY_2200M 12
#define HT_FREQUENCY_2400M 13
#define HT_FREQUENCY_2600M 14
#define HT_FREQUENCY_2800M 17
#define HT_FREQUENCY_3000M 18
#define HT_FREQUENCY_3200M 19
#define HT_FREQUENCY_3600M 20
/**
* HT IDS: HT Link Port Override params.
*
* Provide an absolute override of HT Link Port settings. No checking is done that
* the settings obey limits or capabilities, this responsibility rests with the user.
*
* Rules for values of structure items:
* - Socket
* - HT_LIST_TERMINAL == end of port override list, rest of item is not accessed
* - HT_LIST_MATCH_ANY == Match Any Socket
* - 0 .. 7 == The matching socket
* - Link
* - HT_LIST_MATCH_ANY == Match Any package link (that is not the internal links)
* - HT_LIST_MATCH_INTERNAL_LINK == Match the internal links
* - 0 .. 7 == The matching package link. 0 .. 3 are the ganged links or sublink 0's, 4 .. 7 are the sublink1's.
* - Frequency
* - HT_LIST_TERMINAL == Do not override the frequency, AUTO setting
* - HT_FREQUENCY_200M .. HT_FREQUENCY_3600M = The frequency value to use
* - Widthin
* - HT_LIST_TERMINAL == Do not override the width, AUTO setting
* - 2, 4, 8, 16, 32 == The width value to use
* - Widthout
* - HT_LIST_TERMINAL == Do not override the width, AUTO setting
* - 2, 4, 8, 16, 32 == The width value to use
*/
typedef struct {
// Match Fields
UINT8 Socket; ///< The Socket which this port is on.
UINT8 Link; ///< The port for this package link on that socket.
// Override fields
UINT8 Frequency; ///< Absolutely override the port's frequency.
UINT8 WidthIn; ///< Absolutely override the port's width.
UINT8 WidthOut; ///< Absolutely override the port's width.
} HTIDS_PORT_OVERRIDE;
/**
* A list of port overrides to search.
*/
typedef HTIDS_PORT_OVERRIDE *HTIDS_PORT_OVERRIDE_LIST;
VOID
HtIdsGetPortOverride (
IN BOOLEAN IsSourcePort,
IN OUT PORT_DESCRIPTOR *Port0,
IN OUT PORT_DESCRIPTOR *Port1,
IN OUT HTIDS_PORT_OVERRIDE_LIST *PortOverrideList,
IN STATE_DATA *State
);
typedef
VOID
F_HtIdsGetPortOverride (
IN BOOLEAN IsSourcePort,
IN OUT PORT_DESCRIPTOR *Port0,
IN OUT PORT_DESCRIPTOR *Port1,
IN OUT HTIDS_PORT_OVERRIDE_LIST *PortOverrideList,
IN STATE_DATA *State
);
typedef F_HtIdsGetPortOverride* PF_HtIdsGetPortOverride;
#endif // _IDS_HT_H

89
src/vendorcode/amd/agesa/f12/Include/OptionDmi.h
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@ -1,89 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD DMI option API.
*
* Contains structures and values used to control the DMI option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _OPTION_DMI_H_
#define _OPTION_DMI_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
typedef AGESA_STATUS OPTION_DMI_FEATURE (
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN OUT DMI_INFO **DmiPtr
);
typedef AGESA_STATUS OPTION_DMI_RELEASE_BUFFER (
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
#define DMI_STRUCT_VERSION 0x01
/// DMI option configuration. Determine the item of structure when compiling.
typedef struct {
UINT16 OptDmiVersion; ///< Dmi version.
OPTION_DMI_FEATURE *DmiFeature; ///< Feature main routine, otherwise dummy.
OPTION_DMI_RELEASE_BUFFER *DmiReleaseBuffer; ///< Release buffer
UINT16 NumEntries; ///< Number of entry.
VOID *((*FamilyList)[]); ///< Family service.
} OPTION_DMI_CONFIGURATION;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_DMI_H_

138
src/vendorcode/amd/agesa/f12/Include/OptionFamily12hEarlySample.h
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@ -1,138 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Family 12h 'early sample' support
*
* This file defines the required structures for family 12h pre-production processors.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 37456 $ @e \$Date: 2010-09-04 04:17:05 +0800 (Sat, 04 Sep 2010) $
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _OPTION_FAMILY_12H_EARLY_SAMPLE_H_
#define _OPTION_FAMILY_12H_EARLY_SAMPLE_H_
/*---------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
/**
* Return the appropriate values of certain NB P-state related registers.
*
* @param[in,out] FCRxFE00_6000 The value of FCRxFE006000.
* @param[in,out] FCRxFE00_6002 The value of FCRxFE006002.
* @param[in,out] FCRxFE00_7006 The value of FCRxFE007006.
* @param[in,out] FCRxFE00_7009 The value of FCRxFE007009.
* @param[in] MainPll The main PLL frequency.
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
*/
typedef VOID F_F12_ES_NB_PSTATE_INIT (
IN OUT VOID *FCRxFE00_6000,
IN OUT VOID *FCRxFE00_6002,
IN OUT VOID *FCRxFE00_7006,
IN OUT VOID *FCRxFE00_7009,
IN UINT32 MainPll,
IN AMD_CONFIG_PARAMS *StdHeader
);
/// Reference to a Method.
typedef F_F12_ES_NB_PSTATE_INIT *PF_F12_ES_NB_PSTATE_INIT;
/**
* Return the appropriate value of a certain NB P-state related register.
*
* @param[in,out] FCRxFE00_6000 The value of FCRxFE006000.
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
*/
typedef VOID F_F12_ES_POWER_PLANE_INIT (
IN OUT VOID *FCRxFE00_6000,
IN AMD_CONFIG_PARAMS *StdHeader
);
/// Reference to a Method.
typedef F_F12_ES_POWER_PLANE_INIT *PF_F12_ES_POWER_PLANE_INIT;
/**
* Implements an early sample workaround required for C6
*
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
*/
typedef VOID F_F12_ES_C6_INIT (
IN AMD_CONFIG_PARAMS *StdHeader
);
/// Reference to a Method.
typedef F_F12_ES_C6_INIT *PF_F12_ES_C6_INIT;
/// Hook points in the core functionality necessary for
/// providing support for pre-production CPUs.
typedef struct {
PF_F12_ES_POWER_PLANE_INIT F12PowerPlaneInitHook; ///< Allows for override of a certain processor register value during power plane init
PF_F12_ES_NB_PSTATE_INIT F12NbPstateInitHook; ///< Allows for override of certain processor register values for proper NB P-state init
} F12_ES_CORE_SUPPORT;
/// Hook points in the C6 feature necessary for
/// providing support for pre-production CPUs.
typedef struct {
PF_F12_ES_C6_INIT F12InitializeC6; ///< Hook for erratum 453 workaround
} F12_ES_C6_SUPPORT;
/*---------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*---------------------------------------------------------------------------------------
*/
#endif // _OPTION_FAMILY_12H_EARLY_SAMPLE_H_

81
src/vendorcode/amd/agesa/f12/Include/OptionGfxRecovery.h
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@ -1,81 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD GFX Recovery option API.
*
* Contains structures and values used to control the GfxRecovery option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _OPTION_GFX_RECOVERY_H_
#define _OPTION_GFX_RECOVERY_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
typedef AGESA_STATUS OPTION_GFX_RECOVERY_FEATURE (
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
#define GFX_RECOVERY_STRUCT_VERSION 0x01
/// The Option Configuration of GFX Recovery
typedef struct {
UINT16 OptGfxRecoveryVersion; ///< The version number of GFX Recovery
OPTION_GFX_RECOVERY_FEATURE *GfxRecoveryFeature; ///< The Option Feature of GFX Recovery
} OPTION_GFX_RECOVERY_CONFIGURATION;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_GFX_RECOVERY_H_

105
src/vendorcode/amd/agesa/f12/Include/OptionGnb.h
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@ -1,105 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD ALIB option API.
*
* Contains structures and values used to control the ALIB option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 49316 $ @e \$Date: 2011-03-22 03:06:29 +0800 (Tue, 22 Mar 2011) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _OPTION_GNB_H_
#define _OPTION_GNB_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
typedef AGESA_STATUS OPTION_GNB_FEATURE (
IN AMD_CONFIG_PARAMS *StdHeader
);
/// The Option Configuration
typedef struct {
UINT64 Type; ///< Type
OPTION_GNB_FEATURE *GnbFeature; ///< The GNB Feature
} OPTION_GNB_CONFIGURATION;
/// The Build time options configuration
typedef struct {
BOOLEAN IgfxModeAsPcieEp; ///< Itegrated Gfx mode Pcie EP or Legacy
BOOLEAN LclkDeepSleepEn; ///< Default for LCLK deep sleep
BOOLEAN LclkDpmEn; ///< Default for LCLK DPM
BOOLEAN GmcPowerGateStutterOnly; ///< Force GMC power gate to stutter only
BOOLEAN SmuSclkClockGatingEnable; ///< Control SMU SCLK gating
BOOLEAN PcieAspmBlackListEnable; ///< Control Pcie Aspm Black List
BOOLEAN IvrsRelativeAddrNamesSupport; ///< Support for relative address names
BOOLEAN GnbLoadRealFuseTable; ///< Support for fuse table loading
UINT32 CfgGnbLinkReceiverDetectionPooling; ///< Receiver pooling detection time in us.
UINT32 CfgGnbLinkL0Pooling; ///< Pooling for link to get to L0 in us
UINT32 CfgGnbLinkGpioResetAssertionTime; ///< Gpio reset assertion time in us
UINT32 CfgGnbLinkResetToTrainingTime; ///< Time duration between deassert GPIO reset and release training in us
UINT8 CfgGnbTrainingAlgorithm; ///< distribution of training across interface calls
BOOLEAN CfgForceCableSafeOff; ///< Force cable safe off
BOOLEAN CfgOrbClockGatingEnable; ///< Control ORB clock gating
UINT8 CfgPciePowerGatingFlags; ///< Pcie Power gating flags
BOOLEAN CfgIocLclkClockGatingEnable; ///< Control IOC LCLK clock gating
BOOLEAN CfgIocSclkClockGatingEnable; ///< Control IOC SCLK clock gating
BOOLEAN CfgIommuL1ClockGatingEnable; ///< Control IOMMU L1 clock gating
BOOLEAN CfgIommuL2ClockGatingEnable; ///< Control IOMMU L2 clock gating
BOOLEAN CfgAltVddNb; ///< AltVDDNB support
} GNB_BUILD_OPTIONS;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_GNB_H_

351
src/vendorcode/amd/agesa/f12/Include/OptionMemory.h
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@ -1,351 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Memory option API.
*
* Contains structures and values used to control the Memory option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _OPTION_MEMORY_H_
#define _OPTION_MEMORY_H_
/* Memory Includes */
#include "mm.h"
#include "mn.h"
#include "mt.h"
#include "ma.h"
#include "mp.h"
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
#define MAX_FF_TYPES 6 ///< Maximum number of DDR Form factors (UDIMMs, RDIMMMs, SODIMMS) supported
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
/*
* STANDARD MEMORY FEATURE FUNCTION POINTER
*/
typedef BOOLEAN OPTION_MEM_FEATURE_NB (
IN OUT MEM_NB_BLOCK *NBPtr
);
typedef BOOLEAN MEM_TECH_FEAT (
IN OUT MEM_TECH_BLOCK *TechPtr
);
typedef UINT8 MEM_TABLE_FEAT (
IN OUT MEM_TABLE_ALIAS **MTPtr
);
#define MEM_FEAT_BLOCK_NB_STRUCT_VERSION 0x01
/**
* MEMORY FEATURE BLOCK - This structure serves as a vector table for standard
* memory feature implementation functions. It contains vectors for all of the
* features that are supported by the various Northbridge devices supported by
* AGESA.
*/
typedef struct _MEM_FEAT_BLOCK_NB {
UINT16 OptMemFeatVersion; ///< Version of memory feature block.
OPTION_MEM_FEATURE_NB *OnlineSpare; ///< Online spare support.
OPTION_MEM_FEATURE_NB *InterleaveBanks; ///< Bank (Chip select) interleaving support.
OPTION_MEM_FEATURE_NB *UndoInterleaveBanks; ///< Undo Bank (Chip Select) interleaving.
OPTION_MEM_FEATURE_NB *CheckInterleaveNodes; ///< Check for Node interleaving support.
OPTION_MEM_FEATURE_NB *InterleaveNodes; ///< Node interleaving support.
OPTION_MEM_FEATURE_NB *InterleaveChannels; ///< Channel interleaving support.
OPTION_MEM_FEATURE_NB *InterleaveRegion; ///< Interleave Region support.
OPTION_MEM_FEATURE_NB *CheckEcc; ///< Check for ECC support.
OPTION_MEM_FEATURE_NB *InitEcc; ///< ECC support.
OPTION_MEM_FEATURE_NB *Training; ///< Choose the type of training (Parallel, standard or hardcoded).
OPTION_MEM_FEATURE_NB *LvDdr3; ///< Low voltage DDR3 dimm support
OPTION_MEM_FEATURE_NB *OnDimmThermal; ///< On-Dimm thermal management
MEM_TECH_FEAT *DramInit; ///< Choose the type of Dram init (hardware based or software based).
OPTION_MEM_FEATURE_NB *ExcludeDIMM; ///< Exclude a dimm.
OPTION_MEM_FEATURE_NB *InitEarlySampleSupport; ///< Initialize early sample support.
OPTION_MEM_FEATURE_NB *InitCPG; ///< Continuous pattern generation.
OPTION_MEM_FEATURE_NB *InitHwRxEn; ///< Hardware Receiver Enable Training Initilization.
} MEM_FEAT_BLOCK_NB;
typedef AGESA_STATUS MEM_MAIN_FLOW_CONTROL (
IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
);
typedef BOOLEAN OPTION_MEM_FEATURE_MAIN (
IN MEM_MAIN_DATA_BLOCK *MMPtr
);
typedef BOOLEAN MEM_NB_CONSTRUCTOR (
IN OUT MEM_NB_BLOCK *NBPtr,
IN OUT MEM_DATA_STRUCT *MemPtr,
IN MEM_FEAT_BLOCK_NB *FeatPtr,
IN MEM_SHARED_DATA *mmSharedPtr, ///< Pointer to Memory scratchpad
IN UINT8 NodeID
);
typedef BOOLEAN MEM_TECH_CONSTRUCTOR (
IN OUT MEM_TECH_BLOCK *TechPtr,
IN OUT MEM_NB_BLOCK *NBPtr
);
typedef VOID MEM_INITIALIZER (
IN OUT MEM_DATA_STRUCT *MemPtr
);
typedef AGESA_STATUS MEM_PLATFORM_CFG (
IN struct _MEM_DATA_STRUCT *MemData,
IN UINT8 SocketID,
IN CH_DEF_STRUCT *CurrentChannel
);
typedef BOOLEAN MEM_IDENDIMM_CONSTRUCTOR (
IN OUT MEM_NB_BLOCK *NBPtr,
IN OUT MEM_DATA_STRUCT *MemPtr,
IN UINT8 NodeID
);
typedef VOID MEM_TECH_TRAINING_FEAT (
IN OUT MEM_TECH_BLOCK *TechPtr,
IN UINT8 Pass
);
typedef BOOLEAN MEM_RESUME_CONSTRUCTOR (
IN OUT VOID *S3NBPtr,
IN OUT MEM_DATA_STRUCT *MemPtr,
IN UINT8 NodeID
);
typedef AGESA_STATUS MEM_PLAT_SPEC_CFG (
IN struct _MEM_DATA_STRUCT *MemData,
IN OUT CH_DEF_STRUCT *CurrentChannel,
IN OUT MEM_PS_BLOCK *PsPtr
);
typedef AGESA_STATUS MEM_FLOW_CFG (
IN OUT MEM_MAIN_DATA_BLOCK *MemData
);
#define MEM_FEAT_BLOCK_MAIN_STRUCT_VERSION 0x01
/**
* MAIN FEATURE BLOCK - This structure serves as vector table for memory features
* that shared between all northbridge devices.
*/
typedef struct _MEM_FEAT_BLOCK_MAIN {
UINT16 OptMemFeatVersion; ///< Version of main feature block.
OPTION_MEM_FEATURE_MAIN *Training; ///< Training features.
OPTION_MEM_FEATURE_MAIN *ExcludeDIMM; ///< Exclude a dimm.
OPTION_MEM_FEATURE_MAIN *OnlineSpare; ///< On-line spare.
OPTION_MEM_FEATURE_MAIN *InterleaveNodes; ///< Node interleave.
OPTION_MEM_FEATURE_MAIN *InitEcc; ///< Initialize ECC on all nodes if they all support it.
OPTION_MEM_FEATURE_MAIN *MemClr; ///< Memory Clear.
OPTION_MEM_FEATURE_MAIN *MemDmi; ///< Memory DMI Support.
OPTION_MEM_FEATURE_MAIN *LvDDR3; ///< Low voltage DDR3 support.
OPTION_MEM_FEATURE_MAIN *UmaAllocation; ///< Uma Allocation.
OPTION_MEM_FEATURE_MAIN *MemSave; ///< Memory Context Save
OPTION_MEM_FEATURE_MAIN *MemRestore; ///< Memory Context Restore
} MEM_FEAT_BLOCK_MAIN;
#define MEM_NB_SUPPORT_STRUCT_VERSION 0x01
#define MEM_TECH_FEAT_BLOCK_STRUCT_VERSION 0x01
#define MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION 0x01
#define MEM_TECH_LRDIMM_STRUCT_VERSION 0x01
/**
* MEMORY TECHNOLOGY FEATURE BLOCK - This structure serves as a vector table for standard
* memory feature implementation functions. It contains vectors for all of the
* features that are supported by the various Technology features supported by
* AGESA.
*/
typedef struct _MEM_TECH_FEAT_BLOCK {
UINT16 OptMemTechFeatVersion; ///< Version of memory Tech feature block.
MEM_TECH_FEAT *EnterHardwareTraining; ///<Enter HW WL Training
MEM_TECH_FEAT *SwWLTraining; ///<SW Write Levelization training
MEM_TECH_FEAT *HwBasedWLTrainingPart1; ///<HW based write levelization Training Part 1
MEM_TECH_FEAT *HwBasedDQSReceiverEnableTrainingPart1; ///<HW based DQS receiver Enabled Training Part 1
MEM_TECH_FEAT *HwBasedWLTrainingPart2; ///<HW based write levelization Training Part 2
MEM_TECH_FEAT *HwBasedDQSReceiverEnableTrainingPart2; ///<HW based DQS receiver Enabled Training Part 2
MEM_TECH_FEAT *TrainExitHwTrn; ///<Exit HW WL Training
MEM_TECH_FEAT *NonOptimizedSWDQSRecEnTrainingPart1; ///< Non-Optimized Software based receiver Enable Training part 1
MEM_TECH_FEAT *OptimizedSwDqsRecEnTrainingPart1; ///< Optimized Software based receiver Enable Training part 1
MEM_TECH_FEAT *NonOptimizedSRdWrPosTraining; ///< Non-Optimized Rd Wr Position training
MEM_TECH_FEAT *OptimizedSRdWrPosTraining; ///< Optimized Rd Wr Position training
MEM_TECH_FEAT *MaxRdLatencyTraining; ///< MaxReadLatency Training
MEM_TECH_FEAT *RdPosTraining; ///< HW Rx En Seed Training
} MEM_TECH_FEAT_BLOCK;
/**
* MEMORY TECHNOLOGY LRDIMM BLOCK - This structure serves as a vector table for standard
* memory feature implementation functions. It contains vectors for all of the
* features that are supported by the various LRDIMM features supported by
* AGESA.
*/
typedef struct _MEM_TECH_LRDIMM {
UINT16 OptMemTechLrdimmVersion; ///< Version of memory Tech feature block.
MEM_TECH_FEAT *MemTInitializeLrdimm; ///< LRDIMM initialization
} MEM_TECH_LRDIMM;
/**
* MEMORY NORTHBRIDGE SUPPORT STRUCT - This structure groups the Northbridge dependent
* options together in a list to provide a single access point for all code to use
* and to ensure that everything corresponding to the same NB type is grouped together.
*
* The Technology Block pointers are not included in this structure because DRAM technology
* needs to be decoupled from the northbridge type.
*
*/
typedef struct _MEM_NB_SUPPORT {
UINT16 MemNBSupportVersion; ///< Version of northbridge support.
MEM_NB_CONSTRUCTOR *MemConstructNBBlock; ///< NorthBridge block constructor.
MEM_INITIALIZER *MemNInitDefaults; ///< Default value initialization for MEM_DATA_STRUCT.
MEM_FEAT_BLOCK_NB *MemFeatBlock; ///< Memory feature block.
MEM_RESUME_CONSTRUCTOR *MemS3ResumeConstructNBBlock; ///< S3 memory initialization northbridge block constructor.
MEM_IDENDIMM_CONSTRUCTOR *MemIdentifyDimmConstruct; ///< Constructor for address to dimm identification.
} MEM_NB_SUPPORT;
/*
* MEMORY Non-Training FEATURES - This structure serves as a vector table for standard
* memory non-training feature implementation functions. It contains vectors for all of the
* features that are supported by the various Technology devices supported by
* AGESA.
*/
/**
* MAIN TRAINING SEQUENCE LIST - This structure serves as vector table for memory features
* that shared between all northbridge devices.
*/
typedef struct _MEM_FEAT_TRAIN_SEQ {
UINT16 OptMemTrainingSequenceListVersion; ///< Version of main feature block.
OPTION_MEM_FEATURE_NB *TrainingSequence; ///< Training Sequence function.
OPTION_MEM_FEATURE_NB *TrainingSequenceEnabled; ///< Enable function.
MEM_TECH_FEAT_BLOCK *MemTechFeatBlock; ///< Memory feature block.
} MEM_FEAT_TRAIN_SEQ;
/**
* PLATFORM SPECIFIC CONFIGURATION BLOCK - This structure groups various PSC table
* entries which are used by PSC engine
*/
typedef struct _MEM_PSC_TABLE_BLOCK {
PSC_TBL_ENTRY **TblEntryOfMaxFreq; ///< Table entry of MaxFreq.
PSC_TBL_ENTRY **TblEntryOfDramTerm; ///< Table entry of Dram Term.
PSC_TBL_ENTRY **TblEntryOfODTPattern; ///< Table entry of ODT Pattern.
PSC_TBL_ENTRY **TblEntryOfSAO; ///< Table entry of Slow access mode, AddrTmg and ODC..
PSC_TBL_ENTRY **TblEntryOfMR0WR; ///< Table entry of MR0[WR].
PSC_TBL_ENTRY **TblEntryOfMR0CL; ///< Table entry of MR0[CL].
PSC_TBL_ENTRY **TblEntryOfRC2IBT; ///< Table entry of RC2 IBT.
PSC_TBL_ENTRY **TblEntryOfRC10OpSpeed; ///< Table entry of RC10[operating speed].
PSC_TBL_ENTRY **TblEntryOfLRIBT;///< Table entry of LRDIMM IBT
PSC_TBL_ENTRY **TblEntryOfLRNPR; ///< Table entry of LRDIMM F0RC13[NumPhysicalRanks].
PSC_TBL_ENTRY **TblEntryOfLRNLR; ///< Table entry of LRDIMM F0RC13[NumLogicalRanks].
PSC_TBL_ENTRY **TblEntryOfGen; ///< Table entry of CLKDis map and CKE, ODT as well as ChipSel tri-state map.
} MEM_PSC_TABLE_BLOCK;
typedef BOOLEAN MEM_PSC_FLOW (
IN OUT MEM_NB_BLOCK *NBPtr,
IN MEM_PSC_TABLE_BLOCK *EntryOfTables
);
/**
* PLATFORM SPECIFIC CONFIGURATION FLOW BLOCK - Pointers to the sub-engines of platform
* specific configuration.
*/
typedef struct _MEM_PSC_FLOW_BLOCK {
MEM_PSC_TABLE_BLOCK *EntryOfTables; ///<Entry of NB specific MEM_PSC_TABLE_BLOCK
MEM_PSC_FLOW *MaxFrequency; ///< Sub-engine which performs "Max Frequency" value extraction.
MEM_PSC_FLOW *DramTerm; ///< Sub-engine which performs "Dram Term" value extraction.
MEM_PSC_FLOW *ODTPattern; ///< Sub-engine which performs "ODT Pattern" value extraction.
MEM_PSC_FLOW *SAO; ///< Sub-engine which performs "Slow access mode, AddrTmg and ODC" value extraction.
MEM_PSC_FLOW *MR0WrCL; ///< Sub-engine which performs "MR0[WR] and MR0[CL]" value extraction.
MEM_PSC_FLOW *RC2IBT; ///< Sub-engine "RC2 IBT" value extraction.
MEM_PSC_FLOW *RC10OpSpeed; ///< Sub-engine "RC10[operating speed]" value extraction.
MEM_PSC_FLOW *LRIBT; ///< Sub-engine "LRDIMM IBT" value extraction.
MEM_PSC_FLOW *LRNPR; ///< Sub-engine "LRDIMM F0RC13[NumPhysicalRanks]" value extraction.
MEM_PSC_FLOW *LRNLR; ///< Sub-engine "LRDIMM F0RC13[NumLogicalRanks]" value extraction.
} MEM_PSC_FLOW_BLOCK;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
/* Feature Default Return */
BOOLEAN MemFDefRet (
IN OUT MEM_NB_BLOCK *NBPtr
);
BOOLEAN MemMDefRet (
IN MEM_MAIN_DATA_BLOCK *MMPtr
);
BOOLEAN MemMDefRetFalse (
IN MEM_MAIN_DATA_BLOCK *MMPtr
);
BOOLEAN MemNIdentifyDimmConstructorRetDef (
IN OUT MEM_NB_BLOCK *NBPtr,
IN OUT MEM_DATA_STRUCT *MemPtr,
IN UINT8 NodeID
);
/* Table Feature Default Return */
UINT8 MemFTableDefRet (
IN OUT MEM_TABLE_ALIAS **MTPtr
);
/* S3 Feature Default Return */
BOOLEAN MemFS3DefConstructorRet (
IN OUT VOID *S3NBPtr,
IN OUT MEM_DATA_STRUCT *MemPtr,
IN UINT8 NodeID
);
BOOLEAN
MemProcessConditionalOverrides (
IN PSO_TABLE *PlatformMemoryConfiguration,
IN OUT MEM_NB_BLOCK *NBPtr,
IN UINT8 PsoAction,
IN UINT8 Dimm
);
#endif // _OPTION_MEMORY_H_

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@ -1,184 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Multi-socket option API.
*
* Contains structures and values used to control the multi-socket option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 48937 $ @e \$Date: 2011-03-15 03:37:15 +0800 (Tue, 15 Mar 2011) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _OPTION_MULTISOCKET_H_
#define _OPTION_MULTISOCKET_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
/**
* This function loops through all possible socket locations, gathering the number
* of power management steps each populated socket requires, and returns the
* highest number.
*
* @param[out] NumSystemSteps Maximum number of system steps required
* @param[in] StdHeader Config handle for library and services
*
*/
typedef VOID OPTION_MULTISOCKET_PM_STEPS (
OUT UINT8 *NumSystemSteps,
IN AMD_CONFIG_PARAMS *StdHeader
);
/**
* This function loops through all possible socket locations, starting core 0 of
* each populated socket to perform the passed in AP_TASK. After starting all
* other core 0s, the BSC will perform the AP_TASK as well. This must be run by
* the system BSC only.
*
* @param[in] TaskPtr Function descriptor
* @param[in] StdHeader Config handle for library and services
* @param[in] ConfigParams AMD entry point's CPU parameter structure
*
*/
typedef VOID OPTION_MULTISOCKET_PM_CORE0_TASK (
IN VOID *TaskPtr,
IN AMD_CONFIG_PARAMS *StdHeader,
IN VOID *ConfigParams
);
/**
* This function loops through all possible socket locations, comparing the
* maximum NB frequencies to determine the slowest. This function also
* determines if all coherent NB frequencies are equivalent.
*
* @param[in] NbPstate NB P-state number to check (0 = fastest)
* @param[in] PlatformConfig Platform profile/build option config structure.
* @param[out] SystemNbCofNumerator NB frequency numerator for the system in MHz
* @param[out] SystemNbCofDenominator NB frequency denominator for the system
* @param[out] SystemNbCofsMatch Whether or not all NB frequencies are equivalent
* @param[out] NbPstateIsEnabledOnAllCPUs Whether or not NbPstate is valid on all CPUs
* @param[in] StdHeader Config handle for library and services
*
* @retval TRUE At least one processor has NbPstate enabled.
* @retval FALSE NbPstate is disabled on all CPUs
*/
typedef BOOLEAN OPTION_MULTISOCKET_PM_NB_COF (
IN UINT32 NbPstate,
IN PLATFORM_CONFIGURATION *PlatformConfig,
OUT UINT32 *SystemNbCofNumerator,
OUT UINT32 *SystemNbCofDenominator,
OUT BOOLEAN *SystemNbCofsMatch,
OUT BOOLEAN *NbPstateIsEnabledOnAllCPUs,
IN AMD_CONFIG_PARAMS *StdHeader
);
/**
* This function loops through all possible socket locations, checking whether
* any populated sockets require NB COF VID programming.
*
* @param[in] StdHeader Config handle for library and services
*
*/
typedef BOOLEAN OPTION_MULTISOCKET_PM_NB_COF_UPDATE (
IN AMD_CONFIG_PARAMS *StdHeader
);
/**
* This function loops through all possible socket locations, collecting any
* power management initialization errors that may have occurred. These errors
* are transferred from the core 0s of the socket in which the errors occurred
* to the BSC's heap. The BSC's heap is then searched for the most severe error
* that occurred, and returns it. This function must be called by the BSC only.
*
* @param[in] StdHeader Config handle for library and services
*
*/
typedef AGESA_STATUS OPTION_MULTISOCKET_PM_GET_EVENTS (
IN AMD_CONFIG_PARAMS *StdHeader
);
/**
* This function loops through all possible socket locations and Nb Pstates,
* comparing the NB frequencies to determine the slowest NB P0 and NB Pmin in
* the system.
*
* @param[in] PlatformConfig Platform profile/build option config structure.
* @param[out] MinSysNbFreq NB frequency numerator for the system in MHz
* @param[out] MinP0NbFreq NB frequency numerator for P0 in MHz
* @param[in] StdHeader Config handle for library and services
*/
typedef VOID OPTION_MULTISOCKET_PM_NB_MIN_COF (
IN PLATFORM_CONFIGURATION *PlatformConfig,
OUT UINT32 *MinSysNbFreq,
OUT UINT32 *MinP0NbFreq,
IN AMD_CONFIG_PARAMS *StdHeader
);
#define MULTISOCKET_STRUCT_VERSION 0x01
/**
* Provide build configuration of cpu multi-socket or single socket support.
*
*/
typedef struct {
UINT16 OptMultiSocketVersion; ///< Table version
OPTION_MULTISOCKET_PM_STEPS *GetNumberOfSystemPmSteps; ///< Method: Get number of power mgt tasks
OPTION_MULTISOCKET_PM_CORE0_TASK *BscRunCodeOnAllSystemCore0s; ///< Method: Perform tasks on Core 0 of each processor
OPTION_MULTISOCKET_PM_NB_COF *GetSystemNbPstateSettings; ///< Method: Find the Northbridge frequency for the specified Nb Pstate in the system.
OPTION_MULTISOCKET_PM_NB_COF_UPDATE *GetSystemNbCofVidUpdate; ///< Method: Determine if any Northbridges in the system need to update their COF/VID.
OPTION_MULTISOCKET_PM_GET_EVENTS *BscRetrievePmEarlyInitErrors; ///< Method: Gathers error information from all Core 0s.
OPTION_MULTISOCKET_PM_NB_MIN_COF *GetMinNbCof; ///< Method: Get the minimum system and minimum P0 Northbridge frequency.
} OPTION_MULTISOCKET_CONFIGURATION;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_MULTISOCKET_H_

115
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@ -1,115 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD ACPI PState option API.
*
* Contains structures and values used to control the PStates option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _OPTION_PSTATE_H_
#define _OPTION_PSTATE_H_
#include "cpuPstateTables.h"
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
typedef AGESA_STATUS OPTION_SSDT_FEATURE (
IN AMD_CONFIG_PARAMS *StdHeader,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN OUT VOID **AcpiPstatePtr
);
typedef UINT32 OPTION_ACPI_FEATURE (
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN PSTATE_LEVELING *PStateLevelingBuffer,
IN OUT VOID **AcpiPStatePtr,
IN UINT8 LocalApicId,
IN AMD_CONFIG_PARAMS *StdHeader
);
typedef AGESA_STATUS OPTION_PSTATE_GATHER (
IN AMD_CONFIG_PARAMS *StdHeader,
IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr
);
typedef AGESA_STATUS OPTION_PSTATE_LEVELING (
IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr,
IN AMD_CONFIG_PARAMS *StdHeader
);
#define PSTATE_STRUCT_VERSION 0x01
/// Indirection vectors for POST/PEI PState code
typedef struct {
UINT16 OptPstateVersion; ///< revision of this structure
OPTION_PSTATE_GATHER *PstateGather; ///< vector for data gathering routine
OPTION_PSTATE_LEVELING *PstateLeveling; ///< vector for leveling routine
} OPTION_PSTATE_POST_CONFIGURATION;
/// Indirection vectors for LATE/DXE PState code
typedef struct {
UINT16 OptPstateVersion; ///< revision of this structure
OPTION_SSDT_FEATURE *SsdtFeature; ///< vector for routine to generate SSDT
OPTION_ACPI_FEATURE *PstateFeature; ///< vector for routine to generate ACPI PState Objects
OPTION_ACPI_FEATURE *CstateFeature; ///< vector for routine to generate ACPI CState Objects
BOOLEAN CfgPstatePpc; ///< boolean for creating _PPC method
BOOLEAN CfgPstatePct; ///< boolean for creating _PCT method
BOOLEAN CfgPstatePsd; ///< boolean for creating _PSD method
BOOLEAN CfgPstatePss; ///< boolean for creating _PSS method
BOOLEAN CfgPstateXpss; ///< boolean for creating _XPSS method
} OPTION_PSTATE_LATE_CONFIGURATION;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_PSTATE_H_

96
src/vendorcode/amd/agesa/f12/Include/OptionSlit.h
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@ -1,96 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD SLIT option API.
*
* Contains structures and values used to control the SLIT option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _OPTION_SLIT_H_
#define _OPTION_SLIT_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
/**
* Create the ACPI System Locality Distance Information Table.
*
*/
typedef AGESA_STATUS OPTION_SLIT_FEATURE (
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN OUT VOID **SlitPtr
);
/**
* Clean up DRAM used during SLIT creation.
*
*/
typedef AGESA_STATUS OPTION_SLIT_RELEASE_BUFFER (
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
#define SLIT_STRUCT_VERSION 0x01
/// The Option Configuration of SLIT
typedef struct {
UINT16 OptSlitVersion; ///< The version number of SLIT
OPTION_SLIT_FEATURE *SlitFeature; ///< The Option Feature of SLIT
OPTION_SLIT_RELEASE_BUFFER *SlitReleaseBuffer; ///< Release buffer
} OPTION_SLIT_CONFIGURATION;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_SLIT_H_

82
src/vendorcode/amd/agesa/f12/Include/OptionSrat.h
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@ -1,82 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD SRAT option API.
*
* Contains structures and values used to control the SRAT option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _OPTION_SRAT_H_
#define _OPTION_SRAT_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
typedef AGESA_STATUS OPTION_SRAT_FEATURE (
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN OUT VOID **SratPtr
);
#define SRAT_STRUCT_VERSION 0x01
/// The Option Configuration of SRAT
typedef struct {
UINT16 OptSratVersion; ///< The version number of SRAT
OPTION_SRAT_FEATURE *SratFeature; ///< The Option Feature of SRAT
} OPTION_SRAT_CONFIGURATION;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_SRAT_H_

83
src/vendorcode/amd/agesa/f12/Include/OptionWhea.h
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@ -1,83 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD WHEA option API.
*
* Contains structures and values used to control the WHEA option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _OPTION_WHEA_H_
#define _OPTION_WHEA_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
typedef AGESA_STATUS OPTION_WHEA_FEATURE (
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN OUT VOID **WheaMcePtr,
IN OUT VOID **WheaCmcPtr
);
#define WHEA_STRUCT_VERSION 0x01
/// The Option Configuration of WHEA
typedef struct {
UINT16 OptWheaVersion; ///< The version number of WHEA
OPTION_WHEA_FEATURE *WheaFeature; ///< The Option Feature of WHEA
} OPTION_WHEA_CONFIGURATION;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_WHEA_H_

67
src/vendorcode/amd/agesa/f12/Include/Options.h
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@ -1,67 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AGESA options structures
*
* Contains options control structures for the AGESA build options
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTIONS_H_
#define _OPTIONS_H_
/**
* Provide topology limits for loops and runtime, based on supported families.
*/
typedef struct {
UINT32 PlatformNumberOfSockets; ///< The limit to the number of processors based on
///< supported families and other build options.
UINT32 PlatformNumberOfModules; ///< The limit to the number of modules in a processor, based
///< on supported families.
} OPTIONS_CONFIG_TOPOLOGY;
/**
* Dispatch Table.
*
* The push high dispatcher uses this table to find what entries are currently in the build image.
*/
typedef struct {
UINT32 FunctionId; ///< The function id specified.
IMAGE_ENTRY EntryPoint; ///< The corresponding entry point to call.
} DISPATCH_TABLE;
#endif // _OPTIONS_H_

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@ -1,109 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD HyperTransport option API.
*
* Contains option pre-compile logic. This file is used by the options
* installer and internally by the HT code initializers.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _OPTION_HT_H_
#define _OPTION_HT_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
/**
* Provide HT build option results
*/
typedef struct {
CONST BOOLEAN IsUsingRecoveryHt; ///< Manual BUID Swap List processing should assume that HT Recovery was used.
CONST BOOLEAN IsSetHtCrcFlood; ///< Enable setting of HT CRC Flood.
///< Build-time only customizable - @BldCfgItem{BLDCFG_SET_HTCRC_SYNC_FLOOD}
CONST BOOLEAN IsUsingUnitIdClumping; ///< Enable automatically HT Spec compliant Unit Id Clumping.
///< Build-time only customizable - @BldCfgItem{BLDCFG_USE_UNIT_ID_CLUMPING}
CONST AMD_HT_INTERFACE *HtOptionPlatformDefaults; ///< A set of build time options for HT constructor.
CONST VOID *HtOptionInternalInterface; ///< Use this internal interface initializer.
CONST VOID *HtOptionInternalFeatures; ///< Use this internal feature set initializer.
CONST VOID *HtOptionFamilyNorthbridgeList; ///< Use this list of northbridge initializers.
CONST UINT8 *CONST *HtOptionBuiltinTopologies; ///< Use this list of built-in topologies.
} OPTION_HT_CONFIGURATION;
typedef AGESA_STATUS
F_OPTION_HT_INIT_RESET (
IN AMD_CONFIG_PARAMS *StdHeader,
IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface
);
typedef F_OPTION_HT_INIT_RESET *PF_OPTION_HT_INIT_RESET;
typedef AGESA_STATUS
F_OPTION_HT_RESET_CONSTRUCTOR (
IN AMD_CONFIG_PARAMS *StdHeader,
IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface
);
typedef F_OPTION_HT_RESET_CONSTRUCTOR *PF_OPTION_HT_RESET_CONSTRUCTOR;
/**
* Provide HT reset initialization build option results
*/
typedef struct {
PF_OPTION_HT_INIT_RESET HtInitReset; ///< Method: HT reset initialization.
PF_OPTION_HT_RESET_CONSTRUCTOR HtResetConstructor; ///< Method: HT reset initialization.
} OPTION_HT_INIT_RESET;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_HT_H_

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/* $NoKeywords:$ */
/**
* @file
*
* Create outline and references for Build Configuration and Options Component mainpage documentation.
*
* Design guides, maintenance guides, and general documentation, are
* collected using this file onto the documentation mainpage.
* This file contains doxygen comment blocks, only.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Documentation
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/**
* @page optionmain Build Configuration and Options Documentation
*
* Additional documentation for the Build Configuration and Options component consists of
*
* - Introduction and Overview to Build Options
* - @subpage platforminstall "Platform Build Options"
* - @subpage bldcfg "Build Configuration Item Cross Reference"
* - @subpage examplecustomizations "Customization Examples"
* - Maintenance Guides:
* - For debug of the Options system, use compiler options
* @n <tt> /P /EP /C /FAs </tt> @n
* PreProcessor output is produced in an .i file in the directory where the project
* file is located.
* - Design Guides:
* - add here >>>
*
*/
/**
* @page platforminstall Platform Build Options.
*
* Build options are boolean constants. The purpose of build options is to remove code
* from the build to reduce the overall code size present in the ROM image. Unless
* otherwise specified, the default action is to include all options. If a build option is
* not specifically listed as disabled, then it is included into the build.
*
* The documented build options are imported from a user controlled file for
* processing. The build options for all platform solutions are listed below:
*
* @anchor BLDOPT_REMOVE_UDIMMS_SUPPORT
* @li @e BLDOPT_REMOVE_UDIMMS_SUPPORT @n
* If unbuffered DIMMs are NOT expected to be required in the system, the code that
* handles unbuffered DIMMs can be removed from the build.
*
* @anchor BLDOPT_REMOVE_RDIMMS_SUPPORT
* @li @e BLDOPT_REMOVE_RDIMMS_SUPPORT @n
* If registered DIMMs are NOT expected to be required in the system, the code
* that handles registered DIMMs can be removed from the build.
*
* @anchor BLDOPT_REMOVE_LRDIMMS_SUPPORT
* @li @e BLDOPT_REMOVE_LRDIMMS_SUPPORT @n
* If Load Reduced DIMMs are NOT expected to be required in the system, the code
* that handles Load Reduced DIMMs can be removed from the build.
*
* @note The above three options operate independently from each other; however, at
* least one of the unbuffered , registered or load reduced DIMM options must be present in the build.
*
* @anchor BLDOPT_REMOVE_ECC_SUPPORT
* @li @e BLDOPT_REMOVE_ECC_SUPPORT @n
* Use this option to remove the code for Error Checking & Correction.
*
* @anchor BLDOPT_REMOVE_BANK_INTERLEAVE
* @li @e BLDOPT_REMOVE_BANK_INTERLEAVE @n
* Interleaving is a mechanism to do performance fine tuning. This option
* interleaves memory between banks on a DIMM.
*
* @anchor BLDOPT_REMOVE_DCT_INTERLEAVE
* @li @e BLDOPT_REMOVE_DCT_INTERLEAVE @n
* Interleaving is a mechanism to do performance fine tuning. This option
* interleaves memory from two DRAM controllers.
*
* @anchor BLDOPT_REMOVE_NODE_INTERLEAVE
* @li @e BLDOPT_REMOVE_NODE_INTERLEAVE @n
* Interleaving is a mechanism to do performance fine tuning. This option
* interleaves memory from two HyperTransport nodes.
*
* @anchor BLDOPT_REMOVE_PARALLEL_TRAINING
* @li @e BLDOPT_REMOVE_PARALLEL_TRAINING @n
* For multi-socket systems, training memory in parallel can reduce the time
* needed to boot.
*
* @anchor BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT
* @li @e BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT @n
* Online Spare support is removed by this option.
*
* @anchor BLDOPT_REMOVE_MULTISOCKET_SUPPORT
* @li @e BLDOPT_REMOVE_MULTISOCKET_SUPPORT @n
* Many systems use only a single socket and may benefit in code space to remove
* this code. However, certain processors have multiple HyperTransport nodes
* within a single socket. For these processors, the multi-node support is
* required and this option has no effect.
*
* @anchor BLDOPT_REMOVE_ACPI_PSTATES
* @li @e BLDOPT_REMOVE_ACPI_PSTATES @n
* This option removes the code that generates the ACPI tables used in power
* management.
*
* @anchor BLDOPT_REMOVE_SRAT
* @li @e BLDOPT_REMOVE_SRAT @n
* This option removes the code that generates the SRAT tables used in performance
* tuning.
*
* @anchor BLDOPT_REMOVE_SLIT
* @li @e BLDOPT_REMOVE_SLIT @n
* This option removes the code that generates the SLIT tables used in performance
* tuning.
*
* @anchor BLDOPT_REMOVE_WHEA
* @li @e BLDOPT_REMOVE_WHEA @n
* This option removes the code that generates the WHEA tables used in error
* handling and reporting.
*
* @anchor BLDOPT_REMOVE_DMI
* @li @e BLDOPT_REMOVE_DMI @n
* This option removes the code that generates the DMI tables used in system
* management.
*
* @anchor BLDOPT_REMOVE_DQS_TRAINING
* @li @e BLDOPT_REMOVE_DQS_TRAINING @n
* This option removes the code used in memory performance tuning.
*
* @anchor BLDOPT_REMOVE_EARLY_SAMPLES
* @li @e BLDOPT_REMOVE_EARLY_SAMPLES @n
* Special support for Early Samples is included. Default setting is FALSE.
*
* @anchor BLDOPT_REMOVE_HT_ASSIST
* @li @e BLDOPT_REMOVE_HT_ASSIST @n
* This option removes the code which implements the HT Assist feature.
*
* @anchor BLDOPT_REMOVE_ATM_MODE
* @li @e BLDOPT_REMOVE_ATM_MODE @n
* This option removes the code which implements the ATM feature.
*
* @anchor BLDOPT_REMOVE_MSG_BASED_C1E
* @li @e BLDOPT_REMOVE_MSG_BASED_C1E @n
* This option removes the code which implements the Message Based C1e feature.
*
* @anchor BLDOPT_REMOVE_C6_STATE
* @li @e BLDOPT_REMOVE_C6_STATE @n
* This option removes the code which implements the C6 C-state feature.
*
* @anchor BLDOPT_REMOVE_MEM_RESTORE_SUPPORT
* @li @e BLDOPT_REMOVE_MEM_RESTORE_SUPPORT @n
* This option removes the memory context restore feature.
*
* @anchor BLDOPT_REMOVE_FAMILY_10_SUPPORT
* @li @e BLDOPT_REMOVE_FAMILY_10_SUPPORT @n
* If the package contains support for family 10h processors, remove that support.
*
* @anchor BLDOPT_REMOVE_FAMILY_12_SUPPORT
* @li @e BLDOPT_REMOVE_FAMILY_12_SUPPORT @n
* If the package contains support for family 10h processors, remove that support.
*
* @anchor BLDOPT_REMOVE_FAMILY_14_SUPPORT
* @li @e BLDOPT_REMOVE_FAMILY_14_SUPPORT @n
* If the package contains support for family 14h processors, remove that support.
*
* @anchor BLDOPT_REMOVE_FAMILY_15_SUPPORT
* @li @e BLDOPT_REMOVE_FAMILY_15_SUPPORT @n
* If the package contains support for family 15h processors, remove that support.
*
* @anchor BLDOPT_REMOVE_AM3_SOCKET_SUPPORT
* @li @e BLDOPT_REMOVE_AM3_SOCKET_SUPPORT @n
* This option removes the code which implements support for processors packaged for AM3 sockets.
*
* @anchor BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT
* @li @e BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT @n
* This option removes the code which implements support for processors packaged for ASB2 sockets.
*
* @anchor BLDOPT_REMOVE_C32_SOCKET_SUPPORT
* @li @e BLDOPT_REMOVE_C32_SOCKET_SUPPORT @n
* This option removes the code which implements support for processors packaged for C32 sockets.
*
* @anchor BLDOPT_REMOVE_FM1_SOCKET_SUPPORT
* @li @e BLDOPT_REMOVE_FM1_SOCKET_SUPPORT @n
* This option removes the code which implements support for processors packaged for FM1 sockets.
*
* @anchor BLDOPT_REMOVE_FP1_SOCKET_SUPPORT
* @li @e BLDOPT_REMOVE_FP1_SOCKET_SUPPORT @n
* This option removes the code which implements support for processors packaged for FP1 sockets.
*
* @anchor BLDOPT_REMOVE_FS1_SOCKET_SUPPORT
* @li @e BLDOPT_REMOVE_FS1_SOCKET_SUPPORT @n
* This option removes the code which implements support for processors packaged for FS1 sockets.
*
* @anchor BLDOPT_REMOVE_FT1_SOCKET_SUPPORT
* @li @e BLDOPT_REMOVE_FT1_SOCKET_SUPPORT @n
* This option removes the code which implements support for processors packaged for FT1 sockets.
*
* @anchor BLDOPT_REMOVE_G34_SOCKET_SUPPORT
* @li @e BLDOPT_REMOVE_G34_SOCKET_SUPPORT @n
* This option removes the code which implements support for processors packaged for G34 sockets.
*
* @anchor BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT
* @li @e BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT @n
* This option removes the code which implements support for processors packaged for S1G3 sockets.
*
* @anchor BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT
* @li @e BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT @n
* This option removes the code which implements support for processors packaged for S1G4 sockets.
*/
/**
* @page examplecustomizations Customization Examples
*
* The Addendum \<plat\>Options.c file for each platform contains the minimum required
* customizations for that platform. That is, it contains settings which would be needed
* to boot a SimNow! bsd for that platform.
* However, each individual product based on that platform will have customizations necessary for
* that hardware. Since the actual customizations needed vary so much, they are not included in
* the \<plat\>Options.c. This section provides examples of useful customizations that you can use or
* modify to suit your needs.
*
* @par
*
* Source for the examples shown can be found at Addendum\\Examples. @n
*
* - @ref DeemphasisExamples "Deemphasis List Examples"
* - @ref FrequencyLimitExamples "Frequency Limit Examples"
* - @ref PerfPerWattHt "A performance-per-watt optimization Example"
*
* @anchor DeemphasisExamples
* @par Deemphasis List Examples
*
* These examples customize PLATFORM_CONFIGURATION.PlatformDeemphasisList.
* Source for the deemphasis list examples can be found in DeemphasisExamples.c. @n
* @dontinclude DeemphasisExamples.c
* <ul>
* <li>
* The following deemphasis list provides an example for a 2P MCM Max Performance configuration.
* High Speed HT frequencies are supported. There is only one non-coherent chain. Note the technique of
* putting specified link matches before all uses of match any. It often works well to specify the non-coherent links
* and use match any for the coherent links.
* @skip DinarDeemphasisList
* @until {
* The non-coherent chain can run up to 2600 MHz. The chain is located on Socket 0, package Link 2.
* @until {
* @line }
* @line {
* @line }
* The coherent links can run up to 3200 MHz.
* @until HT_FREQUENCY_MAX
* @line }
* end of list:
* @until }
* Make this list the build time customized deemphasis list.
* @line define
*
* </li><li>
*
* The following deemphasis list provides an example for a 4P MCM Max Performance configuration.
* This system has a backplane with connectors for CPU cards and an IO board. So trace lengths are long.
* There can be one to four IO Chains, depending on the IO board.
* @skipline DoubloonDeemphasisList
* @until DoubloonDeemphasisList
*
* </li><li>
*
* The following deemphasis list further illustrates complex coherent system deemphasis. This is the same
* Dinar system as in an earlier example, but this time all the coherent links are explicitly customized (as
* might be needed if each link has unique characterization). For this example, we skip the non-coherent chains.
* (A real system would have to include them, see example above.)
* @skip DinarPerLinkDeemphasisList
* @until {
* Provide deemphasis settings for the 16 bit, ganged, links, Socket 0 links 0, 1 and Socket 1 links 1 and 2.
* Provide entries to customize all HT3 frequencies at which the links may run. This example covers all HT3 speeds.
* @until {
* @until DcvLevelMinus6
* @until DcvLevelMinus6
* @until DcvLevelMinus6
* @until DcvLevelMinus6
* Link 3 on both sockets connects different internal die: sublink 0 connects the internal node zeroes, and
* sublink 1 connects the internal node ones. So the link is unganged and both sublinks must be specifically
* customized.
* @until {
* @until DcvLevelMinus6
* @until DcvLevelMinus6
* @until DcvLevelMinus6
* @until DcvLevelMinus6
* end of list:
* @until define
*
* </ul>
*
* @anchor FrequencyLimitExamples
* @par Frequency Limit Examples
*
* These examples customize AMD_HT_INTERFACE.CpuToCpuPcbLimitsList and AMD_HT_INTERFACE.IoPcbLimitsList.
* Source for the frequency limit examples can be found in FrequencyLimitExamples.c. @n
* @dontinclude FrequencyLimitExamples.c
* <ul>
* <li>
* The following list provides an example for limiting all coherent links to non-extended frequencies,
* that is, to 2600 MHz or less.
* @skipline NonExtendedCpuToCpuLimitList
* @until {
* Provide the limit customization. Match links from any socket, any package link, to any socket, any package link. Width is not limited.
* @until HT_FREQUENCY_LIMIT_2600M
* End of list:
* @until ;
* Customize the build to use this cpu to cpu frequency limit.
* @until NonExtendedCpuToCpuLimitList
* @n </li>
* <li>
* The following list provides an example for limiting all coherent links to HT 1 frequencies,
* that is, to 1000 MHz or less. This is sometimes useful for test and debug.
* @skipline Ht1CpuToCpuLimitList
* @until Ht1CpuToCpuLimitList
* @n </li>
* <li>
* The following list provides an example for limiting all non-coherent links to 2400 MHz or less.
* The chain is matched by host processor Socket and package Link. The depth can be used to select a particular device
* to device link on the chain. In this example, the chain consists of a single cave device and depth can be set to match any.
* @skipline No2600MhzIoLimitList
* @until No2600MhzIoLimitList
* @n </li>
* <li>
* The following list provides an example for limiting all non-coherent links to the minimum HT 3 frequency,
* that is, to 1200 MHz or less. This can be useful for test and debug.
* @skipline MinHt3IoLimitList
* @until MinHt3IoLimitList
* @n </li>
*
* </ul>
*
* @anchor PerfPerWattHt
* @par Performance-per-Watt Optimization Example
*
* This example customizes AMD_HT_INTERFACE.SkipRegangList.
* Source for the Performance-per-watt Optimization example can be found in PerfPerWatt.c. @n
* @dontinclude PerfPerWatt.c
* To implement a performance-per-watt optimization for MCM processors, use the skip regang structure shown. @n
* @skipline PerfPerWatt
* @until PerfPerWatt
*
*/

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/* $NoKeywords:$ */
/**
* @file
*
* AMD Platform Specific Memory Configuration
*
* Contains Definitions and Macros for control of AGESA Memory code on a per platform basis
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 47408 $ @e \$Date: 2011-02-19 00:56:31 +0800 (Sat, 19 Feb 2011) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _PLATFORM_MEMORY_CONFIGURATION_H_
#define _PLATFORM_MEMORY_CONFIGURATION_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
#ifndef PSO_ENTRY
#define PSO_ENTRY UINT8
#endif
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* PLATFORM SPECIFIC MEMORY DEFINITIONS
*----------------------------------------------------------------------------------------
*/
///
/// Memory Speed and DIMM Population Masks
///
///< DDR Speed Masks
///< Specifies the DDR Speed on a memory channel
///
#define ANY_SPEED 0xFFFFFFFF
#define DDR400 ((UINT32) 1 << (DDR400_FREQUENCY / 66))
#define DDR533 ((UINT32) 1 << (DDR533_FREQUENCY / 66))
#define DDR667 ((UINT32) 1 << (DDR667_FREQUENCY / 66))
#define DDR800 ((UINT32) 1 << (DDR800_FREQUENCY / 66))
#define DDR1066 ((UINT32) 1 << (DDR1066_FREQUENCY / 66))
#define DDR1333 ((UINT32) 1 << (DDR1333_FREQUENCY / 66))
#define DDR1600 ((UINT32) 1 << (DDR1600_FREQUENCY / 66))
#define DDR1866 ((UINT32) 1 << (DDR1866_FREQUENCY / 66))
#define DDR2133 ((UINT32) 1 << (DDR2133_FREQUENCY / 66))
#define DDR2400 ((UINT32) 1 << (DDR2400_FREQUENCY / 66))
///
///< DIMM POPULATION MASKS
///< Specifies the DIMM Population on a channel (can be added together to specify configuration).
///< ex. SR_DIMM0 + SR_DIMM1 : Single Rank Dimm in slot 0 AND Slot 1
///< SR_DIMM0 + DR_DIMM0 + SR_DIMM1 +DR_DIMM1 : Single OR Dual rank in Slot 0 AND Single OR Dual rank in Slot 1
///
#define ANY_ 0xFF ///< Any dimm configuration the current channel
#define SR_DIMM0 0x0001 ///< Single rank dimm in slot 0 on the current channel
#define SR_DIMM1 0x0010 ///< Single rank dimm in slot 1 on the current channel
#define SR_DIMM2 0x0100 ///< Single rank dimm in slot 2 on the current channel
#define SR_DIMM3 0x1000 ///< Single rank dimm in slot 3 on the current channel
#define DR_DIMM0 0x0002 ///< Dual rank dimm in slot 0 on the current channel
#define DR_DIMM1 0x0020 ///< Dual rank dimm in slot 1 on the current channel
#define DR_DIMM2 0x0200 ///< Dual rank dimm in slot 2 on the current channel
#define DR_DIMM3 0x2000 ///< Dual rank dimm in slot 3 on the current channel
#define QR_DIMM0 0x0004 ///< Quad rank dimm in slot 0 on the current channel
#define QR_DIMM1 0x0040 ///< Quad rank dimm in slot 1 on the current channel
#define QR_DIMM2 0x0400 ///< Quad rank dimm in slot 2 on the current channel
#define QR_DIMM3 0x4000 ///< Quad rank dimm in slot 3 on the current channel
#define ANY_DIMM0 0x000F ///< Any Dimm combination in slot 0 on the current channel
#define ANY_DIMM1 0x00F0 ///< Any Dimm combination in slot 1 on the current channel
#define ANY_DIMM2 0x0F00 ///< Any Dimm combination in slot 2 on the current channel
#define ANY_DIMM3 0xF000 ///< Any Dimm combination in slot 3 on the current channel
///
///< Number of Dimms on the current channel
///< This is a mask used to indicate the number of dimms in a channel
///< They can be added to indicate multiple conditions (i.e 1 OR 2 Dimms)
///
#define ANY_NUM 0xFF ///< Any number of Dimms
#define NO_DIMM 0x00 ///< No Dimms present
#define ONE_DIMM 0x01 ///< One dimm Poulated on the current channel
#define TWO_DIMM 0x02 ///< Two dimms Poulated on the current channel
#define THREE_DIMM 0x04 ///< Three dimms Poulated on the current channel
#define FOUR_DIMM 0x08 ///< Four dimms Poulated on the current channel
/*----------------------------------------------------------------------------------------
*
* Platform Specific Override Definitions for Socket, Channel and Dimm
* This indicates where a platform override will be applied.
*
*----------------------------------------------------------------------------------------
*/
///
///< SOCKET MASKS
///< Indicates associated processor sockets to apply override settings
///
#define ANY_SOCKET 0xFF ///< Apply to all sockets
#define SOCKET0 0x01 ///< Apply to socket 0
#define SOCKET1 0x02 ///< Apply to socket 1
#define SOCKET2 0x04 ///< Apply to socket 2
#define SOCKET3 0x08 ///< Apply to socket 3
#define SOCKET4 0x10 ///< Apply to socket 4
#define SOCKET5 0x20 ///< Apply to socket 5
#define SOCKET6 0x40 ///< Apply to socket 6
#define SOCKET7 0x80 ///< Apply to socket 7
///
///< CHANNEL MASKS
///< Indicates Memory channels where override should be applied
///
#define ANY_CHANNEL 0xFF ///< Apply to all Memory channels
#define CHANNEL_A 0x01 ///< Apply to Channel A
#define CHANNEL_B 0x02 ///< Apply to Channel B
#define CHANNEL_C 0x04 ///< Apply to Channel C
#define CHANNEL_D 0x08 ///< Apply to Channel D
///
/// DIMM MASKS
/// Indicates Dimm Slots where override should be applied
///
#define ALL_DIMMS 0xFF ///< Apply to all dimm slots
#define DIMM0 0x01 ///< Apply to Dimm Slot 0
#define DIMM1 0x02 ///< Apply to Dimm Slot 1
#define DIMM2 0x04 ///< Apply to Dimm Slot 2
#define DIMM3 0x08 ///< Apply to Dimm Slot 3
///
/// REGISTER ACCESS MASKS
/// Not supported as an at this time
///
#define ACCESS_NB0 0x0
#define ACCESS_NB1 0x1
#define ACCESS_NB2 0x2
#define ACCESS_NB3 0x3
#define ACCESS_NB4 0x4
#define ACCESS_PHY 0x5
#define ACCESS_DCT_XT 0x6
/*----------------------------------------------------------------------------------------
*
* Platform Specific Overriding Table Definitions
*
*----------------------------------------------------------------------------------------
*/
#define PSO_END 0 ///< Table End
#define PSO_CKE_TRI 1 ///< CKE Tristate Map
#define PSO_ODT_TRI 2 ///< ODT Tristate Map
#define PSO_CS_TRI 3 ///< CS Tristate Map
#define PSO_MAX_DIMMS 4 ///< Max Dimms per channel
#define PSO_CLK_SPEED 5 ///< Clock Speed
#define PSO_DIMM_TYPE 6 ///< Dimm Type
#define PSO_MEMCLK_DIS 7 ///< MEMCLK Disable Map
#define PSO_MAX_CHNLS 8 ///< Max Channels per Socket
#define PSO_BUS_SPEED 9 ///< Max Memory Bus Speed
#define PSO_MAX_CHIPSELS 10 ///< Max Chipsel per Channel
#define PSO_MEM_TECH 11 ///< Channel Memory Type
#define PSO_WL_SEED 12 ///< DDR3 Write Levelization Seed delay
#define PSO_RXEN_SEED 13 ///< Hardwared based RxEn seed
#define PSO_NO_LRDIMM_CS67_ROUTING 14 ///< CS6 and CS7 are not Routed to all Memoy slots on a channel for LRDIMMs
#define PSO_SOLDERED_DOWN_SODIMM_TYPE 15 ///< Soldered down SODIMM type
#define PSO_LVDIMM_VOLT1_5_SUPPORT 16 ///< Force LvDimm voltage to 1.5V
/*----------------------------------
* CONDITIONAL PSO SPECIFIC ENTRIES
*---------------------------------*/
// Condition Types
#define CONDITIONAL_PSO_MIN 100 ///< Start of Conditional Entry Types
#define PSO_CONDITION_AND 100 ///< And Block - Start of Conditional block
#define PSO_CONDITION_LOC 101 ///< Location - Specify Socket, Channel, Dimms to be affected
#define PSO_CONDITION_SPD 102 ///< SPD - Specify a specific SPD value on a Dimm on the channel
#define PSO_CONDITION_REG 103 // Reserved
#define PSO_CONDITION_MAX 103 ///< End Of Condition Entry Types
// Action Types
#define PSO_ACTION_MIN 120 ///< Start of Action Entry Types
#define PSO_ACTION_ODT 120 ///< ODT values to override
#define PSO_ACTION_ADDRTMG 121 ///< Address/Timing values to override
#define PSO_ACTION_ODCCONTROL 122 ///< ODC Control values to override
#define PSO_ACTION_SLEWRATE 123 ///< Slew Rate value to override
#define PSO_ACTION_REG 124 // Reserved
#define PSO_ACTION_SPEEDLIMIT 125 ///< Memory Bus speed Limit based on configuration
#define PSO_ACTION_MAX 125 ///< End of Action Entry Types
#define CONDITIONAL_PSO_MAX 139 ///< End of Conditional Entry Types
/*----------------------------------------------------------------------------------------
* CONDITIONAL OVERRIDE TABLE MACROS
*----------------------------------------------------------------------------------------
*/
#define MEMCLK_DIS_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map) \
PSO_MEMCLK_DIS, 10, SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map
#define CKE_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map) \
PSO_CKE_TRI, 4, SocketID, ChannelID, Bit0Map, Bit1Map
#define ODT_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map) \
PSO_ODT_TRI, 6, SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map
#define CS_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map) \
PSO_CS_TRI, 10, SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map
#define NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) \
PSO_MAX_DIMMS, 3, SocketID, ChannelID, NumberOfDimmSlotsPerChannel
#define NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) \
PSO_MAX_CHIPSELS, 3, SocketID, ChannelID, NumberOfChipSelectsPerChannel
#define NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) \
PSO_MAX_CHNLS, 3, SocketID, ANY_CHANNEL, NumberOfChannelsPerSocket
#define OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, TimingMode, BusSpeed) \
PSO_BUS_SPEED, 10, SocketID, ChannelID, TimingMode, (TimingMode >> 8), (TimingMode >> 16), (TimingMode >> 24), \
BusSpeed, (BusSpeed >> 8), (BusSpeed >> 16), (BusSpeed >> 24)
#define DRAM_TECHNOLOGY(SocketID, MemTechType) \
PSO_MEM_TECH, 6, SocketID, ANY_CHANNEL, MemTechType, (MemTechType >> 8), (MemTechType >> 16), (MemTechType >> 24)
#define WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \
Byte6Seed, Byte7Seed, ByteEccSeed) \
PSO_WL_SEED, 11, SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \
Byte6Seed, Byte7Seed, ByteEccSeed
#define HW_RXEN_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \
Byte6Seed, Byte7Seed, ByteEccSeed) \
PSO_RXEN_SEED, 20, SocketID, ChannelID, Byte0Seed, (Byte0Seed >> 8), Byte1Seed, (Byte1Seed >> 8), Byte2Seed, (Byte2Seed >> 8), \
Byte3Seed, (Byte3Seed >> 8), Byte4Seed, (Byte4Seed >> 8), Byte5Seed, (Byte5Seed >> 8), Byte6Seed, (Byte6Seed >> 8), \
Byte7Seed, (Byte7Seed >> 8), ByteEccSeed, (ByteEccSeed >> 8)
#define NO_LRDIMM_CS67_ROUTING(SocketID, ChannelID) \
PSO_NO_LRDIMM_CS67_ROUTING, 3, SocketID, ChannelID, TRUE
#define SOLDERED_DOWN_SODIMM_TYPE(SocketID, ChannelID) \
PSO_SOLDERED_DOWN_SODIMM_TYPE, 3, SocketID, ChannelID, TRUE
#define LVDIMM_FORCE_VOLT1_5_FOR_D0 \
PSO_LVDIMM_VOLT1_5_SUPPORT, 3, ANY_SOCKET, ANY_CHANNEL, TRUE
/*----------------------------------------------------------------------------------------
* CONDITIONAL OVERRIDE TABLE MACROS
*----------------------------------------------------------------------------------------
*/
#define CONDITION_AND \
PSO_CONDITION_AND, 0
#define COND_LOC(SocketMsk, ChannelMsk, DimmMsk) \
PSO_CONDITION_LOC, 3, SocketMsk, ChannelMsk, DimmMsk
#define COND_SPD(Byte, Mask, Value) \
PSO_CONDITION_SPD, 3, Byte, Mask, Value
#define COND_REG(Access, Offset, Mask, Value) \
PSO_CONDITION_REG, 11, Access, (Offset & 0x0FF), (Offset >> 8), \
((Mask) & 0x0FF), (((Mask) >> 8) & 0x0FF), (((Mask) >> 16) & 0x0FF), (((Mask) >> 24) & 0x0FF), \
((Value) & 0x0FF), (((Value) >> 8) & 0x0FF), (((Value) >> 16) & 0x0FF), (((Value) >> 24) & 0x0FF)
#define ACTION_ODT(Frequency, Dimms, QrDimms, DramOdt, QrDramOdt, DramDynOdt) \
PSO_ACTION_ODT, 9, \
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), ((Frequency >> 24)& 0x0FF), \
Dimms, QrDimms, DramOdt, QrDramOdt, DramDynOdt
#define ACTION_ADDRTMG(Frequency, DimmConfig, AddrTmg) \
PSO_ACTION_ADDRTMG, 10, \
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
(AddrTmg & 0x0FF), ((AddrTmg >> 8)& 0x0FF), ((AddrTmg >> 16)& 0x0FF), ((AddrTmg >> 24)& 0x0FF)
#define ACTION_ODCCTRL(Frequency, DimmConfig, OdcCtrl) \
PSO_ACTION_ODCCONTROL, 10, \
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
(OdcCtrl & 0x0FF), ((OdcCtrl >> 8)& 0x0FF), ((OdcCtrl >> 16)& 0x0FF), ((OdcCtrl >> 24)& 0x0FF)
#define ACTION_SLEWRATE(Frequency, DimmConfig, SlewRate) \
PSO_ACTION_SLEWRATE, 10, \
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
(SlewRate & 0x0FF), ((SlewRate >> 8)& 0x0FF), ((SlewRate >> 16)& 0x0FF), ((SlewRate >> 24)& 0x0FF)
#define ACTION_SPEEDLIMIT(DimmConfig, Dimms, SpeedLimit15, SpeedLimit135, SpeedLimit125) \
PSO_ACTION_SPEEDLIMIT, 9, \
((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), Dimms, \
(SpeedLimit15 & 0x0FF), ((SpeedLimit15 >> 8)& 0x0FF), \
(SpeedLimit135 & 0x0FF), ((SpeedLimit135 >> 8)& 0x0FF), \
(SpeedLimit125 & 0x0FF), ((SpeedLimit125 >> 8)& 0x0FF)
/*----------------------------------------------------------------------------------------
* END OF CONDITIONAL OVERRIDE TABLE MACROS
*----------------------------------------------------------------------------------------
*/
#endif // _PLATFORM_MEMORY_CONFIGURATION_H_

162
src/vendorcode/amd/agesa/f12/Include/Topology.h
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@ -1,162 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Topology interface definitions.
*
* Contains AMD AGESA internal interface for topology related data which
* is consumed by code other than HyperTransport init (and produced by
* HyperTransport init.)
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _TOPOLOGY_H_
#define _TOPOLOGY_H_
// Defines for limiting data structure maximum allocation and limit checking.
#define MAX_NODES 8
#define MAX_SOCKETS MAX_NODES
#define MAX_DIES 2
// Defines useful with package link
#define HT_LIST_MATCH_INTERNAL_LINK_0 0xFA
#define HT_LIST_MATCH_INTERNAL_LINK_1 0xFB
#define HT_LIST_MATCH_INTERNAL_LINK_2 0xFC
/**
* Hop Count Table.
* This is a heap data structure. The Hops array is filled as a size x size matrix.
* The unused space, if any, is all at the end.
*/
typedef struct {
UINT8 Size; ///< The row and column size of actual hop count data */
UINT8 Hops[MAX_NODES * MAX_NODES]; ///< Room for a dynamic two dimensional array of [size][size] */
} HOP_COUNT_TABLE;
/**
* Socket and Module to Node Map Item.
* Provide the Node Id and core id range for each module in each processor.
*/
typedef struct {
UINT8 Node; ///< The module's Node id.
UINT8 LowCore; ///< The lowest processor core id for this module.
UINT8 HighCore; ///< The highest processor core id for this module.
UINT8 EnabledComputeUnits; ///< The value of Enabled for this processor module.
UINT8 DualCoreComputeUnits; ///< The value of DualCore for this processor module.
} SOCKET_DIE_TO_NODE_ITEM;
/**
* Socket and Module to Node Map.
* This type is a pointer to the actual map, it can be used for a struct item or
* for typecasting a heap buffer pointer.
*/
typedef SOCKET_DIE_TO_NODE_ITEM (*SOCKET_DIE_TO_NODE_MAP)[MAX_SOCKETS][MAX_DIES];
/**
* Node id to Socket Die Map Item.
*/
typedef struct {
UINT8 Socket; ///< socket of the processor containing the Node.
UINT8 Die; ///< the module in the processor which is Node.
} NODE_TO_SOCKET_DIE_ITEM;
/**
* Node id to Socket Die Map.
*/
typedef NODE_TO_SOCKET_DIE_ITEM (*NODE_TO_SOCKET_DIE_MAP)[MAX_NODES];
/**
* Provide AP core with socket and node context at start up.
* This information is posted to the AP cores using a register as a mailbox.
*/
typedef struct {
UINT32 Node:4; ///< The node id of Core's node.
UINT32 Socket:4; ///< The socket of this Core's node.
UINT32 Module:2; ///< The internal module number for Core's node.
UINT32 ModuleType:2; ///< Single Module = 0, Multi-module = 1.
UINT32 :20; ///< Reserved
} AP_MAIL_INFO_FIELDS;
/**
* AP info fields can be written and read to a register.
*/
typedef union {
UINT32 Info; ///< Just a number for register access, or opaque passing.
AP_MAIL_INFO_FIELDS Fields; ///< access to the info fields.
} AP_MAIL_INFO;
/**
* Provide AP core with system degree and system core number at start up.
* This information is posted to the AP cores using a register as a mailbox.
*/
typedef struct {
UINT32 SystemDegree:3; ///< The number of connected links
UINT32 :3; ///< Reserved
UINT32 HeapIndex:6; ///< The zero-based system core number
UINT32 :20; ///< Reserved
} AP_MAIL_EXT_INFO_FIELDS;
/**
* AP info fields can be written and read to a register.
*/
typedef union {
UINT32 Info; ///< Just a number for register access, or opaque passing.
AP_MAIL_EXT_INFO_FIELDS Fields; ///< access to the info fields.
} AP_MAIL_EXT_INFO;
/**
* AP Info mailbox set.
*/
typedef struct {
AP_MAIL_INFO ApMailInfo; ///< The AP mail info
AP_MAIL_EXT_INFO ApMailExtInfo; ///< The extended AP mail info
} AP_MAILBOXES;
/**
* Provide a northbridge to package mapping for link assignments.
*
*/
typedef struct {
UINT8 Link; ///< The Node's link
UINT8 Module; ///< The internal module position of Node
UINT8 PackageLink; ///< The corresponding package link
} PACKAGE_HTLINK_MAP_ITEM;
/**
* A Processor's complete set of link assignments
*/
typedef PACKAGE_HTLINK_MAP_ITEM (*PACKAGE_HTLINK_MAP)[];
#endif // _TOPOLOGY_H_

135
src/vendorcode/amd/agesa/f12/Legacy/Proc/Dispatcher.c
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@ -1,135 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD binary block interface
*
* Contains the block entry function dispatcher
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Legacy
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ***************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Dispatcher.h"
#include "Options.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE LEGACY_PROC_DISPATCHER_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
extern CONST DISPATCH_TABLE DispatchTable[];
extern AMD_MODULE_HEADER mCpuModuleID;
/*---------------------------------------------------------------------------------------*/
/**
* The Dispatcher is the entry point into the AGESA software. It takes a function
* number as entry parameter in order to invoke the published function
*
* @param[in,out] ConfigPtr
*
* @return AGESA Status.
*
*/
AGESA_STATUS
CALLCONV
AmdAgesaDispatcher (
IN OUT VOID *ConfigPtr
)
{
AGESA_STATUS Status;
MODULE_ENTRY ModuleEntry;
DISPATCH_TABLE *Entry;
Status = AGESA_UNSUPPORTED;
ModuleEntry = NULL;
Entry = (DISPATCH_TABLE *) DispatchTable;
while (Entry->FunctionId != 0) {
if ((((AMD_CONFIG_PARAMS *) ConfigPtr)->Func) == Entry->FunctionId) {
Status = Entry->EntryPoint (ConfigPtr);
break;
}
Entry++;
}
// 2. Try next dispatcher if possible, and we have not already got status back
if ((mCpuModuleID.NextBlock != NULL) && (Status == AGESA_UNSUPPORTED)) {
ModuleEntry = (MODULE_ENTRY) (intptr_t) mCpuModuleID.NextBlock->ModuleDispatcher;
if (ModuleEntry != NULL) {
Status = (*ModuleEntry) (ConfigPtr);
}
}
return (Status);
}
/*---------------------------------------------------------------------------------------*/
/**
* The host environment interface of callout.
*
* @param[in] Func
* @param[in] Data
* @param[in,out] ConfigPtr
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
CALLCONV
AmdAgesaCallout (
IN UINT32 Func,
IN UINTN Data,
IN OUT VOID *ConfigPtr
)
{
UINT32 Result;
Result = AGESA_UNSUPPORTED;
if (((AMD_CONFIG_PARAMS *) ConfigPtr)->CalloutPtr == NULL) {
return Result;
}
Result = (((AMD_CONFIG_PARAMS *) ConfigPtr)->CalloutPtr) (Func, Data, ConfigPtr);
return (Result);
}

3
src/vendorcode/amd/agesa/f12/Legacy/Proc/Makefile.inc
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@ -1,3 +0,0 @@
libagesa-y += Dispatcher.c
libagesa-y += agesaCallouts.c
libagesa-y += hobTransfer.c

420
src/vendorcode/amd/agesa/f12/Legacy/Proc/agesaCallouts.c
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@ -1,420 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD CPU AGESA Callout Functions
*
* Contains code to set / get useful platform information.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Common
* @e \$Revision: 49633 $ @e \$Date: 2011-03-26 06:52:29 +0800 (Sat, 26 Mar 2011) $
*
*/
/*****************************************************************************
* AMD Generic Encapsulated Software Architecture
*
* Description: agesaCallouts.c - AGESA Call out functions
*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "Dispatcher.h"
#include "cpuServices.h"
#include "Ids.h"
#include "Filecode.h"
#define FILECODE LEGACY_PROC_AGESACALLOUTS_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S - (AGESA ONLY)
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
*
* Call the host environment interface to do the warm or cold reset.
*
* @param[in] ResetType Warm or Cold Reset is requested
* @param[in,out] StdHeader Config header
*
*/
VOID
AgesaDoReset (
IN UINTN ResetType,
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
WARM_RESET_REQUEST Request;
// Clear warm request bit and set state bits to the current post stage
GetWarmResetFlag (StdHeader, &Request);
Request.RequestBit = FALSE;
Request.StateBits = Request.PostStage;
SetWarmResetFlag (StdHeader, &Request);
Status = AmdAgesaCallout (AGESA_DO_RESET, (UINT32)ResetType, (VOID *) StdHeader);
}
/*---------------------------------------------------------------------------------------*/
/**
*
* Call the host environment interface to allocate buffer in main system memory.
*
* @param[in] FcnData
* @param[in,out] AllocParams Heap manager parameters
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaAllocateBuffer (
IN UINTN FcnData,
IN OUT AGESA_BUFFER_PARAMS *AllocParams
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_ALLOCATE_BUFFER, (UINT32)FcnData, (VOID *) AllocParams);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to deallocate buffer in main system memory.
*
* @param[in] FcnData
* @param[in,out] DeallocParams Heap Manager parameters
*
* @return The AGESA Status returned from the callout.
*/
AGESA_STATUS
AgesaDeallocateBuffer (
IN UINTN FcnData,
IN OUT AGESA_BUFFER_PARAMS *DeallocParams
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_DEALLOCATE_BUFFER, (UINT32)FcnData, (VOID *) DeallocParams);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
*
* Call the host environment interface to Locate buffer Pointer in main system memory
*
* @param[in] FcnData
* @param[in,out] LocateParams Heap manager parameters
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaLocateBuffer (
IN UINTN FcnData,
IN OUT AGESA_BUFFER_PARAMS *LocateParams
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_LOCATE_BUFFER, (UINT32)FcnData, (VOID *) LocateParams);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to launch APs
*
* @param[in] ApicIdOfCore
* @param[in,out] LaunchApParams
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaRunFcnOnAp (
IN UINTN ApicIdOfCore,
IN AP_EXE_PARAMS *LaunchApParams
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_RUNFUNC_ONAP, (UINT32)ApicIdOfCore, (VOID *) LaunchApParams);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to read an SPD's content.
*
* @param[in] FcnData
* @param[in,out] ReadSpd
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaReadSpd (
IN UINTN FcnData,
IN OUT AGESA_READ_SPD_PARAMS *ReadSpd
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_READ_SPD, (UINT32)FcnData, ReadSpd);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to read an SPD's content.
*
* @param[in] FcnData
* @param[in,out] ReadSpd
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaReadSpdRecovery (
IN UINTN FcnData,
IN OUT AGESA_READ_SPD_PARAMS *ReadSpd
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_READ_SPD_RECOVERY, (UINT32)FcnData, ReadSpd);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to provide a user hook opportunity.
*
* @param[in] FcnData
* @param[in,out] MemData
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaHookBeforeDramInitRecovery (
IN UINTN FcnData,
IN OUT MEM_DATA_STRUCT *MemData
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, (UINT32)FcnData, MemData);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to provide a user hook opportunity.
*
* @param[in] SocketIdModuleId - (SocketID << 8) | ModuleId
* @param[in,out] MemData
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaHookBeforeDramInit (
IN UINTN SocketIdModuleId,
IN OUT MEM_DATA_STRUCT *MemData
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_HOOKBEFORE_DRAM_INIT, (UINT32)SocketIdModuleId, MemData);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to provide a user hook opportunity.
*
* @param[in] SocketIdModuleId - (SocketID << 8) | ModuleId
* @param[in,out] MemData
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaHookBeforeDQSTraining (
IN UINTN SocketIdModuleId,
IN OUT MEM_DATA_STRUCT *MemData
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_HOOKBEFORE_DQS_TRAINING, (UINT32)SocketIdModuleId, MemData);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to provide a user hook opportunity.
*
* @param[in] FcnData
* @param[in,out] MemData
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaHookBeforeExitSelfRefresh (
IN UINTN FcnData,
IN OUT MEM_DATA_STRUCT *MemData
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_HOOKBEFORE_EXIT_SELF_REF, (UINT32)FcnData, MemData);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to provide a user hook opportunity.
*
* @param[in] Data
* @param[in,out] IdsCalloutData
*
* @return The AGESA Status returned from the callout.
*
*/
/*
AGESA_STATUS
AgesaGetIdsData (
IN UINTN Data,
IN OUT IDS_CALLOUT_STRUCT *IdsCalloutData
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_GET_IDS_INIT_DATA, (UINT32)Data, IdsCalloutData);
return Status;
}
*/
/*----------------------------------------------------------------------------------------*/
/**
* PCIE slot reset control
*
*
*
* @param[in] FcnData Function data
* @param[in] ResetInfo Reset information
* @retval Status Agesa status
*/
AGESA_STATUS
AgesaPcieSlotResetControl (
IN UINTN FcnData,
IN PCIe_SLOT_RESET_INFO *ResetInfo
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_GNB_PCIE_SLOT_RESET, (UINT32) FcnData, ResetInfo);
return Status;
}
/*----------------------------------------------------------------------------------------*/
/**
* OEM callout function for FCH data override
*
*
* @param[in] FchData FCH data pointer
* @retval Status This feature is not supported
*/
AGESA_STATUS
AgesaFchOemCallout (
IN VOID *FchData
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_FCH_OEM_CALLOUT, (UINT32) 0, FchData);
return Status;
}

392
src/vendorcode/amd/agesa/f12/Legacy/Proc/hobTransfer.c
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@ -1,392 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Hob Transfer functions.
*
* Contains code that copy Heap to temp memory or main memory.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "cpuRegisters.h"
#include "GeneralServices.h"
#include "cpuServices.h"
#include "cpuCacheInit.h"
#include "cpuFamilyTranslation.h"
#include "heapManager.h"
#include "cpuLateInit.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE LEGACY_PROC_HOBTRANSFER_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P U B L I C F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
extern BUILD_OPT_CFG UserOptions;
/* -----------------------------------------------------------------------------*/
/**
*
* CopyHeapToTempRamAtPost
*
* This function copies BSP heap content to RAM
*
* @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct.
*
* @retval AGESA_STATUS
*
*/
AGESA_STATUS
CopyHeapToTempRamAtPost (
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 *BaseAddressInCache;
UINT8 *BaseAddressInTempMem;
UINT8 *Source;
UINT8 *Destination;
UINT8 AlignTo16ByteInCache;
UINT8 AlignTo16ByteInTempMem;
UINT8 Ignored;
UINT32 SizeOfNodeData;
UINT32 TotalSize;
UINT32 HeapRamFixMtrr;
UINT32 HeapRamVariableMtrr;
UINT32 HeapInCacheOffset;
UINT64 MsrData;
UINT64 VariableMtrrBase;
UINT64 VariableMtrrMask;
UINTN AmdHeapRamAddress;
AGESA_STATUS IgnoredStatus;
BUFFER_NODE *HeapInCache;
BUFFER_NODE *HeapInTempMem;
HEAP_MANAGER *HeapManagerInCache;
HEAP_MANAGER *HeapManagerInTempMem;
CACHE_INFO *CacheInfoPtr;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
AmdHeapRamAddress = (UINTN) UserOptions.CfgHeapDramAddress;
//
//If the user define address above 1M, Mem Init has already set
//whole available memory as WB cacheable.
//
if (AmdHeapRamAddress < 0x100000) {
// Region below 1MB
// Fixed MTRR region
// turn on modification bit
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
MsrData |= 0x80000;
LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader);
if (AmdHeapRamAddress >= 0xC0000) {
//
// 0xC0000 ~ 0xFFFFF
//
HeapRamFixMtrr = (UINT32) (AMD_MTRR_FIX4k_C0000 + (((AmdHeapRamAddress >> 16) & 0x3) * 2));
MsrData = (UINT64)AMD_MTRR_FIX4K_UC_DRAM;
LibAmdMsrWrite (HeapRamFixMtrr, &MsrData, StdHeader);
LibAmdMsrWrite ((HeapRamFixMtrr + 1), &MsrData, StdHeader);
} else if (AmdHeapRamAddress >= 0x80000) {
//
// 0x80000~0xBFFFF
//
HeapRamFixMtrr = (UINT32) (AMD_MTRR_FIX16k_80000 + ((AmdHeapRamAddress >> 17) & 0x1));
MsrData = (UINT64)AMD_MTRR_FIX16K_UC_DRAM;
LibAmdMsrWrite (HeapRamFixMtrr, &MsrData, StdHeader);
} else {
//
// 0x0 ~ 0x7FFFF
//
LibAmdMsrRead (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader);
MsrData = MsrData & (~(0xFF << (8 * ((AmdHeapRamAddress >> 16) & 0x7))));
MsrData = MsrData | (AMD_MTRR_FIX64K_UC_DRAM << (8 * ((AmdHeapRamAddress >> 16) & 0x7)));
LibAmdMsrWrite (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader);
}
// Turn on MTRR enable bit and turn off modification bit
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
MsrData |= 0x40000;
MsrData &= 0xFFFFFFFFFFF7FFFFull;
LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader);
} else {
// Region above 1MB
// Variable MTRR region
// Get family specific cache Info
GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (const VOID **) &CacheInfoPtr, &Ignored, StdHeader);
// Find an empty MTRRphysBase/MTRRphysMask
for (HeapRamVariableMtrr = AMD_MTRR_VARIABLE_HEAP_BASE;
HeapRamVariableMtrr >= AMD_MTRR_VARIABLE_BASE0;
HeapRamVariableMtrr--) {
LibAmdMsrRead (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader);
LibAmdMsrRead ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader);
if ((VariableMtrrBase == 0) && (VariableMtrrMask == 0)) {
break;
}
}
if (HeapRamVariableMtrr < AMD_MTRR_VARIABLE_BASE0) {
// All variable MTRR is used.
ASSERT (FALSE);
}
// Set variable MTRR base and mask
// If the address ranges of two or more MTRRs overlap
// and if at least one of the memory types is UC, the UC memory type is used.
VariableMtrrBase = (UINT64) (AmdHeapRamAddress & CacheInfoPtr->HeapBaseMask);
VariableMtrrMask = CacheInfoPtr->VariableMtrrHeapMask & (UINT64)AMD_HEAP_MTRR_MASK;
LibAmdMsrWrite (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader);
LibAmdMsrWrite ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader);
}
// Copying Heap content
if (IsBsp (StdHeader, &IgnoredStatus)) {
TotalSize = sizeof (HEAP_MANAGER);
SizeOfNodeData = 0;
AlignTo16ByteInTempMem = 0;
BaseAddressInCache = (UINT8 *) (intptr_t) StdHeader->HeapBasePtr;
HeapManagerInCache = (HEAP_MANAGER *) BaseAddressInCache;
HeapInCacheOffset = HeapManagerInCache->FirstActiveBufferOffset;
HeapInCache = (BUFFER_NODE *) (BaseAddressInCache + HeapInCacheOffset);
BaseAddressInTempMem = (UINT8 *) (intptr_t) UserOptions.CfgHeapDramAddress;
HeapManagerInTempMem = (HEAP_MANAGER *) BaseAddressInTempMem;
HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize);
// copy heap from cache to temp memory.
// only heap with persist great than HEAP_LOCAL_CACHE will be copied.
// Note: Only copy heap with persist greater than HEAP_LOCAL_CACHE.
while (HeapInCacheOffset != AMD_HEAP_INVALID_HEAP_OFFSET) {
if (HeapInCache->Persist > HEAP_LOCAL_CACHE) {
AlignTo16ByteInCache = HeapInCache->PadSize;
AlignTo16ByteInTempMem = (UINT8) ((0x10 - (((UINTN) (VOID *) HeapInTempMem + sizeof (BUFFER_NODE) + SIZE_OF_SENTINEL) & 0xF)) & 0xF);
SizeOfNodeData = HeapInCache->BufferSize - AlignTo16ByteInCache;
TotalSize = (UINT32) (TotalSize + sizeof (BUFFER_NODE) + SizeOfNodeData + AlignTo16ByteInTempMem);
Source = (UINT8 *) HeapInCache + sizeof (BUFFER_NODE) + AlignTo16ByteInCache;
Destination = (UINT8 *) HeapInTempMem + sizeof (BUFFER_NODE) + AlignTo16ByteInTempMem;
LibAmdMemCopy (HeapInTempMem, HeapInCache, sizeof (BUFFER_NODE), StdHeader);
LibAmdMemCopy (Destination, Source, SizeOfNodeData, StdHeader);
HeapInTempMem->OffsetOfNextNode = TotalSize;
HeapInTempMem->BufferSize = SizeOfNodeData + AlignTo16ByteInTempMem;
HeapInTempMem->PadSize = AlignTo16ByteInTempMem;
HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize);
}
HeapInCacheOffset = HeapInCache->OffsetOfNextNode;
HeapInCache = (BUFFER_NODE *) (BaseAddressInCache + HeapInCacheOffset);
}
// initialize heap manager
if (TotalSize == sizeof (HEAP_MANAGER)) {
// heap is empty
HeapManagerInTempMem->UsedSize = sizeof (HEAP_MANAGER);
HeapManagerInTempMem->FirstActiveBufferOffset = AMD_HEAP_INVALID_HEAP_OFFSET;
HeapManagerInTempMem->FirstFreeSpaceOffset = sizeof (HEAP_MANAGER);
} else {
// heap is NOT empty
HeapManagerInTempMem->UsedSize = TotalSize;
HeapManagerInTempMem->FirstActiveBufferOffset = sizeof (HEAP_MANAGER);
HeapManagerInTempMem->FirstFreeSpaceOffset = TotalSize;
HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize - SizeOfNodeData - AlignTo16ByteInTempMem - sizeof (BUFFER_NODE));
HeapInTempMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET;
HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize);
}
// heap signature
HeapManagerInCache->Signature = 0x00000000;
HeapManagerInTempMem->Signature = HEAP_SIGNATURE_VALID;
// Free space node
HeapInTempMem->BufferSize = (UINT32) (AMD_HEAP_SIZE_PER_CORE - TotalSize);
HeapInTempMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET;
}
return AGESA_SUCCESS;
}
/* -----------------------------------------------------------------------------*/
/**
*
* CopyHeapToMainRamAtPost
*
* This function copies Temp Ram heap content to Main Ram
*
* @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct.
*
* @retval AGESA_STATUS
*
*/
AGESA_STATUS
CopyHeapToMainRamAtPost (
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 *BaseAddressInTempMem;
UINT8 *BaseAddressInMainMem;
UINT8 *Source;
UINT8 *Destination;
UINT8 AlignTo16ByteInTempMem;
UINT8 AlignTo16ByteInMainMem;
UINT8 Ignored;
UINT32 SizeOfNodeData;
UINT32 TotalSize;
UINT32 HeapInTempMemOffset;
UINT32 HeapRamVariableMtrr;
UINT64 VariableMtrrBase;
UINT64 VariableMtrrMask;
AGESA_STATUS IgnoredStatus;
BUFFER_NODE *HeapInTempMem;
BUFFER_NODE *HeapInMainMem;
HEAP_MANAGER *HeapManagerInTempMem;
HEAP_MANAGER *HeapManagerInMainMem;
AGESA_BUFFER_PARAMS AgesaBuffer;
CACHE_INFO *CacheInfoPtr;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
if (IsBsp (StdHeader, &IgnoredStatus)) {
TotalSize = sizeof (HEAP_MANAGER);
SizeOfNodeData = 0;
AlignTo16ByteInMainMem = 0;
BaseAddressInTempMem = (UINT8 *) (intptr_t) StdHeader->HeapBasePtr;
HeapManagerInTempMem = (HEAP_MANAGER *) (intptr_t) StdHeader->HeapBasePtr;
HeapInTempMemOffset = HeapManagerInTempMem->FirstActiveBufferOffset;
HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + HeapInTempMemOffset);
AgesaBuffer.StdHeader = *StdHeader;
AgesaBuffer.BufferHandle = AMD_HEAP_IN_MAIN_MEMORY_HANDLE;
AgesaBuffer.BufferLength = AMD_HEAP_SIZE_PER_CORE;
if (AgesaAllocateBuffer (0, &AgesaBuffer) != AGESA_SUCCESS) {
return AGESA_ERROR;
}
BaseAddressInMainMem = (UINT8 *) AgesaBuffer.BufferPointer;
HeapManagerInMainMem = (HEAP_MANAGER *) BaseAddressInMainMem;
HeapInMainMem = (BUFFER_NODE *) (BaseAddressInMainMem + TotalSize);
LibAmdMemFill (BaseAddressInMainMem, 0x00, AMD_HEAP_SIZE_PER_CORE, StdHeader);
// copy heap from temp memory to main memory.
// only heap with persist great than HEAP_TEMP_MEM will be copied.
// Note: Only copy heap buffers with persist greater than HEAP_TEMP_MEM.
while (HeapInTempMemOffset != AMD_HEAP_INVALID_HEAP_OFFSET) {
if (HeapInTempMem->Persist > HEAP_TEMP_MEM) {
AlignTo16ByteInTempMem = HeapInTempMem->PadSize;
AlignTo16ByteInMainMem = (UINT8) ((0x10 - (((UINTN) (VOID *) HeapInMainMem + sizeof (BUFFER_NODE) + SIZE_OF_SENTINEL) & 0xF)) & 0xF);
SizeOfNodeData = HeapInTempMem->BufferSize - AlignTo16ByteInTempMem;
TotalSize = (UINT32) (TotalSize + sizeof (BUFFER_NODE) + SizeOfNodeData + AlignTo16ByteInMainMem);
Source = (UINT8 *) HeapInTempMem + sizeof (BUFFER_NODE) + AlignTo16ByteInTempMem;
Destination = (UINT8 *) HeapInMainMem + sizeof (BUFFER_NODE) + AlignTo16ByteInMainMem;
LibAmdMemCopy (HeapInMainMem, HeapInTempMem, sizeof (BUFFER_NODE), StdHeader);
LibAmdMemCopy (Destination, Source, SizeOfNodeData, StdHeader);
HeapInMainMem->OffsetOfNextNode = TotalSize;
HeapInMainMem->BufferSize = SizeOfNodeData + AlignTo16ByteInMainMem;
HeapInMainMem->PadSize = AlignTo16ByteInMainMem;
HeapInMainMem = (BUFFER_NODE *) (BaseAddressInMainMem + TotalSize);
}
HeapInTempMemOffset = HeapInTempMem->OffsetOfNextNode;
HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + HeapInTempMemOffset);
}
// initialize heap manager
if (TotalSize == sizeof (HEAP_MANAGER)) {
// heap is empty
HeapManagerInMainMem->UsedSize = sizeof (HEAP_MANAGER);
HeapManagerInMainMem->FirstActiveBufferOffset = AMD_HEAP_INVALID_HEAP_OFFSET;
HeapManagerInMainMem->FirstFreeSpaceOffset = sizeof (HEAP_MANAGER);
} else {
// heap is NOT empty
HeapManagerInMainMem->UsedSize = TotalSize;
HeapManagerInMainMem->FirstActiveBufferOffset = sizeof (HEAP_MANAGER);
HeapManagerInMainMem->FirstFreeSpaceOffset = TotalSize;
HeapInMainMem = (BUFFER_NODE *) (BaseAddressInMainMem + TotalSize - SizeOfNodeData - AlignTo16ByteInMainMem - sizeof (BUFFER_NODE));
HeapInMainMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET;
HeapInMainMem = (BUFFER_NODE *) (BaseAddressInMainMem + TotalSize);
}
// heap signature
HeapManagerInTempMem->Signature = 0x00000000;
HeapManagerInMainMem->Signature = HEAP_SIGNATURE_VALID;
// Free space node
HeapInMainMem->BufferSize = AMD_HEAP_SIZE_PER_CORE - TotalSize;
HeapInMainMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET;
}
// if address of heap in temp memory is above 1M, then we must used one variable MTRR.
if (StdHeader->HeapBasePtr >= 0x100000) {
// Find out which variable MTRR was used in CopyHeapToTempRamAtPost.
GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **) &FamilySpecificServices, StdHeader);
FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (const VOID **) &CacheInfoPtr, &Ignored, StdHeader);
for (HeapRamVariableMtrr = AMD_MTRR_VARIABLE_HEAP_BASE;
HeapRamVariableMtrr >= AMD_MTRR_VARIABLE_BASE0;
HeapRamVariableMtrr--) {
LibAmdMsrRead (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader);
LibAmdMsrRead ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader);
if ((VariableMtrrBase == (UINT64) (StdHeader->HeapBasePtr & CacheInfoPtr->HeapBaseMask)) &&
(VariableMtrrMask == (UINT64) (CacheInfoPtr->VariableMtrrHeapMask & (UINT64) AMD_HEAP_MTRR_MASK))) {
break;
}
}
if (HeapRamVariableMtrr >= AMD_MTRR_VARIABLE_BASE0) {
// Clear variable MTRR which set in CopyHeapToTempRamAtPost.
VariableMtrrBase = 0;
VariableMtrrMask = 0;
LibAmdMsrWrite (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader);
LibAmdMsrWrite ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader);
}
}
return AGESA_SUCCESS;
}

119
src/vendorcode/amd/agesa/f12/MainPage.h
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@ -1,119 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Create outline and references for mainpage documentation.
*
* Design guides, maintenance guides, and general documentation, are
* collected using this file onto the documentation mainpage.
* This file contains doxygen comment blocks, only.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Documentation
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/**
* @mainpage
*
* The design and maintenance documentation for AGESA Sample Code is organized as
* follows. On this page, you can reference design guides, maintenance guides, and
* general documentation. Detailed Data Structure, Function, and Interface documentation
* may be found using the Data Structures or Files tabs. See Related Pages for a
* Release content summary, and, if this is not a production release, lists of To Do's,
* Deprecated items, etc.
*
* @subpage starthere "Start Here - Initial Porting and Integration."
*
* @subpage optionmain "Build Configuration and Options Guides and Documentation."
*
* @subpage commonmain "Processor Common Component Guides and Documentation."
*
* @subpage cpumain "CPU Component Guides and Documentation."
*
* @subpage htmain "HT Component Guides and Documentation."
*
* @subpage memmain "MEM Component Guides and Documentation."
*
* @subpage gnbmain "GNB Component Documentation."
*
* @subpage idsmain "IDS Component Guides and Documentation."
*
* @subpage recoverymain "Recovery Component Guides and Documentation."
*
*/
/**
* @page starthere Initial Porting and Integration
*
* @par Basic Check List
*
* <ul>
* <li> Copy the \<plat\>Options.c file from the Addendum directory to the platform tip build directory.
* AMD recommends the use of a sub-directory named AGESA to contain these files and the build output files.
* <li> Copy the OptionsIds.h content in the spec to OptionsIds.h in the platform build tip directory
* and make changes to enable the IDS support desired. It is highly recommended to set the following for
* initial integration and development:@n
* @code
* #define IDSOPT_IDS_ENABLED TRUE
* #define IDSOPT_ERROR_TRAP_ENABLED TRUE
* #define IDSOPT_ASSERT_ENABLED TRUE
* @endcode
* <li> Edit and modify the option selections in those two files to meet the needs of the specific platform.
* <li> Set the environment variable AGESA_ROOT to the root folder of the AGESA code.
* <li> Set the environment variable AGESA_OptsDir the platform build tip AGESA directory.
* <li> Generate the doxygen documentation or locate the file arch2008.chm within your AGESA release package.
* </ul>
*
* @par Debugging Using ASSERT and IDS_ERROR_TRAP
*
* While AGESA code uses ::ASSERT and ::IDS_ERROR_TRAP to check for internal errors, these macros can also
* catch and assist debug of wrapper and platform BIOS issues.
*
* When an ::ASSERT fails or an ::IDS_ERROR_TRAP is executed, the AGESA code will enter a halt loop and display a
* Stop Code. A Stop Code is eight hex digits. The first (most significant) four are the FILECODE.
* FILECODEs can be looked up in Filecode.h to determine which file contains the stop macro. Each file has a
* unique code value.
* The least significant digits are the line number in that file.
* For example, 0210 means the macro is on line two hundred ten.
* (see ::IdsErrorStop for more details on stop code display.)
*
* Enabling ::ASSERT and ::IDS_ERROR_TRAP ensure errors are caught and also provide a useful debug assist.
* Comments near each macro use will describe the nature of the error and typical wrapper errors or other
* root causes.
*
* After your wrapper consistently executes ::ASSERT and ::IDS_ERROR_TRAP stop free, you can disable them in
* OptionsIds.h, except for regression testing. IDS is not expected to be enabled in production BIOS builds.
*
*/

49
src/vendorcode/amd/agesa/f12/Makefile.inc
View File

@ -1,49 +0,0 @@
#*****************************************************************************
#
# Copyright (c) 2011, Advanced Micro Devices, Inc.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# * Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# * Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# * Neither the name of Advanced Micro Devices, Inc. nor the names of
# its contributors may be used to endorse or promote products derived
# from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
# DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#*****************************************************************************
# AGESA V5 Files
AGESA_ROOT = src/vendorcode/amd/agesa/f12
AGESA_AUTOINCLUDES := $(shell find $(AGESA_ROOT)/Proc -type d -exec echo -n "-I"{}" " \;)
AGESA_INC = -I$(src)/vendorcode/amd/include
AGESA_INC += -I$(AGESA_ROOT)
AGESA_INC += -I$(AGESA_ROOT)/../common
AGESA_INC += -I$(AGESA_ROOT)/Include
AGESA_INC += -I$(src)/mainboard/$(MAINBOARDDIR) # OptionsIds.h
BUILDOPTS_INCLUDES = -I$(AGESA_ROOT)/Config $(AGESA_INC) $(AGESA_AUTOINCLUDES)
CPPFLAGS_x86_32 += $(AGESA_INC)
CPPFLAGS_x86_64 += $(AGESA_INC)
#######################################################################
subdirs-y += Legacy/Proc
subdirs-y += $(dir $(shell cd $(dir); find Proc -name Makefile.inc))

193
src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12C6State.c
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@ -1,193 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_12 C6 C-state feature support functions.
*
* Provides the functions necessary to initialize the C6 feature.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F12
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "cpuRegisters.h"
#include "cpuFeatures.h"
#include "cpuC6State.h"
#include "cpuF12PowerMgmt.h"
#include "OptionFamily12hEarlySample.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_CPU_FAMILY_0X12_F12C6STATE_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
extern F12_ES_C6_SUPPORT F12EarlySampleC6Support;
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
* Is C6 supported on this CPU
*
* @param[in] C6Services Pointer to this CPU's C6 family services.
* @param[in] Socket This core's zero-based socket number.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] StdHeader Config Handle for library, services.
*
* @retval TRUE C6 state is supported.
* @retval FALSE C6 state is not supported.
*
*/
BOOLEAN
STATIC
F12IsC6Supported (
IN C6_FAMILY_SERVICES *C6Services,
IN UINT32 Socket,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 LocalPciRegister;
BOOLEAN IsEnabled;
PCI_ADDR PciAddress;
IsEnabled = TRUE;
PciAddress.AddressValue = CPU_STATE_PM_CTRL1_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
if ((((CPU_STATE_PM_CTRL1_REGISTER *) &LocalPciRegister)->CoreC6Cap == 0) &&
(((CPU_STATE_PM_CTRL1_REGISTER *) &LocalPciRegister)->PkgC6Cap == 0)) {
IsEnabled = FALSE;
}
return IsEnabled;
}
/*---------------------------------------------------------------------------------------*/
/**
* Enable C6 on a family 12h CPU.
*
* @param[in] C6Services Pointer to this CPU's C6 family services.
* @param[in] EntryPoint Timepoint designator.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] StdHeader Config Handle for library, services.
*
* @return AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
F12InitializeC6 (
IN C6_FAMILY_SERVICES *C6Services,
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 i;
UINT32 MaxEnabledPstate;
UINT32 LocalPciRegister;
UINT64 LocalMsrRegister;
PCI_ADDR PciAddress;
for (i = MSR_PSTATE_7; i > MSR_PSTATE_0; i--) {
LibAmdMsrRead (i, &LocalMsrRegister, StdHeader);
if (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) {
break;
}
}
MaxEnabledPstate = i - MSR_PSTATE_0;
if ((EntryPoint & CPU_FEAT_AFTER_PM_INIT) != 0) {
F12EarlySampleC6Support.F12InitializeC6 (StdHeader);
} else {
// Ensure D18F2x118[C6DramLock] and D18F4x12C[C6Base] are programmed.
PciAddress.AddressValue = MEM_CFG_LOW_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
ASSERT (((MEM_CFG_LOW_REGISTER *) &LocalPciRegister)->C6DramLock == 1);
PciAddress.AddressValue = C6_BASE_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
ASSERT (((C6_BASE_REGISTER *) &LocalPciRegister)->C6Base != 0);
// If PC6 is supported, program D18F4x1AC[PstateIdCoreOffExit] to
// the index of lowest-performance Pstate with MSRC001_00[6B:64]
// [PstateEn] == 1 on core 0.
PciAddress.AddressValue = CPU_STATE_PM_CTRL1_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
if (((CPU_STATE_PM_CTRL1_REGISTER *) &LocalPciRegister)->PkgC6Cap == 1) {
((CPU_STATE_PM_CTRL1_REGISTER *) &LocalPciRegister)->PstateIdCoreOffExit = MaxEnabledPstate;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
}
// Program D18F4x118 to 0000_0101h.
PciAddress.AddressValue = CSTATE_CTRL1_PCI_ADDR;
LocalPciRegister = 0x00000101;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
}
return AGESA_SUCCESS;
}
CONST C6_FAMILY_SERVICES ROMDATA F12C6Support =
{
0,
F12IsC6Supported,
F12InitializeC6,
ReloadMicrocodePatchAfterMemInit
};

171
src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12Cpb.c
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@ -1,171 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_12 CPB Initialization
*
* Enables core performance boost.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F12
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "cpuFamilyTranslation.h"
#include "cpuF12PowerMgmt.h"
#include "GnbRegistersLN.h"
#include "NbSmuLib.h"
#include "cpuFeatures.h"
#include "cpuCpb.h"
#include "OptionFamily12hEarlySample.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_CPU_FAMILY_0X12_F12CPB_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
//extern F12_ES_CPB_SUPPORT F12EarlySampleCpbSupport;
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
* BSC entry point for checking whether or not CPB is supported.
*
* @param[in] CpbServices The current CPU's family services.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] Socket Zero based socket number to check.
* @param[in] StdHeader Config handle for library and services.
*
* @retval TRUE CPB is supported.
* @retval FALSE CPB is not supported.
*
*/
BOOLEAN
STATIC
F12IsCpbSupported (
IN CPB_FAMILY_SERVICES *CpbServices,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN UINT32 Socket,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
PCI_ADDR PciAddress;
D18F4x15C_STRUCT CpbControl;
PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl.Value, StdHeader);
return (BOOLEAN) (CpbControl.Field.NumBoostStates != 0);
}
/*---------------------------------------------------------------------------------------*/
/**
* BSC entry point for enabling Core Performance Boost.
*
* Set up D18F4x15C[BoostSrc] and start the PDMs according to the BKDG.
*
* @param[in] CpbServices The current CPU's family services.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] EntryPoint Current CPU feature dispatch point.
* @param[in] Socket Zero based socket number to check.
* @param[in] StdHeader Config handle for library and services.
*
* @retval AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
F12InitializeCpb (
IN CPB_FAMILY_SERVICES *CpbServices,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN UINT64 EntryPoint,
IN UINT32 Socket,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
PCI_ADDR PciAddress;
D18F4x15C_STRUCT CpbControl;
SMUx0B_x8580_STRUCT SMUx0Bx8580;
if ((EntryPoint & CPU_FEAT_BEFORE_PM_INIT) != 0) {
// F12EarlySampleCpbSupport.F12CpbInitHook (StdHeader);
PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl.Value, StdHeader);
CpbControl.Field.BoostSrc = 1;
IDS_OPTION_HOOK (IDS_CPB_CTRL, &CpbControl.Value, StdHeader);
LibAmdPciWrite (AccessWidth32, PciAddress, &CpbControl.Value, StdHeader);
} else if ((EntryPoint & CPU_FEAT_INIT_LATE_END) != 0) {
// Ensure that the recommended settings have been programmed into SMUx0B_x8580, then
// interrupt the SMU with service index 12h.
SMUx0Bx8580.Value = 0;
SMUx0Bx8580.Field.PdmPeriod = 0x1388;
SMUx0Bx8580.Field.PdmUnit = 1;
SMUx0Bx8580.Field.PdmCacEn = 1;
SMUx0Bx8580.Field.PdmEn = 1;
NbSmuRcuRegisterWrite (SMUx0B_x8580_ADDRESS, &SMUx0Bx8580.Value, 1, TRUE, StdHeader);
NbSmuServiceRequest (0x12, TRUE, StdHeader);
}
return AGESA_SUCCESS;
}
CONST CPB_FAMILY_SERVICES ROMDATA F12CpbSupport =
{
0,
F12IsCpbSupported,
F12InitializeCpb
};

278
src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12IoCstate.c
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@ -1,278 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_12 IO C-state feature support functions.
*
* Provides the functions necessary to initialize the IO C-state feature.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F12
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "cpuRegisters.h"
#include "cpuFamilyTranslation.h"
#include "cpuFeatures.h"
#include "cpuIoCstate.h"
#include "cpuF12PowerMgmt.h"
#include "cpuLateInit.h"
#include "cpuApicUtilities.h"
#include "cpuServices.h"
#include "CommonReturns.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_CPU_FAMILY_0X12_F12IOCSTATE_FILECODE
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
STATIC
F12InitializeIoCstateOnCore (
IN VOID *CstateBaseMsr,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
* Enable IO Cstate on a family 12h CPU.
* Implement steps 1 to 3 of BKDG section 2.5.3.2.9 BIOS Requirements for Initialization
*
* @param[in] IoCstateServices Pointer to this CPU's IO Cstate family services.
* @param[in] EntryPoint Timepoint designator.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] StdHeader Config Handle for library, services.
*
* @return AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
F12InitializeIoCstate (
IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 i;
UINT32 MaxEnabledPstate;
UINT32 LocalPciRegister;
UINT64 LocalMsrRegister;
AP_TASK TaskPtr;
PCI_ADDR PciAddress;
if ((EntryPoint & CPU_FEAT_AFTER_PM_INIT) != 0) {
for (i = MSR_PSTATE_7; i > MSR_PSTATE_0; i--) {
LibAmdMsrRead (i, &LocalMsrRegister, StdHeader);
if (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) {
break;
}
}
MaxEnabledPstate = i - MSR_PSTATE_0;
// Initialize MSRC001_0073[CstateAddr] on each core to a region of
// the IO address map with 8 consecutive available addresses.
LocalMsrRegister = 0;
((CSTATE_ADDRESS_MSR *) &LocalMsrRegister)->CstateAddr = PlatformConfig->CStateIoBaseAddress;
ASSERT ((((CSTATE_ADDRESS_MSR *) &LocalMsrRegister)->CstateAddr != 0) &&
(((CSTATE_ADDRESS_MSR *) &LocalMsrRegister)->CstateAddr <= 0xFFF8));
TaskPtr.FuncAddress.PfApTaskI = F12InitializeIoCstateOnCore;
TaskPtr.DataTransfer.DataSizeInDwords = 2;
TaskPtr.DataTransfer.DataPtr = &LocalMsrRegister;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.ExeFlags = WAIT_FOR_CORE;
ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL);
// Program D18F4x1A8[PService] to the index of lowest-performance
// P-state with MSRC001_00[6B:64][PstateEn]==1 on core 0.
PciAddress.AddressValue = CPU_STATE_PM_CTRL0_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
((CPU_STATE_PM_CTRL0_REGISTER *) &LocalPciRegister)->PService = MaxEnabledPstate;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
// Program D18F4x1AC[CstPminEn] to 1.
PciAddress.AddressValue = CPU_STATE_PM_CTRL1_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
((CPU_STATE_PM_CTRL1_REGISTER *) &LocalPciRegister)->CstPminEn = 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
}
return AGESA_SUCCESS;
}
/*---------------------------------------------------------------------------------------*/
/**
* Enable C-State on a family 12h core.
*
* @param[in] CstateBaseMsr MSR value to write to C001_0073 as determined by core 0.
* @param[in] StdHeader Config Handle for library, services.
*
*/
VOID
STATIC
F12InitializeIoCstateOnCore (
IN VOID *CstateBaseMsr,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
// Initialize MSRC001_0073[CstateAddr] on each core
LibAmdMsrWrite (MSR_CSTATE_ADDRESS, (UINT64 *) CstateBaseMsr, StdHeader);
}
/*---------------------------------------------------------------------------------------*/
/**
* Returns the size of CST object
*
* @param[in] IoCstateServices IoCstate services.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data
* @param[in] StdHeader Config Handle for library, services.
*
* @retval CstObjSize Size of CST Object
*
*/
UINT32
STATIC
F12GetAcpiCstObj (
IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
return (CST_HEADER_SIZE + CST_BODY_SIZE);
}
/*---------------------------------------------------------------------------------------*/
/**
* Routine to generate the ACPI C-State objects
*
* @param[in] IoCstateServices IO Cstate services.
* @param[in] LocalApicId Local Apic Id
* @param[in, out] PstateAcpiBufferPtr Pointer to Pstate data buffer.
* @param[in] StdHeader Config Handle for library, services.
*
*/
VOID
STATIC
F12CreateAcpiCstObj (
IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
IN UINT8 LocalApicId,
IN OUT VOID **PstateAcpiBufferPtr,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 MsrData;
CST_HEADER_STRUCT *CstHeaderPtr;
CST_BODY_STRUCT *CstBodyPtr;
// Read from MSR C0010073 to obtain CstateAddr
LibAmdMsrRead (MSR_CSTATE_ADDRESS, &MsrData, StdHeader);
ASSERT ((((CSTATE_ADDRESS_MSR *) &MsrData)->CstateAddr != 0) &&
(((CSTATE_ADDRESS_MSR *) &MsrData)->CstateAddr <= 0xFFF8));
// Typecast the pointer
CstHeaderPtr = (CST_HEADER_STRUCT *) *PstateAcpiBufferPtr;
// Set CST Header
CstHeaderPtr->NameOpcode = NAME_OPCODE;
CstHeaderPtr->CstName_a__ = CST_NAME__;
CstHeaderPtr->CstName_a_C = CST_NAME_C;
CstHeaderPtr->CstName_a_S = CST_NAME_S;
CstHeaderPtr->CstName_a_T = CST_NAME_T;
// Typecast the pointer
CstHeaderPtr++;
CstBodyPtr = (CST_BODY_STRUCT *) CstHeaderPtr;
// Set CST Body
CstBodyPtr->PkgOpcode = PACKAGE_OPCODE;
CstBodyPtr->PkgLength = CST_LENGTH;
CstBodyPtr->PkgElements = CST_NUM_OF_ELEMENTS;
CstBodyPtr->BytePrefix = BYTE_PREFIX_OPCODE;
CstBodyPtr->Count = CST_COUNT;
CstBodyPtr->PkgOpcode2 = PACKAGE_OPCODE;
CstBodyPtr->PkgLength2 = CST_PKG_LENGTH;
CstBodyPtr->PkgElements2 = CST_PKG_ELEMENTS;
CstBodyPtr->BufferOpcode = BUFFER_OPCODE;
CstBodyPtr->BufferLength = CST_SUBPKG_LENGTH;
CstBodyPtr->BufferElements = CST_SUBPKG_ELEMENTS;
CstBodyPtr->BufferOpcode2 = BUFFER_OPCODE;
CstBodyPtr->GdrOpcode = GENERIC_REG_DESCRIPTION;
CstBodyPtr->GdrLength = CST_GDR_LENGTH;
CstBodyPtr->AddrSpaceId = GDR_ASI_SYSTEM_IO;
CstBodyPtr->RegBitWidth = 0x08;
CstBodyPtr->RegBitOffset = 0x00;
CstBodyPtr->AddressSize = GDR_ASZ_BYTE_ACCESS;
CstBodyPtr->RegisterAddr = ((CSTATE_ADDRESS_MSR *) &MsrData)->CstateAddr + 1;
CstBodyPtr->EndTag = 0x0079;
CstBodyPtr->BytePrefix2 = BYTE_PREFIX_OPCODE;
CstBodyPtr->Type = CST_C2_TYPE;
CstBodyPtr->WordPrefix = WORD_PREFIX_OPCODE;
CstBodyPtr->Latency = 0x64;
CstBodyPtr->DWordPrefix = DWORD_PREFIX_OPCODE;
CstBodyPtr->Power = 0;
CstBodyPtr++;
//Update the pointer
*PstateAcpiBufferPtr = CstBodyPtr;
}
CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F12IoCstateSupport =
{
0,
(PF_IO_CSTATE_IS_SUPPORTED) CommonReturnTrue,
F12InitializeIoCstate,
F12GetAcpiCstObj,
F12CreateAcpiCstObj,
(PF_IO_CSTATE_IS_CSD_GENERATED) CommonReturnFalse
};

195
src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12MicrocodePatch03000002.c
View File

@ -1,195 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_12 Microcode patch.
*
* Fam12 Microcode Patch rev 03000002 for 1200 or equivalent.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/FAMILY/0x12
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "cpuEarlyInit.h"
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
// Patch code 03000002 for 1200 and equivalent
CONST MICROCODE_PATCHES ROMDATA CpuF12MicrocodePatch03000002 =
{{
0x10, 0x20, 0x24, 0x03, 0x02, 0x00, 0x00, 0x03,
0x03, 0x80, 0x20, 0x00, 0x49, 0xb8, 0x03, 0x43,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x12, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa,
0x6d, 0x10, 0xd8, 0x0b, 0x51, 0x0a, 0x38, 0x29,
0xff, 0xff, 0x72, 0x0a, 0xfc, 0x03, 0xa7, 0x7c,
0xff, 0xff, 0xb8, 0x1c, 0xff, 0xff, 0x59, 0x6b,
0xff, 0xff, 0xf9, 0xa9, 0xff, 0xff, 0xc8, 0x1a,
0x6f, 0x58, 0x39, 0x00, 0x81, 0x3f, 0xa0, 0xd7,
0xfc, 0xff, 0xff, 0x03, 0x0f, 0xef, 0x58, 0xc8,
0xf0, 0xfe, 0xff, 0x4f, 0x3a, 0xfc, 0x31, 0xe8,
0xc0, 0x87, 0x93, 0x01, 0x80, 0xff, 0xc0, 0x3f,
0xbf, 0xe1, 0x1f, 0xc0, 0x00, 0xfe, 0x03, 0xff,
0xff, 0x86, 0x7f, 0x00, 0x03, 0xf8, 0x0f, 0xfc,
0xfc, 0x1b, 0xfe, 0x01, 0x00, 0xe0, 0xff, 0xf7,
0xbf, 0x4b, 0xff, 0xff, 0xf0, 0xf3, 0xf0, 0x0f,
0x38, 0x00, 0x4f, 0xdb, 0xa0, 0xd7, 0x81, 0x3f,
0xeb, 0x01, 0xfc, 0x77, 0x5a, 0x3e, 0x0f, 0xfd,
0x69, 0x00, 0x70, 0x41, 0xfd, 0xdf, 0x03, 0xdc,
0x07, 0xf8, 0x79, 0xf8, 0xfa, 0x7f, 0x14, 0xd6,
0x1f, 0xe0, 0xe7, 0xe1, 0xeb, 0xff, 0x4f, 0x56,
0x7f, 0x80, 0x9f, 0x87, 0xff, 0x3d, 0x00, 0xe8,
0x20, 0xf0, 0x6f, 0x82, 0xfc, 0x03, 0xfc, 0x1c,
0xf9, 0xff, 0xbf, 0xc9, 0xf0, 0xcf, 0x74, 0x7d,
0xff, 0x3f, 0xff, 0x25, 0xc3, 0xbf, 0xd2, 0xfd,
0xac, 0x56, 0x19, 0x00, 0xf8, 0x0f, 0xfc, 0x03,
0x1b, 0xfe, 0x01, 0xfc, 0xe0, 0x3f, 0xf0, 0x0f,
0x6f, 0xf8, 0x07, 0xf0, 0x80, 0xff, 0xc0, 0x3f,
0xbf, 0xe1, 0x1f, 0xc0, 0x00, 0xfe, 0x7f, 0x0f,
0x00, 0x18, 0x60, 0xe5, 0x3e, 0x07, 0xfd, 0x00,
0xff, 0xf2, 0xfd, 0xff, 0xfc, 0x3c, 0xfc, 0x03,
0x0e, 0xc0, 0x81, 0x57, 0xe0, 0x73, 0xd0, 0x0f,
0x06, 0x00, 0xb2, 0x5d, 0xff, 0x00, 0xfe, 0x03,
0x00, 0xff, 0x86, 0x7f, 0xfc, 0x03, 0xf8, 0x0f,
0x01, 0xfc, 0x1b, 0xfe, 0xf0, 0x0f, 0xe0, 0x3f,
0x07, 0xf0, 0x6f, 0xf8, 0xdf, 0x03, 0x80, 0xff,
0x81, 0x7f, 0x00, 0xff, 0x3f, 0x80, 0x7f, 0xc3,
0x07, 0xfe, 0x01, 0xfc, 0xff, 0x00, 0xfe, 0x0d,
0x1f, 0xf8, 0x07, 0xf0, 0xfc, 0x03, 0xf8, 0x37,
0xff, 0xef, 0x01, 0xc0, 0xff, 0xc0, 0x3f, 0x80,
0xe1, 0x1f, 0xc0, 0xbf, 0xfe, 0x03, 0xff, 0x00,
0x86, 0x7f, 0x00, 0xff, 0xf8, 0x0f, 0xfc, 0x03,
0x1b, 0xfe, 0x01, 0xfc, 0xe0, 0xff, 0xf7, 0x00,
0xc0, 0x7f, 0xe0, 0x1f, 0xdf, 0xf0, 0x0f, 0xe0,
0x00, 0xff, 0x81, 0x7f, 0x7f, 0xc3, 0x3f, 0x80,
0x01, 0xfc, 0x07, 0xfe, 0xfe, 0x0d, 0xff, 0x00,
0x00, 0xf0, 0xff, 0x7b, 0x0f, 0xe0, 0x3f, 0xf0,
0xf0, 0x6f, 0xf8, 0x07, 0x3f, 0x80, 0xff, 0xc0,
0xc0, 0xbf, 0xe1, 0x1f, 0xff, 0x00, 0xfe, 0x03,
0x00, 0xff, 0x86, 0x7f, 0x3d, 0x00, 0xf8, 0xff,
0xf8, 0x07, 0xf0, 0x1f, 0x03, 0xf8, 0x37, 0xfc,
0xe0, 0x1f, 0xc0, 0x7f, 0x0f, 0xe0, 0xdf, 0xf0,
0x81, 0x7f, 0x00, 0xff, 0x3f, 0x80, 0x7f, 0xc3,
0xff, 0x1e, 0x00, 0xfc, 0x0f, 0xfc, 0x03, 0xf8,
0xfe, 0x01, 0xfc, 0x1b, 0x3f, 0xf0, 0x0f, 0xe0,
0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xc0, 0x3f, 0x80,
0xe1, 0x1f, 0xc0, 0xbf, 0xfe, 0x7f, 0x0f, 0x00,
0xfc, 0x07, 0xfe, 0x01, 0x0d, 0xff, 0x00, 0xfe,
0xf0, 0x1f, 0xf8, 0x07, 0x37, 0xfc, 0x03, 0xf8,
0xc0, 0x7f, 0xe0, 0x1f, 0xdf, 0xf0, 0x0f, 0xe0,
0x00, 0xff, 0xbf, 0x07, 0x00, 0xfe, 0x03, 0xff,
0xff, 0x86, 0x7f, 0x00, 0x03, 0xf8, 0x0f, 0xfc,
0xfc, 0x1b, 0xfe, 0x01, 0x0f, 0xe0, 0x3f, 0xf0,
0xf0, 0x6f, 0xf8, 0x07, 0x03, 0x80, 0xff, 0xdf,
0x7f, 0x00, 0xff, 0x81, 0x80, 0x7f, 0xc3, 0x3f,
0xfe, 0x01, 0xfc, 0x07, 0x00, 0xfe, 0x0d, 0xff,
0xf8, 0x07, 0xf0, 0x1f, 0x03, 0xf8, 0x37, 0xfc,
0xef, 0x01, 0xc0, 0xff, 0xff, 0x7f, 0x16, 0xff,
0x9f, 0x6b, 0xf1, 0xe0, 0xff, 0xff, 0x5b, 0x98,
0x7f, 0x80, 0xb3, 0x86, 0xdf, 0xfe, 0x63, 0xf9,
0xfe, 0xb1, 0x16, 0x0f, 0x98, 0xd6, 0x00, 0x80,
0x01, 0x56, 0x0e, 0x80, 0xd0, 0x0f, 0xe0, 0x73,
0xdf, 0xff, 0xff, 0x2c, 0xc3, 0x3f, 0xc0, 0xcf,
0x1c, 0x60, 0xe5, 0x00, 0x07, 0xfd, 0x00, 0x3e,
0xc0, 0x3d, 0x6b, 0x00, 0xe0, 0x3f, 0xf0, 0x0f,
0x6f, 0xf8, 0x07, 0xf0, 0x80, 0xff, 0xc0, 0x3f,
0xbf, 0xe1, 0x1f, 0xc0, 0x00, 0xfe, 0x03, 0xff,
0xff, 0x86, 0x7f, 0x00, 0x00, 0xf8, 0xff, 0x3d,
0x07, 0xf0, 0x1f, 0xf8, 0xf8, 0x37, 0xfc, 0x03,
0x1f, 0xc0, 0x7f, 0xe0, 0xe0, 0xdf, 0xf0, 0x0f,
0x7f, 0x00, 0xff, 0x81, 0x80, 0x7f, 0xc3, 0x3f,
0x1e, 0x00, 0xfc, 0xff, 0xfc, 0x03, 0xf8, 0x0f,
0x01, 0xfc, 0x1b, 0xfe, 0xf0, 0x0f, 0xe0, 0x3f,
0x07, 0xf0, 0x6f, 0xf8, 0xc0, 0x3f, 0x80, 0xff,
0x1f, 0xc0, 0xbf, 0xe1, 0x7f, 0x0f, 0x00, 0xfe,
0x07, 0xfe, 0x01, 0xfc, 0xff, 0x00, 0xfe, 0x0d,
0x1f, 0xf8, 0x07, 0xf0, 0xfc, 0x03, 0xf8, 0x37,
0x7f, 0xe0, 0x1f, 0xc0, 0xf0, 0x0f, 0xe0, 0xdf,
0xff, 0xbf, 0x07, 0x00, 0xfe, 0x03, 0xff, 0x00,
0x86, 0x7f, 0x00, 0xff, 0xf8, 0x0f, 0xfc, 0x03,
0x1b, 0xfe, 0x01, 0xfc, 0xe0, 0x3f, 0xf0, 0x0f,
0x6f, 0xf8, 0x07, 0xf0, 0x80, 0xff, 0xdf, 0x03,
0x00, 0xff, 0x81, 0x7f, 0x7f, 0xc3, 0x3f, 0x80,
0x01, 0xfc, 0x07, 0xfe, 0xfe, 0x0d, 0xff, 0x00,
0x07, 0xf0, 0x1f, 0xf8, 0xf8, 0x37, 0xfc, 0x03,
0x01, 0xc0, 0xff, 0xef, 0x3f, 0x80, 0xff, 0xc0,
0xc0, 0xbf, 0xe1, 0x1f, 0xff, 0x00, 0xfe, 0x03,
0x00, 0xff, 0x86, 0x7f, 0xfc, 0x03, 0xf8, 0x0f,
0x01, 0xfc, 0x1b, 0xfe, 0xf7, 0x00, 0xe0, 0xff,
0xe0, 0x1f, 0xc0, 0x7f, 0x0f, 0xe0, 0xdf, 0xf0,
0x81, 0x7f, 0x00, 0xff, 0x3f, 0x80, 0x7f, 0xc3,
0x07, 0xfe, 0x01, 0xfc, 0xff, 0x00, 0xfe, 0x0d,
0xff, 0x7b, 0x00, 0xf0, 0x3f, 0xf0, 0x0f, 0xe0,
0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xc0, 0x3f, 0x80,
0xe1, 0x1f, 0xc0, 0xbf, 0xfe, 0x03, 0xff, 0x00,
0x86, 0x7f, 0x00, 0xff, 0xf8, 0xff, 0x3d, 0x00,
0xf0, 0x1f, 0xf8, 0x07, 0x37, 0xfc, 0x03, 0xf8,
0xc0, 0x7f, 0xe0, 0x1f, 0xdf, 0xf0, 0x0f, 0xe0,
0x00, 0xff, 0x81, 0x7f, 0x7f, 0xc3, 0x3f, 0x80,
0x00, 0xfc, 0xff, 0x1e, 0x03, 0xf8, 0x0f, 0xfc,
0xfc, 0x1b, 0xfe, 0x01, 0x0f, 0xe0, 0x3f, 0xf0,
0xf0, 0x6f, 0xf8, 0x07, 0x3f, 0x80, 0xff, 0xc0,
0xc0, 0xbf, 0xe1, 0x1f, 0x0f, 0x00, 0xfe, 0x7f,
0xfe, 0x01, 0xfc, 0x07, 0x00, 0xfe, 0x0d, 0xff,
0xf8, 0x07, 0xf0, 0x1f, 0x03, 0xf8, 0x37, 0xfc,
0xe0, 0x1f, 0xc0, 0x7f, 0x0f, 0xe0, 0xdf, 0xf0,
0xbf, 0x07, 0x00, 0xff, 0x03, 0xff, 0x00, 0xfe,
0x7f, 0x00, 0xff, 0x86, 0x0f, 0xfc, 0x03, 0xf8,
0xfe, 0x01, 0xfc, 0x1b, 0x3f, 0xf0, 0x0f, 0xe0,
0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xdf, 0x03, 0x80
}};
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/

195
src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12MicrocodePatch0300000e.c
View File

@ -1,195 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_12 Microcode patch.
*
* Fam12 Microcode Patch rev 0300000E for 3001 or equivalent.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/FAMILY/0x12
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "cpuEarlyInit.h"
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
// Patch code 0300000E for 3001 and equivalent
CONST MICROCODE_PATCHES ROMDATA CpuF12MicrocodePatch0300000e =
{{
0x10, 0x20, 0x04, 0x10, 0x0e, 0x00, 0x00, 0x03,
0x03, 0x80, 0x20, 0x00, 0xbc, 0x7c, 0x68, 0xfe,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x01, 0x30, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa,
0x96, 0x0c, 0xc1, 0x47, 0xbd, 0x02, 0x2a, 0x19,
0xff, 0xff, 0xcd, 0x73, 0xff, 0xff, 0x17, 0xa0,
0xff, 0xff, 0xb9, 0x5e, 0xff, 0xff, 0x81, 0x4a,
0xff, 0xff, 0xd0, 0x2a, 0xff, 0xff, 0xfd, 0xa8,
0xef, 0x98, 0x38, 0x00, 0x03, 0x3e, 0x80, 0xa1,
0xfc, 0x57, 0xfe, 0x39, 0x0f, 0xfb, 0x1c, 0x2e,
0xf0, 0xbf, 0xf9, 0xa7, 0x3c, 0xec, 0x73, 0xb8,
0x40, 0x83, 0xab, 0x01, 0x87, 0xff, 0xca, 0xbf,
0xe5, 0x61, 0xdf, 0xc3, 0x16, 0xfe, 0x37, 0xff,
0x97, 0x87, 0x7d, 0x0b, 0x5b, 0xf8, 0xcf, 0xfc,
0x5c, 0x1e, 0xf6, 0x2d, 0x00, 0xe0, 0xff, 0xf7,
0x3f, 0xc0, 0x81, 0xff, 0x45, 0xff, 0xf0, 0x2d,
0xff, 0x28, 0xbb, 0xfc, 0x54, 0x95, 0xc3, 0x2f,
0xff, 0x03, 0xfc, 0xfd, 0x58, 0xf6, 0x0f, 0xdf,
0x6a, 0x00, 0xb0, 0xe0, 0xc1, 0x9f, 0x00, 0x3c,
0x65, 0xa0, 0x75, 0xf8, 0xff, 0x7f, 0x80, 0x7f,
0xdb, 0xcb, 0xfe, 0xe1, 0x23, 0xfc, 0x09, 0x62,
0x5f, 0x06, 0x5a, 0x87, 0xbb, 0x35, 0x00, 0x50,
0x1f, 0xf8, 0x07, 0xf0, 0xfc, 0x03, 0xf8, 0x37,
0x7f, 0xe0, 0x1f, 0xc0, 0xf0, 0x0f, 0xe0, 0xdf,
0xff, 0x81, 0x7f, 0x00, 0xc3, 0x3f, 0x80, 0x7f,
0xfc, 0xff, 0x1e, 0x00, 0xf8, 0x0f, 0xfc, 0x03,
0x1b, 0xfe, 0x01, 0xfc, 0xe0, 0x3f, 0xf0, 0x0f,
0x6f, 0xf8, 0x07, 0xf0, 0x80, 0xff, 0xc0, 0x3f,
0xbf, 0xe1, 0x1f, 0xc0, 0x00, 0xfe, 0x7f, 0x0f,
0x01, 0xfc, 0x07, 0xfe, 0xfe, 0x0d, 0xff, 0x00,
0x07, 0xf0, 0x1f, 0xf8, 0xf8, 0x37, 0xfc, 0x03,
0x1f, 0xc0, 0x7f, 0xe0, 0xe0, 0xdf, 0xf0, 0x0f,
0x07, 0x00, 0xff, 0xbf, 0xff, 0x00, 0xfe, 0x03,
0x00, 0xff, 0x86, 0x7f, 0xfc, 0x03, 0xf8, 0x0f,
0x01, 0xfc, 0x1b, 0xfe, 0xf0, 0x0f, 0xe0, 0x3f,
0x07, 0xf0, 0x6f, 0xf8, 0xdf, 0x03, 0x80, 0xff,
0x81, 0x7f, 0x00, 0xff, 0x3f, 0x80, 0x7f, 0xc3,
0x07, 0xfe, 0x01, 0xfc, 0xff, 0x00, 0xfe, 0x0d,
0x1f, 0xf8, 0x07, 0xf0, 0xfc, 0x03, 0xf8, 0x37,
0xff, 0xef, 0x01, 0xc0, 0xff, 0xc0, 0x3f, 0x80,
0xe1, 0x1f, 0xc0, 0xbf, 0xfe, 0x03, 0xff, 0x00,
0x86, 0x7f, 0x00, 0xff, 0xf8, 0x0f, 0xfc, 0x03,
0x1b, 0xfe, 0x01, 0xfc, 0xe0, 0xff, 0xf7, 0x00,
0xc0, 0x7f, 0xe0, 0x1f, 0xdf, 0xf0, 0x0f, 0xe0,
0x00, 0xff, 0x81, 0x7f, 0x7f, 0xc3, 0x3f, 0x80,
0x01, 0xfc, 0x07, 0xfe, 0xfe, 0x0d, 0xff, 0x00,
0x00, 0xf0, 0xff, 0x7b, 0x0f, 0xe0, 0x3f, 0xf0,
0xf0, 0x6f, 0xf8, 0x07, 0x3f, 0x80, 0xff, 0xc0,
0xc0, 0xbf, 0xe1, 0x1f, 0xff, 0x00, 0xfe, 0x03,
0x00, 0xff, 0x86, 0x7f, 0x3d, 0x00, 0xf8, 0xff,
0xf8, 0x07, 0xf0, 0x1f, 0x03, 0xf8, 0x37, 0xfc,
0xe0, 0x1f, 0xc0, 0x7f, 0x0f, 0xe0, 0xdf, 0xf0,
0x81, 0x7f, 0x00, 0xff, 0x3f, 0x80, 0x7f, 0xc3,
0xff, 0x1e, 0x00, 0xfc, 0x0f, 0xfc, 0x03, 0xf8,
0xfe, 0x01, 0xfc, 0x1b, 0x3f, 0xf0, 0x0f, 0xe0,
0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xc0, 0x3f, 0x80,
0xe1, 0x1f, 0xc0, 0xbf, 0xfe, 0x7f, 0x0f, 0x00,
0xfc, 0x07, 0xfe, 0x01, 0x0d, 0xff, 0x00, 0xfe,
0xf0, 0x1f, 0xf8, 0x07, 0x37, 0xfc, 0x03, 0xf8,
0xc0, 0x7f, 0xe0, 0x1f, 0xdf, 0xf0, 0x0f, 0xe0,
0x00, 0xff, 0xbf, 0x07, 0x00, 0xfe, 0x03, 0xff,
0xff, 0x86, 0x7f, 0x00, 0x03, 0xf8, 0x0f, 0xfc,
0xfc, 0x1b, 0xfe, 0x01, 0x0f, 0xe0, 0x3f, 0xf0,
0xf0, 0x6f, 0xf8, 0x07, 0x03, 0x80, 0xff, 0xdf,
0x7f, 0x00, 0xff, 0x81, 0x80, 0x7f, 0xc3, 0x3f,
0xfe, 0x01, 0xfc, 0x07, 0x00, 0xfe, 0x0d, 0xff,
0xf8, 0x07, 0xf0, 0x1f, 0x03, 0xf8, 0x37, 0xfc,
0xaf, 0x01, 0xc0, 0x3f, 0xc0, 0x3f, 0x80, 0xff,
0x1f, 0xc0, 0xbf, 0xe1, 0x03, 0xff, 0x00, 0xfe,
0x7f, 0x00, 0xff, 0x86, 0x0f, 0xfc, 0x03, 0xf8,
0xfe, 0x01, 0xfc, 0x1b, 0x9f, 0xd7, 0x00, 0xc0,
0x42, 0x80, 0x3f, 0x41, 0xf0, 0xcb, 0x40, 0xeb,
0xff, 0x9d, 0x7f, 0x3f, 0xc3, 0xbe, 0x87, 0xdd,
0xfc, 0x67, 0xfe, 0xf9, 0x0f, 0xfb, 0x16, 0x76,
0xf0, 0xff, 0x77, 0x00, 0xe0, 0x3f, 0xf0, 0x0f,
0x6f, 0xf8, 0x07, 0xf0, 0x80, 0xff, 0xc0, 0x3f,
0xbf, 0xe1, 0x1f, 0xc0, 0x00, 0xfe, 0x17, 0xdf,
0xb6, 0x83, 0x7f, 0x2f, 0x00, 0xf8, 0xff, 0x3d,
0x0f, 0xf0, 0xfd, 0xff, 0xd9, 0x3f, 0x7c, 0x7b,
0x3f, 0xc1, 0xff, 0xff, 0x40, 0xeb, 0xf0, 0xcb,
0x7f, 0x00, 0xff, 0x81, 0x80, 0x7f, 0xc3, 0x3f,
0x1e, 0x00, 0xfc, 0xff, 0xff, 0x07, 0x80, 0xf0,
0xa5, 0xe8, 0x1f, 0xbe, 0xff, 0xdf, 0xc5, 0xff,
0x05, 0xb8, 0x72, 0xf8, 0x6e, 0x1c, 0xc0, 0xb0,
0x1f, 0xc0, 0xe7, 0xa1, 0xbe, 0x0c, 0x00, 0xca,
0x07, 0xfe, 0x01, 0xfc, 0xff, 0x00, 0xfe, 0x0d,
0x1f, 0xf8, 0x07, 0xf0, 0xfc, 0x03, 0xf8, 0x37,
0x7f, 0xe0, 0x1f, 0xc0, 0xf0, 0x0f, 0xe0, 0xdf,
0xff, 0xbf, 0x07, 0x00, 0xfe, 0x03, 0xff, 0x00,
0x86, 0x7f, 0x00, 0xff, 0xf8, 0x0f, 0xfc, 0x03,
0x1b, 0xfe, 0x01, 0xfc, 0xe0, 0x3f, 0xf0, 0x0f,
0x6f, 0xf8, 0x07, 0xf0, 0x80, 0xff, 0xdf, 0x03,
0x00, 0xff, 0x81, 0x7f, 0x7f, 0xc3, 0x3f, 0x80,
0x01, 0xfc, 0x07, 0xfe, 0xfe, 0x0d, 0xff, 0x00,
0x07, 0xf0, 0x1f, 0xf8, 0xf8, 0x37, 0xfc, 0x03,
0x01, 0xc0, 0xff, 0xef, 0x3f, 0x80, 0xff, 0xc0,
0xc0, 0xbf, 0xe1, 0x1f, 0xff, 0x00, 0xfe, 0x03,
0x00, 0xff, 0x86, 0x7f, 0xfc, 0x03, 0xf8, 0x0f,
0x01, 0xfc, 0x1b, 0xfe, 0xf7, 0x00, 0xe0, 0xff,
0xe0, 0x1f, 0xc0, 0x7f, 0x0f, 0xe0, 0xdf, 0xf0,
0x81, 0x7f, 0x00, 0xff, 0x3f, 0x80, 0x7f, 0xc3,
0x07, 0xfe, 0x01, 0xfc, 0xff, 0x00, 0xfe, 0x0d,
0xff, 0x7b, 0x00, 0xf0, 0x3f, 0xf0, 0x0f, 0xe0,
0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xc0, 0x3f, 0x80,
0xe1, 0x1f, 0xc0, 0xbf, 0xfe, 0x03, 0xff, 0x00,
0x86, 0x7f, 0x00, 0xff, 0xf8, 0xff, 0x3d, 0x00,
0xf0, 0x1f, 0xf8, 0x07, 0x37, 0xfc, 0x03, 0xf8,
0xc0, 0x7f, 0xe0, 0x1f, 0xdf, 0xf0, 0x0f, 0xe0,
0x00, 0xff, 0x81, 0x7f, 0x7f, 0xc3, 0x3f, 0x80,
0x00, 0xfc, 0xff, 0x1e, 0x03, 0xf8, 0x0f, 0xfc,
0xfc, 0x1b, 0xfe, 0x01, 0x0f, 0xe0, 0x3f, 0xf0,
0xf0, 0x6f, 0xf8, 0x07, 0x3f, 0x80, 0xff, 0xc0,
0xc0, 0xbf, 0xe1, 0x1f, 0x0f, 0x00, 0xfe, 0x7f,
0xfe, 0x01, 0xfc, 0x07, 0x00, 0xfe, 0x0d, 0xff,
0xf8, 0x07, 0xf0, 0x1f, 0x03, 0xf8, 0x37, 0xfc,
0xe0, 0x1f, 0xc0, 0x7f, 0x0f, 0xe0, 0xdf, 0xf0,
0xbf, 0x07, 0x00, 0xff, 0x03, 0xff, 0x00, 0xfe,
0x7f, 0x00, 0xff, 0x86, 0x0f, 0xfc, 0x03, 0xf8,
0xfe, 0x01, 0xfc, 0x1b, 0x3f, 0xf0, 0x0f, 0xe0,
0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xdf, 0x03, 0x80
}};
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/

195
src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12MicrocodePatch03000027.c
View File

@ -1,195 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_12 Microcode patch.
*
* Fam12 Microcode Patch rev 03000027 for 3010 or equivalent.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/FAMILY/0x12
* @e \$Revision: 58717 $ @e \$Date: 2011-09-13 23:20:11 +0800 (Tue, 13 Sep 2011) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "cpuEarlyInit.h"
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
// Patch code 03000027 for 3010 and equivalent
CONST MICROCODE_PATCHES ROMDATA CpuF12MicrocodePatch03000027 =
{{
0x11, 0x20, 0x09, 0x13, 0x27, 0x00, 0x00, 0x03,
0x03, 0x80, 0x20, 0x00, 0x40, 0x00, 0x4f, 0x10,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x10, 0x30, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa,
0xbd, 0x02, 0x19, 0xe3, 0x99, 0x0c, 0x06, 0x98,
0x8a, 0x0f, 0x7b, 0x68, 0xc6, 0x11, 0x45, 0xd0,
0x8c, 0x0e, 0x45, 0x3c, 0xff, 0xff, 0x29, 0xee,
0xff, 0xff, 0x66, 0xdd, 0xff, 0xff, 0x53, 0x89,
0x04, 0xfe, 0xff, 0x00, 0xc3, 0xb7, 0x14, 0xfd,
0xec, 0xf2, 0xff, 0xa3, 0x0e, 0xbf, 0x50, 0x55,
0xf0, 0xf7, 0xff, 0x0f, 0x3f, 0x7c, 0x63, 0xd9,
0x80, 0x83, 0xab, 0x01, 0x02, 0x87, 0x04, 0x7f,
0xd6, 0xe1, 0x97, 0x81, 0x01, 0xfe, 0xfd, 0xff,
0xfb, 0x87, 0x6f, 0x2f, 0x27, 0x78, 0x8d, 0xf0,
0x68, 0x1d, 0x7e, 0x19, 0x00, 0x40, 0xed, 0xd6,
0x0e, 0xc0, 0x3b, 0x26, 0x60, 0xe8, 0x80, 0x0f,
0x7f, 0x0e, 0xff, 0x95, 0x87, 0xcb, 0xc3, 0x3e,
0xfe, 0x29, 0xfc, 0x6f, 0x1c, 0x2e, 0x0f, 0xfb,
0x6a, 0x00, 0xc0, 0xe0, 0xf2, 0xef, 0xe1, 0xbf,
0xf7, 0x70, 0x79, 0xd8, 0xcd, 0xbf, 0x85, 0xff,
0xdf, 0xc2, 0xe5, 0x61, 0x33, 0xff, 0x16, 0xfe,
0x7d, 0x0b, 0x97, 0x87, 0xff, 0x3d, 0x00, 0xf8,
0xb4, 0x8d, 0x03, 0xf0, 0xf8, 0x03, 0x02, 0x1c,
0xfa, 0xb4, 0x0e, 0xc0, 0xe0, 0xaf, 0x0d, 0xf0,
0xff, 0x81, 0x7f, 0x00, 0xc3, 0x3f, 0x80, 0x7f,
0x28, 0xb8, 0x1a, 0x00, 0xa0, 0xcf, 0xca, 0x01,
0x0e, 0xfc, 0x01, 0xbd, 0xe0, 0x3f, 0xf0, 0x0f,
0x6f, 0xf8, 0x07, 0xf0, 0x80, 0xff, 0xc0, 0x3f,
0xbf, 0xe1, 0x1f, 0xc0, 0x00, 0xfe, 0x7f, 0x07,
0xb7, 0x3c, 0xf8, 0xff, 0x3f, 0x0f, 0xff, 0x00,
0x0f, 0x90, 0xfa, 0xff, 0xd1, 0x3f, 0x1c, 0x73,
0x3f, 0xcb, 0xea, 0xff, 0x55, 0xff, 0xf0, 0xcf,
0x06, 0x00, 0x36, 0xae, 0xfc, 0x09, 0xae, 0x23,
0x06, 0x59, 0x87, 0x3f, 0xff, 0x07, 0x38, 0xfd,
0xb9, 0xe8, 0x1f, 0x8e, 0xf0, 0x0f, 0xe0, 0x3f,
0x07, 0xf0, 0x6f, 0xf8, 0x57, 0x03, 0x80, 0x1a,
0x02, 0xff, 0x29, 0x03, 0x3f, 0xc0, 0xcf, 0xc3,
0xff, 0xff, 0xa7, 0x9c, 0xff, 0x52, 0xd7, 0x07,
0xff, 0xdf, 0x97, 0xfa, 0xf8, 0x7b, 0x7b, 0x1d,
0x84, 0xab, 0x01, 0x40, 0x05, 0x6e, 0x1c, 0x80,
0xc1, 0x1f, 0x10, 0xe0, 0xfe, 0x03, 0xff, 0x4a,
0x87, 0x7f, 0x80, 0xcf, 0x09, 0xff, 0xff, 0x6f,
0x1a, 0xfe, 0x01, 0xce, 0xe0, 0xff, 0xf7, 0x00,
0xc0, 0x7f, 0xe0, 0x1f, 0xdf, 0xf0, 0x0f, 0xe0,
0x00, 0xff, 0x81, 0x7f, 0x7f, 0xc3, 0x3f, 0x80,
0x01, 0xfc, 0x07, 0xfe, 0xfe, 0x0d, 0xff, 0x00,
0x00, 0xf0, 0xff, 0x7b, 0x0f, 0xe0, 0x3f, 0xf0,
0xf0, 0x6f, 0xf8, 0x07, 0x3f, 0x80, 0xff, 0xc0,
0xc0, 0xbf, 0xe1, 0x1f, 0xff, 0x00, 0xfe, 0x03,
0x00, 0xff, 0x86, 0x7f, 0x3d, 0x00, 0xf8, 0xff,
0xf8, 0x07, 0xf0, 0x1f, 0x03, 0xf8, 0x37, 0xfc,
0xe0, 0x1f, 0xc0, 0x7f, 0x0f, 0xe0, 0xdf, 0xf0,
0x81, 0x7f, 0x00, 0xff, 0x3f, 0x80, 0x7f, 0xc3,
0xff, 0x1e, 0x00, 0xfc, 0x0f, 0xfc, 0x03, 0xf8,
0xfe, 0x01, 0xfc, 0x1b, 0x3f, 0xf0, 0x0f, 0xe0,
0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xc0, 0x3f, 0x80,
0xe1, 0x1f, 0xc0, 0xbf, 0xfe, 0x7f, 0x0f, 0x00,
0xfe, 0x7f, 0xff, 0xad, 0x0f, 0xff, 0x5a, 0x3f,
0xfa, 0xbf, 0xfc, 0xd7, 0x3c, 0xfc, 0x6b, 0xfd,
0xcb, 0xff, 0xf6, 0x9f, 0xff, 0xf0, 0xcf, 0x75,
0x00, 0xff, 0xbf, 0x07, 0x00, 0xfe, 0xbb, 0xff,
0xfa, 0x87, 0x63, 0x2b, 0x63, 0xfd, 0xff, 0xff,
0x7e, 0x0e, 0xfe, 0x01, 0x7f, 0xe5, 0xdf, 0xff,
0xf8, 0x79, 0xf8, 0x07, 0x03, 0x80, 0xdc, 0x5a,
0xff, 0x04, 0xf5, 0xff, 0x83, 0xad, 0xc3, 0x2f,
0xfe, 0x01, 0xfc, 0x07, 0x00, 0xfe, 0x0d, 0xff,
0xf8, 0x07, 0xf0, 0x1f, 0x03, 0xf8, 0x37, 0xfc,
0xef, 0x01, 0xc0, 0xff, 0xff, 0x7f, 0x80, 0xef,
0xdb, 0xcb, 0xfe, 0xe1, 0xff, 0xff, 0x09, 0xfe,
0x5f, 0x06, 0x5a, 0x87, 0x0f, 0xfc, 0x03, 0xf8,
0xfe, 0x01, 0xfc, 0x1b, 0xff, 0xf7, 0x00, 0xe0,
0x83, 0xff, 0x3f, 0x40, 0xf0, 0x2d, 0x45, 0xff,
0xfe, 0xff, 0xff, 0x2e, 0xc3, 0x2f, 0xc0, 0x95,
0x86, 0x75, 0xe3, 0x00, 0x0f, 0xfd, 0x00, 0x3e,
0x50, 0xf6, 0x65, 0x00, 0x20, 0x21, 0xc0, 0x9f,
0x75, 0xf8, 0x65, 0xa0, 0x9f, 0xff, 0xce, 0xbf,
0xee, 0x61, 0xdf, 0xc3, 0x7c, 0xfe, 0x33, 0xff,
0xbb, 0x87, 0x7d, 0x0b, 0x00, 0xf8, 0xff, 0x3b,
0x07, 0xf0, 0x1f, 0xf8, 0xf8, 0x37, 0xfc, 0x03,
0x1f, 0xc0, 0x7f, 0xe0, 0xe0, 0xdf, 0xf0, 0x0f,
0x6f, 0x00, 0xff, 0x8b, 0x17, 0xdb, 0xc1, 0xbf,
0x1e, 0x00, 0xfc, 0xff, 0xca, 0x01, 0xa0, 0xaf,
0x01, 0xbd, 0x0e, 0xfc, 0xfb, 0x4f, 0xe5, 0x3f,
0xa7, 0xaa, 0x3f, 0xf8, 0xff, 0x7f, 0x00, 0xc0,
0x9b, 0x4a, 0xf1, 0xe0, 0x5c, 0x0d, 0x00, 0x14,
0x57, 0xeb, 0x00, 0xac, 0xfe, 0xda, 0x00, 0x0f,
0xff, 0xff, 0x4f, 0xf0, 0xfc, 0x32, 0xd0, 0x3a,
0x7f, 0xe0, 0x1f, 0xc0, 0xf0, 0x0f, 0xe0, 0xdf,
0xff, 0xbf, 0x03, 0x00, 0xfe, 0xa7, 0xdf, 0x54,
0x87, 0x7f, 0xaa, 0xfe, 0x58, 0xff, 0xff, 0x07,
0x1f, 0xde, 0xa9, 0x90, 0x60, 0x02, 0xc0, 0x9f,
0x75, 0xf8, 0x63, 0xd0, 0x80, 0xff, 0xdf, 0x03,
0x25, 0xff, 0xdf, 0x7f, 0xe2, 0xc3, 0xbf, 0xd2,
0x97, 0xfc, 0xdf, 0xff, 0xfd, 0x0f, 0xff, 0x4a,
0x07, 0xf0, 0xbf, 0xac, 0xf9, 0x3c, 0xf4, 0x5b,
0x01, 0xc0, 0x1c, 0xac, 0x1c, 0x00, 0x7a, 0xac,
0xd0, 0xeb, 0xc0, 0x1f, 0xff, 0x5f, 0xfe, 0xfd,
0xac, 0xc5, 0x83, 0x7f, 0xca, 0x01, 0xa0, 0xf7,
0x01, 0x7c, 0x0e, 0xfa, 0xf7, 0x00, 0xa0, 0xff,
0xf6, 0x5f, 0xcb, 0x7f, 0xaf, 0xf4, 0x7b, 0xf0,
0xdd, 0x7f, 0x00, 0xff, 0xb1, 0x16, 0xfd, 0xc1,
0xff, 0xff, 0x13, 0xfc, 0x7f, 0x0c, 0xb0, 0x0e,
0x5b, 0x65, 0x00, 0x90, 0x3f, 0xf0, 0x6f, 0xe5,
0x38, 0xb6, 0xfa, 0x7c, 0xda, 0x03, 0x7f, 0x82,
0xe1, 0x97, 0xc1, 0xd6, 0xfe, 0x03, 0xff, 0x00,
0x86, 0x7f, 0x00, 0xff, 0xf8, 0xff, 0x3d, 0x00,
0xf2, 0x9f, 0xfd, 0xd7, 0x3c, 0xfc, 0x03, 0xfc,
0xcb, 0xef, 0xff, 0xbf, 0x7f, 0xf0, 0x8f, 0xf5,
0x29, 0xff, 0xd9, 0x7d, 0xd7, 0x83, 0xbf, 0xb7,
0x00, 0xfc, 0xff, 0x1e, 0xfb, 0xfd, 0xcf, 0xfe,
0x7e, 0x0e, 0xfe, 0xfd, 0x0f, 0xe0, 0x7f, 0xfb,
0xa2, 0x3f, 0x38, 0xc6, 0x7f, 0x82, 0x01, 0x00,
0x41, 0xd7, 0xe1, 0x8f, 0x0d, 0x00, 0x72, 0x6b,
0xf8, 0x13, 0x0c, 0x00, 0x0c, 0xb6, 0x0e, 0xbf,
0xfd, 0x07, 0xf0, 0xdf, 0x63, 0xd1, 0x1f, 0x1c,
0x80, 0x3f, 0xc1, 0x00, 0xc7, 0x00, 0xeb, 0xf0,
0xbf, 0x07, 0x00, 0xff, 0x03, 0xff, 0x00, 0xfe,
0x7f, 0x00, 0xff, 0x86, 0x0f, 0xfc, 0x03, 0xf8,
0xfe, 0x01, 0xfc, 0x1b, 0x3f, 0xf0, 0x0f, 0xe0,
0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xdf, 0x03, 0x80
}};
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/

75
src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12PackageType.h
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@ -1,75 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_12 Package Type Definitions
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F12
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _F12_PACKAGE_TYPE_H_
#define _F12_PACKAGE_TYPE_H_
/*---------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*---------------------------------------------------------------------------------------
*/
// Below equates are defined to cooperate with LibAmdGetPackageType.
#define PACKAGE_TYPE_FP1 (1 << 0)
#define PACKAGE_TYPE_FS1 (1 << 1)
#define PACKAGE_TYPE_FM1 (1 << 2)
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*---------------------------------------------------------------------------------------
*/
#endif // _F12_PACKAGE_TYPE_H_

113
src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/LN/F12LnEquivalenceTable.c
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@ -1,113 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_12 Llano Equivalence Table related data
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x12
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuFamilyTranslation.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_CPU_FAMILY_0X12_LN_F12LNEQUIVALENCETABLE_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
GetF12LnMicrocodeEquivalenceTable (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **LnEquivalenceTablePtr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
STATIC CONST UINT16 ROMDATA CpuF12LnMicrocodeEquivalenceTable[] =
{
0x3010, 0x3010,
0x3001, 0x3001,
0x3000, 0x1200
};
/*---------------------------------------------------------------------------------------*/
/**
* Returns the appropriate microcode patch equivalent ID table.
*
* @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[out] LnEquivalenceTablePtr Points to the first entry in the table.
* @param[out] NumberOfElements Number of valid entries in the table.
* @param[in] StdHeader Header for library and services.
*
*/
VOID
GetF12LnMicrocodeEquivalenceTable (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **LnEquivalenceTablePtr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
*NumberOfElements = ((sizeof (CpuF12LnMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
*LnEquivalenceTablePtr = CpuF12LnMicrocodeEquivalenceTable;
}

110
src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/LN/F12LnLogicalIdTables.c
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@ -1,110 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_12 Llano Logical ID Table
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/FAMILY/0x12
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_CPU_FAMILY_0X12_LN_F12LNLOGICALIDTABLES_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
GetF12LnLogicalIdAndRev (
OUT CONST CPU_LOGICAL_ID_XLAT **LnIdPtr,
OUT UINT8 *NumberOfElements,
OUT UINT64 *LogicalFamily,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
STATIC CONST CPU_LOGICAL_ID_XLAT ROMDATA CpuF12LnLogicalIdAndRevArray[] =
{
{
0x3010,
AMD_F12_LN_B0
},
{
0x3000,
AMD_F12_LN_A0
},
{
0x3001,
AMD_F12_LN_A1
}
};
VOID
GetF12LnLogicalIdAndRev (
OUT CONST CPU_LOGICAL_ID_XLAT **LnIdPtr,
OUT UINT8 *NumberOfElements,
OUT UINT64 *LogicalFamily,
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
*NumberOfElements = (sizeof (CpuF12LnLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT));
*LnIdPtr = CpuF12LnLogicalIdAndRevArray;
*LogicalFamily = AMD_FAMILY_12_LN;
}

111
src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/LN/F12LnMicrocodePatchTables.c
View File

@ -1,111 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_12 Llano PCI tables with values as defined in BKDG
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x10
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "cpuEarlyInit.h"
#include "cpuFamilyTranslation.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_CPU_FAMILY_0X12_LN_F12LNMICROCODEPATCHTABLES_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
extern CONST MICROCODE_PATCHES ROMDATA *CpuF12LnMicroCodePatchArray[];
extern CONST UINT8 ROMDATA CpuF12LnNumberOfMicrocodePatches;
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
GetF12LnMicroCodePatchesStruct (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **LnUcodePtr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
* Returns a table containing the appropriate microcode patches.
*
* @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[out] LnUcodePtr Points to the first entry in the table.
* @param[out] NumberOfElements Number of valid entries in the table.
* @param[in] StdHeader Header for library and services.
*
*/
VOID
GetF12LnMicroCodePatchesStruct (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **LnUcodePtr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
*NumberOfElements = CpuF12LnNumberOfMicrocodePatches;
*LnUcodePtr = &CpuF12LnMicroCodePatchArray[0];
}

3
src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/LN/Makefile.inc
View File

@ -1,3 +0,0 @@
libagesa-y += F12LnEquivalenceTable.c
libagesa-y += F12LnLogicalIdTables.c
libagesa-y += F12LnMicrocodePatchTables.c

23
src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/Makefile.inc
View File

@ -1,23 +0,0 @@
libagesa-y += F12C6State.c
libagesa-y += F12Cpb.c
libagesa-y += F12IoCstate.c
libagesa-y += F12MicrocodePatch03000002.c
libagesa-y += F12MicrocodePatch0300000e.c
libagesa-y += F12MicrocodePatch03000027.c
libagesa-y += cpuCommonF12Utilities.c
libagesa-y += cpuF12BrandId.c
libagesa-y += cpuF12BrandIdFm1.c
libagesa-y += cpuF12BrandIdFs1.c
libagesa-y += cpuF12CacheDefaults.c
libagesa-y += cpuF12Dmi.c
libagesa-y += cpuF12EarlyNbPstateInit.c
libagesa-y += cpuF12MsrTables.c
libagesa-y += cpuF12PciTables.c
libagesa-y += cpuF12PerCorePciTables.c
libagesa-y += cpuF12PowerCheck.c
libagesa-y += cpuF12PowerMgmtSystemTables.c
libagesa-y += cpuF12PowerPlane.c
libagesa-y += cpuF12Pstate.c
libagesa-y += cpuF12SoftwareThermal.c
libagesa-y += cpuF12Utilities.c
libagesa-y += cpuF12WheaInitDataTables.c

572
src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuCommonF12Utilities.c
View File

@ -1,572 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_12 specific utility functions.
*
* Provides numerous utility functions specific to family 12h.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/FAMILY/0x12
* @e \$Revision: 49553 $ @e \$Date: 2011-03-25 08:55:17 +0800 (Fri, 25 Mar 2011) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "cpuRegisters.h"
#include "cpuServices.h"
#include "cpuFamilyTranslation.h"
#include "cpuCommonF12Utilities.h"
#include "cpuF12PowerMgmt.h"
#include "OptionFamily12hEarlySample.h"
#include "NbSmuLib.h"
#include "GnbRegistersLN.h"
#include "F12PackageType.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_CPU_FAMILY_0X12_CPUCOMMONF12UTILITIES_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
extern F12_ES_CORE_SUPPORT F12EarlySampleCoreSupport;
#define F12_DDR1333_ENCODED_MEMCLK (0xE)
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
CONST UINT16 ROMDATA F12MaxNbFreqAtMinVidFreqTable[] =
{
25, // 00000b
50, // 00001b
100, // 00010b
150, // 00011b
167, // 00100b
183, // 00101b
200, // 00110b
217, // 00111b
233, // 01000b
250, // 01001b
267, // 01010b
283, // 01011b
300, // 01100b
317, // 01101b
333, // 01110b
350, // 01111b
366, // 10000b
383, // 10001b
400, // 10010b
417, // 10011b
433, // 10100b
450, // 10101b
467, // 10110b
483, // 10111b
500, // 11000b
517, // 11001b
533, // 11010b
550, // 11011b
563, // 11100b
575, // 11101b
588, // 11110b
600 // 11111b
};
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
UINT32
STATIC
RoundedDivision (
IN UINT32 Dividend,
IN UINT32 Divisor
);
UINT32
F12GetApCoreNumber (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CONFIG_PARAMS *StdHeader
);
CORE_ID_POSITION
F12CpuAmdCoreIdPositionInInitialApicId (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
* Set warm reset status and count
*
* @CpuServiceMethod{::F_CPU_SET_WARM_RESET_FLAG}.
*
* This function will use bit9, and bit 10 of register F0x6C as a warm reset status and count.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] StdHeader Handle of Header for calling lib functions and services.
* @param[in] Request Indicate warm reset status
*
*/
VOID
F12SetAgesaWarmResetFlag (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CONFIG_PARAMS *StdHeader,
IN WARM_RESET_REQUEST *Request
)
{
PCI_ADDR PciAddress;
UINT32 PciData;
PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_0, HT_INIT_CTRL);
LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
// bit[5] - indicate a warm reset is or is not required
PciData &= ~(HT_INIT_BIOS_RST_DET_0);
PciData = PciData | (Request->RequestBit << 5);
// bit[10,9] - indicate warm reset status and count
PciData &= ~(HT_INIT_BIOS_RST_DET_1 | HT_INIT_BIOS_RST_DET_2);
PciData |= Request->StateBits << 9;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
}
/*---------------------------------------------------------------------------------------*/
/**
* Get warm reset status and count
*
* @CpuServiceMethod{::F_CPU_GET_WARM_RESET_FLAG}.
*
* This function will bit9, and bit 10 of register F0x6C as a warm reset status and count.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] StdHeader Config handle for library and services
* @param[out] Request Indicate warm reset status
*
*/
VOID
F12GetAgesaWarmResetFlag (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CONFIG_PARAMS *StdHeader,
OUT WARM_RESET_REQUEST *Request
)
{
PCI_ADDR PciAddress;
UINT32 PciData;
PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_0, HT_INIT_CTRL);
LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
// bit[5] - indicate a warm reset is or is not required
Request->RequestBit = (UINT8) ((PciData & HT_INIT_BIOS_RST_DET_0) >> 5);
// bit[10,9] - indicate warm reset status and count
Request->StateBits = (UINT8) ((PciData & (HT_INIT_BIOS_RST_DET_1 | HT_INIT_BIOS_RST_DET_2)) >> 9);
}
/*---------------------------------------------------------------------------------------*/
/**
* Use the Mailbox Register to get the Ap Mailbox info for the current core.
*
* @CpuServiceMethod{::F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE}.
*
* Access the mailbox register used with this NB family. This is valid until the
* point that some init code initializes the mailbox register for its normal use.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[out] ApMailboxInfo The AP Mailbox info
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
*/
VOID
F12GetApMailboxFromHardware (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT AP_MAILBOXES *ApMailboxInfo,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
// For Family 12h, we will return socket 0, node 0, module 0, module type 0, and 0 for
// the system degree
ApMailboxInfo->ApMailInfo.Info = (UINT32) 0x00000000;
ApMailboxInfo->ApMailExtInfo.Info = (UINT32) 0x00000000;
}
/*---------------------------------------------------------------------------------------*/
/**
* Get this AP's system core number from hardware.
*
* @CpuServiceMethod{::F_CPU_GET_AP_CORE_NUMBER}.
*
* Returns the system core number. For family 12h, this is simply the
* initial APIC ID.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
* @return The AP's unique core number
*/
UINT32
F12GetApCoreNumber (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
CPUID_DATA Cpuid;
LibAmdCpuidRead (0x1, &Cpuid, StdHeader);
return ((Cpuid.EBX_Reg >> 24) & 0xFF);
}
/*---------------------------------------------------------------------------------------*/
/**
* Return a number zero or one, based on the Core ID position in the initial APIC Id.
*
* @CpuServiceMethod{::F_CORE_ID_POSITION_IN_INITIAL_APIC_ID}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
* @retval CoreIdPositionZero Core Id is not low
* @retval CoreIdPositionOne Core Id is low
*/
CORE_ID_POSITION
F12CpuAmdCoreIdPositionInInitialApicId (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
return (CoreIdPositionOne);
}
/*---------------------------------------------------------------------------------------*/
/**
* Sets up a valid set of NB P-states based on the value of MEMCLK, transitions
* to the desired NB P-state, and returns the current NB frequency in megahertz.
*
* @param[in] TargetMemclk The target MEMCLK in megahertz, or zero to
* indicate NB P-state change only.
* @param[in] TargetMemclkEncoded The target MEMCLK's register encoding.
* @param[in] TargetNbPstate The NB P-state to exit in.
* @param[out] CurrentNbFreq Current NB operating frequency in megahertz.
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
* @retval TRUE Transition to TargetNbPstate was successful.
* @retval FALSE Transition to TargetNbPstate was unsuccessful.
*/
BOOLEAN
F12NbPstateInit (
IN UINT32 TargetMemclk,
IN UINT32 TargetMemclkEncoded,
IN UINT32 TargetNbPstate,
OUT UINT32 *CurrentNbFreq,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 EncodedNbPs1Vid;
UINT32 EncodedNbPs0NclkDiv;
UINT32 EncodedNbPs1NclkDiv;
UINT32 NbP0Cof;
UINT32 NbP1Cof;
UINT32 NbPstateNumerator;
UINT32 TargetNumerator;
UINT32 TargetDenominator;
UINT32 PkgType;
BOOLEAN ReturnStatus;
BOOLEAN WaitForTransition;
BOOLEAN EnableAltVddNb;
PCI_ADDR PciAddress;
D18F3xD4_STRUCT Cptc0;
D18F3xDC_STRUCT Cptc2;
D18F6x90_STRUCT NbPsCfgLow;
D18F6x98_STRUCT NbPsCtrlSts;
FCRxFE00_6000_STRUCT FCRxFE00_6000;
FCRxFE00_6002_STRUCT FCRxFE00_6002;
FCRxFE00_7006_STRUCT FCRxFE00_7006;
FCRxFE00_7009_STRUCT FCRxFE00_7009;
FCRxFE00_705F_STRUCT FCRxFE00_705F;
// F12 only supports NB P0 and NB P1
ASSERT (TargetNbPstate < 2);
WaitForTransition = FALSE;
ReturnStatus = TRUE;
EnableAltVddNb = FALSE;
// Get D18F3xD4[MainPllOpFreqId] frequency
PciAddress.AddressValue = CPTC0_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &Cptc0.Value, StdHeader);
// Calculate the numerator to be used for NB P-state calculations
NbPstateNumerator = (UINT32) (4 * ((Cptc0.Field.MainPllOpFreqId + 0x10) * 100));
if (TargetMemclk != 0) {
// Determine the appropriate numerator / denominator of the target memclk
switch (TargetMemclk) {
case DDR800_FREQUENCY:
TargetNumerator = 400;
TargetDenominator = 1;
break;
case DDR1066_FREQUENCY:
TargetNumerator = 1600;
TargetDenominator = 3;
break;
case DDR1333_FREQUENCY:
TargetNumerator = 2000;
TargetDenominator = 3;
break;
case DDR1600_FREQUENCY:
TargetNumerator = 800;
TargetDenominator = 1;
break;
case DDR1866_FREQUENCY:
TargetNumerator = 2800;
TargetDenominator = 3;
break;
default:
// An invalid memclk has been passed in.
ASSERT (FALSE);
TargetNumerator = TargetMemclk;
TargetDenominator = 1;
break;
}
FCRxFE00_6000.Value = NbSmuReadEfuse (FCRxFE00_6000_ADDRESS, StdHeader);
FCRxFE00_6002.Value = NbSmuReadEfuse (FCRxFE00_6002_ADDRESS, StdHeader);
FCRxFE00_7006.Value = NbSmuReadEfuse (FCRxFE00_7006_ADDRESS, StdHeader);
FCRxFE00_7009.Value = NbSmuReadEfuse (FCRxFE00_7009_ADDRESS, StdHeader);
F12EarlySampleCoreSupport.F12NbPstateInitHook (&FCRxFE00_6000,
&FCRxFE00_6002,
&FCRxFE00_7006,
&FCRxFE00_7009,
NbPstateNumerator,
StdHeader);
// Determine NB P0 settings
if ((TargetNumerator * FCRxFE00_7009.Field.NbPs0NclkDiv) < (NbPstateNumerator * TargetDenominator)) {
// Program D18F3xDC[NbPs0NclkDiv] to the minimum divisor where
// (target memclk frequency >= (D18F3xD4[MainPllOpFreqId] freq) / divisor)
EncodedNbPs0NclkDiv = ((NbPstateNumerator * TargetDenominator) / TargetNumerator);
if (((NbPstateNumerator * TargetDenominator) % TargetNumerator) != 0) {
EncodedNbPs0NclkDiv++;
}
// Ensure that the encoded divisor is even to give 50% duty cycle
EncodedNbPs0NclkDiv = ((EncodedNbPs0NclkDiv + 1) & 0xFFFFFFFE);
ASSERT (EncodedNbPs0NclkDiv >= 8);
ASSERT (EncodedNbPs0NclkDiv <= 0x3F);
} else {
EncodedNbPs0NclkDiv = FCRxFE00_7009.Field.NbPs0NclkDiv;
}
// Check to see if the DIMMs are too fast for the CPU (NB P0 COF < (Memclk / 2))
if ((TargetNumerator * EncodedNbPs0NclkDiv) > (NbPstateNumerator * TargetDenominator * 2)) {
// Indicate the error to the memory code so the DIMMs can be derated.
ReturnStatus = FALSE;
}
// Apply the appropriate P0 frequency
PciAddress.AddressValue = CPTC2_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &Cptc2.Value, StdHeader);
if (Cptc2.Field.NbPs0NclkDiv != EncodedNbPs0NclkDiv) {
WaitForTransition = TRUE;
Cptc2.Field.NbPs0NclkDiv = EncodedNbPs0NclkDiv;
LibAmdPciWrite (AccessWidth32, PciAddress, &Cptc2.Value, StdHeader);
}
NbP0Cof = RoundedDivision (NbPstateNumerator, EncodedNbPs0NclkDiv);
// Determine NB P1 settings if necessary
PciAddress.AddressValue = NB_PSTATE_CFG_LOW_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCfgLow.Value, StdHeader);
if (NbPsCfgLow.Field.NbPsCap == 1) {
if ((TargetNumerator * FCRxFE00_7006.Field.NbPs1NclkDiv) > (NbPstateNumerator * TargetDenominator * 2)) {
// Program D18F6x90[NbPs1NclkDiv] to the maximum divisor where
// (target memclk frequency / 2 <= (D18F3xD4[MainPllOpFreqId] freq) / divisor)
EncodedNbPs1NclkDiv = ((NbPstateNumerator * TargetDenominator * 2) / TargetNumerator);
// Ensure that the encoded divisor is even to give 50% duty cycle
EncodedNbPs1NclkDiv &= 0xFFFFFFFE;
ASSERT (EncodedNbPs1NclkDiv >= 8);
ASSERT (EncodedNbPs1NclkDiv <= 0x3F);
// Calculate the new effective P1 frequency to determine the voltage
NbP1Cof = RoundedDivision (NbPstateNumerator, EncodedNbPs1NclkDiv);
if (NbP1Cof <= F12MaxNbFreqAtMinVidFreqTable[FCRxFE00_7006.Field.MaxNbFreqAtMinVid]) {
// Program D18F6x90[NbPs1Vid] = FCRxFE00_6002[NbPs1VidAddl]
EncodedNbPs1Vid = FCRxFE00_6002.Field.NbPs1VidAddl;
} else {
// Program D18F6x90[NbPs1Vid] = FCRxFE00_6002[NbPs1VidHigh]
EncodedNbPs1Vid = FCRxFE00_6002.Field.NbPs1VidHigh;
}
} else {
// Fused frequency and voltage are legal
EncodedNbPs1Vid = FCRxFE00_6000.Field.NbPs1Vid;
EncodedNbPs1NclkDiv = FCRxFE00_7006.Field.NbPs1NclkDiv;
NbP1Cof = RoundedDivision (NbPstateNumerator, EncodedNbPs1NclkDiv);
}
if (NbP0Cof < NbP1Cof) {
// NB P1 frequency is faster than NB P0. Fix it up by slowing
// P1 to match P0.
EncodedNbPs1NclkDiv = EncodedNbPs0NclkDiv;
NbP1Cof = NbP0Cof;
}
// Program the new NB P1 settings
NbPsCfgLow.Field.NbPs1NclkDiv = EncodedNbPs1NclkDiv;
NbPsCfgLow.Field.NbPs1Vid = EncodedNbPs1Vid;
LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCfgLow.Value, StdHeader);
} else {
// NB P-states are not enabled
NbP1Cof = 0;
}
*CurrentNbFreq = NbP0Cof;
if (WaitForTransition) {
// Ensure that the frequency has settled before returning to memory code.
PciAddress.AddressValue = CPTC2_PCI_ADDR;
do {
LibAmdPciRead (AccessWidth32, PciAddress, &Cptc2.Value, StdHeader);
} while (Cptc2.Field.NclkFreqDone != 1);
}
} else {
// Get NB P0 COF
PciAddress.AddressValue = CPTC2_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &Cptc2.Value, StdHeader);
NbP0Cof = RoundedDivision (NbPstateNumerator, Cptc2.Field.NbPs0NclkDiv);
// Read NB P-state status
PciAddress.AddressValue = NB_PSTATE_CTRL_STS_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlSts.Value, StdHeader);
FCRxFE00_705F.Value = NbSmuReadEfuse (FCRxFE00_705F_ADDRESS, StdHeader);
if (FCRxFE00_705F.Field.GnbIdleAdjustVid != 0) {
PkgType = LibAmdGetPackageType (StdHeader);
if ((PkgType == PACKAGE_TYPE_FP1) || ((PkgType == PACKAGE_TYPE_FS1) && (TargetMemclkEncoded <= F12_DDR1333_ENCODED_MEMCLK))) {
EnableAltVddNb = TRUE;
}
}
// Read low config register
PciAddress.AddressValue = NB_PSTATE_CFG_LOW_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCfgLow.Value, StdHeader);
if (TargetNbPstate == 1) {
// If target is P1, the CPU MUST be in P0, otherwise the P1 settings
// cannot be realized. This is a programming error.
ASSERT (NbPsCtrlSts.Field.NbPs1Act == 0);
if (NbPsCfgLow.Field.NbPsCap == 1) {
// The part is capable of NB P-states. Transition to P1.
if (EnableAltVddNb) {
NbPsCfgLow.Field.NbPs1Vid += FCRxFE00_705F.Field.GnbIdleAdjustVid;
LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCfgLow.Value, StdHeader);
}
NbPsCfgLow.Field.NbPsForceSel = 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCfgLow.Value, StdHeader);
WaitForTransition = TRUE;
*CurrentNbFreq = RoundedDivision (NbPstateNumerator, NbPsCfgLow.Field.NbPs1NclkDiv);
} else {
// No NB P-states. Return FALSE, and set current frequency to P0.
*CurrentNbFreq = NbP0Cof;
ReturnStatus = FALSE;
}
} else {
// Target P0
*CurrentNbFreq = NbP0Cof;
if (NbPsCtrlSts.Field.NbPs1Act != 0) {
// Request transition to P0
if (EnableAltVddNb) {
NbPsCfgLow.Field.NbPs1Vid -= FCRxFE00_705F.Field.GnbIdleAdjustVid;
}
NbPsCfgLow.Field.NbPsForceSel = 0;
LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCfgLow.Value, StdHeader);
WaitForTransition = TRUE;
}
}
if (WaitForTransition) {
// Ensure that the frequency has settled before returning to memory code.
PciAddress.AddressValue = NB_PSTATE_CTRL_STS_PCI_ADDR;
do {
LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlSts.Value, StdHeader);
} while (NbPsCtrlSts.Field.NbPs1Act != TargetNbPstate);
}
}
return ReturnStatus;
}
/*---------------------------------------------------------------------------------------*/
/**
* Performs integer division, and rounds the quotient up if the remainder is greater
* than or equal to 50% of the divisor.
*
* @param[in] Dividend The target MEMCLK in megahertz.
* @param[in] Divisor The target MEMCLK's register encoding.
*
* @return The rounded quotient
*/
UINT32
STATIC
RoundedDivision (
IN UINT32 Dividend,
IN UINT32 Divisor
)
{
UINT32 Quotient;
ASSERT (Divisor != 0);
Quotient = Dividend / Divisor;
if (((Dividend % Divisor) * 2) >= Divisor) {
Quotient++;
}
return Quotient;
}

102
src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuCommonF12Utilities.h
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@ -1,102 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_12 specific utility functions.
*
* Provides numerous utility functions specific to family 12h.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/FAMILY/0x12
* @e \$Revision: 49553 $ @e \$Date: 2011-03-25 08:55:17 +0800 (Fri, 25 Mar 2011) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _CPU_COMMON_F12_UTILITES_H_
#define _CPU_COMMON_F12_UTILITES_H_
/*---------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*---------------------------------------------------------------------------------------
*/
VOID
F12SetAgesaWarmResetFlag (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CONFIG_PARAMS *StdHeader,
IN WARM_RESET_REQUEST *Request
);
VOID
F12GetAgesaWarmResetFlag (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CONFIG_PARAMS *StdHeader,
OUT WARM_RESET_REQUEST *Request
);
VOID
F12GetApMailboxFromHardware (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT AP_MAILBOXES *ApMailboxInfo,
IN AMD_CONFIG_PARAMS *StdHeader
);
BOOLEAN
F12NbPstateInit (
IN UINT32 TargetMemclk,
IN UINT32 TargetMemclkEncoded,
IN UINT32 TargetNbPstate,
OUT UINT32 *CurrentNbFreq,
IN AMD_CONFIG_PARAMS *StdHeader
);
#endif // _CPU_COMMON_F12_UTILITES_H_

157
src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12BrandId.c
View File

@ -1,157 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD CPU BrandId related functions and structures.
*
* Contains code that provides CPU BrandId information
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "cpuEarlyInit.h"
#include "cpuFamilyTranslation.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_CPU_FAMILY_0X12_CPUF12BRANDID_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
extern CPU_BRAND_TABLE *F12BrandIdString1Tables[];
extern CPU_BRAND_TABLE *F12BrandIdString2Tables[];
extern CONST UINT8 F12BrandIdString1TableCount;
extern CONST UINT8 F12BrandIdString2TableCount;
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
VOID
GetF12BrandIdString1 (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **BrandString1Ptr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
);
VOID
GetF12BrandIdString2 (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **BrandString2Ptr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*---------------------------------------------------------------------------------------*/
/**
* Returns a table containing the appropriate beginnings of the CPU brandstring.
*
* @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[out] BrandString1Ptr Points to the first entry in the table.
* @param[out] NumberOfElements Number of valid entries in the table.
* @param[in] StdHeader Header for library and services.
*
*/
VOID
GetF12BrandIdString1 (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **BrandString1Ptr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
CPU_BRAND_TABLE **TableEntryPtr;
TableEntryPtr = &F12BrandIdString1Tables[0];
*BrandString1Ptr = TableEntryPtr;
*NumberOfElements = F12BrandIdString1TableCount;
}
/*---------------------------------------------------------------------------------------*/
/**
* Returns a table containing the appropriate endings of the CPU brandstring.
*
* @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[out] BrandString2Ptr Points to the first entry in the table.
* @param[out] NumberOfElements Number of valid entries in the table.
* @param[in] StdHeader Header for library and services.
*
*/
VOID
GetF12BrandIdString2 (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **BrandString2Ptr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
CPU_BRAND_TABLE **TableEntryPtr;
TableEntryPtr = &F12BrandIdString2Tables[0];
*BrandString2Ptr = TableEntryPtr;
*NumberOfElements = F12BrandIdString2TableCount;
}

232
src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12BrandIdFm1.c
View File

@ -1,232 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD CPU BrandId related functions and structures.
*
* Contains code that provides CPU BrandId information
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x12
* @e \$Revision: 52412 $ @e \$Date: 2011-05-06 08:13:56 +0800 (Fri, 06 May 2011) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "cpuEarlyInit.h"
#include "F12PackageType.h"
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
// String1
CONST CHAR8 ROMDATA str_F12_Fm1_AMD_A4_3[] = "AMD A4-3";
CONST CHAR8 ROMDATA str_F12_Fm1_AMD_A4_33[] = "AMD A4-33";
CONST CHAR8 ROMDATA str_F12_Fm1_AMD_A4_34[] = "AMD A4-34";
CONST CHAR8 ROMDATA str_F12_Fm1_AMD_A6_3[] = "AMD A6-3";
CONST CHAR8 ROMDATA str_F12_Fm1_AMD_A6_34[] = "AMD A6-34";
CONST CHAR8 ROMDATA str_F12_Fm1_AMD_A6_35[] = "AMD A6-35";
CONST CHAR8 ROMDATA str_F12_Fm1_AMD_A6_36[] = "AMD A6-36";
CONST CHAR8 ROMDATA str_F12_Fm1_AMD_A8_3[] = "AMD A8-3";
CONST CHAR8 ROMDATA str_F12_Fm1_AMD_A8_35[] = "AMD A8-35";
CONST CHAR8 ROMDATA str_F12_Fm1_AMD_A8_38[] = "AMD A8-38";
CONST CHAR8 ROMDATA str_F12_Fm1_AMD_E2_1[] = "AMD E2-1";
CONST CHAR8 ROMDATA str_F12_Fm1_AMD_E2_12[] = "AMD E2-12";
CONST CHAR8 ROMDATA str_F12_Fm1_AMD_E2_3[] = "AMD E2-3";
CONST CHAR8 ROMDATA str_F12_Fm1_AMD_E2_32[] = "AMD E2-32";
CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Athlon_II[] = "AMD Athlon(tm) II ";
CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Athlon_II_1[] = "AMD Athlon(tm) II 1";
CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Athlon_II_X2[] = "AMD Athlon(tm) II X2 ";
CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Athlon_II_X2_2[] = "AMD Athlon(tm) II X2 2";
CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Athlon_II_X3[] = "AMD Athlon(tm) II X3 ";
CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Athlon_II_X3_3[] = "AMD Athlon(tm) II X3 3";
CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Athlon_II_X3_4[] = "AMD Athlon(tm) II X3 4";
CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Athlon_II_X4_4[] = "AMD Athlon(tm) II X4 4";
CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Athlon_II_X4_6[] = "AMD Athlon(tm) II X4 6";
CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Athlon_II_X4[] = "AMD Athlon(tm) II X4 ";
CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Athlon_FM1[] = "AMD Athlon(tm) FM1 ";
CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Athlon_FM1_X2[] = "AMD Athlon(tm) FM1 X2 ";
CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Athlon_FM1_X3[] = "AMD Athlon(tm) FM1 X3 ";
CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Athlon_FM1_X4[] = "AMD Athlon(tm) FM1 X4 ";
CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Sempron_1[] = "AMD Sempron(tm) 1";
CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Sempron_X2_1[] = "AMD Sempron(tm) X2 1";
CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Sempron_X2_2[] = "AMD Sempron(tm) X2 2";
CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Sempron_II[] = "AMD Sempron(tm) II ";
CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Sempron_II_1[] = "AMD Sempron(tm) II 1";
CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Sempron_II_X2[] = "AMD Sempron(tm) II X2 ";
CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Sempron_II_X2_2[] = "AMD Sempron(tm) II X2 2";
CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Sempron_II_X3[] = "AMD Sempron(tm) II X3 ";
CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Sempron_II_X3_3[] = "AMD Sempron(tm) II X3 3";
CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Sempron_II_X4_4[] = "AMD Sempron(tm) II X4 4";
CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Sempron_II_X4[] = "AMD Sempron(tm) II X4 ";
CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Sempron_FM1[] = "AMD Sempron(tm) FM1 ";
CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Sempron_FM1_X2[] = "AMD Sempron(tm) FM1 X2 ";
CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Sempron_FM1_X3[] = "AMD Sempron(tm) FM1 X3 ";
CONST CHAR8 ROMDATA str_F12_Fm1_AMD_Sempron_FM1_X4[] = "AMD Sempron(tm) FM1 X4 ";
// String2
CONST CHAR8 ROMDATA str_F12_Fm1_APU[] = " APU with Radeon(tm) HD Graphics";
CONST CHAR8 ROMDATA str_F12_Fm1_0_APU[] = "0 APU with Radeon(tm) HD Graphics";
CONST CHAR8 ROMDATA str_F12_Fm1_P_APU[] = "P APU with Radeon(tm) HD Graphics";
CONST CHAR8 ROMDATA str_F12_Fm1_0P_APU[] = "0P APU with Radeon(tm) HD Graphics";
CONST CHAR8 ROMDATA str_F12_Fm1_Processor[] = " Processor";
CONST CHAR8 ROMDATA str_F12_Fm1_0_Processor[] = "0 Processor";
CONST CHAR8 ROMDATA str_F12_Fm1_DC_Processor[] = " Dual-Core Processor";
CONST CHAR8 ROMDATA str_F12_Fm1_0_DC_Processor[] = "0 Dual-Core Processor";
CONST CHAR8 ROMDATA str_F12_Fm1_TC_Processor[] = " Triple-Core Processor";
CONST CHAR8 ROMDATA str_F12_Fm1_0_TC_Processor[] = "0 Triple-Core Processor";
CONST CHAR8 ROMDATA str_F12_Fm1_QC_Processor[] = " Quad-Core Processor";
CONST CHAR8 ROMDATA str_F12_Fm1_0_QC_Processor[] = "0 Quad-Core Processor";
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
CONST AMD_CPU_BRAND ROMDATA CpuF12LnBrandIdString1ArrayFm1[] =
{
// FM1
{1, 0, 1, LN_SOCKET_FM1, str_F12_Fm1_AMD_E2_12, sizeof (str_F12_Fm1_AMD_E2_12)},
{1, 0, 2, LN_SOCKET_FM1, str_F12_Fm1_AMD_Sempron_II_1, sizeof (str_F12_Fm1_AMD_Sempron_II_1)},
{1, 0, 3, LN_SOCKET_FM1, str_F12_Fm1_AMD_Athlon_II_1, sizeof (str_F12_Fm1_AMD_Athlon_II_1)},
{1, 0, 4, LN_SOCKET_FM1, str_F12_Fm1_AMD_E2_1, sizeof (str_F12_Fm1_AMD_E2_1)},
{1, 0, 5, LN_SOCKET_FM1, str_F12_Fm1_AMD_Sempron_II, sizeof (str_F12_Fm1_AMD_Sempron_II)},
{1, 0, 6, LN_SOCKET_FM1, str_F12_Fm1_AMD_Athlon_II, sizeof (str_F12_Fm1_AMD_Athlon_II)},
{1, 0, 7, LN_SOCKET_FM1, str_F12_Fm1_AMD_Sempron_FM1, sizeof (str_F12_Fm1_AMD_Sempron_FM1)},
{1, 0, 8, LN_SOCKET_FM1, str_F12_Fm1_AMD_Athlon_FM1, sizeof (str_F12_Fm1_AMD_Athlon_FM1)},
{1, 0, 9, LN_SOCKET_FM1, str_F12_Fm1_AMD_Sempron_1, sizeof (str_F12_Fm1_AMD_Sempron_1)},
{2, 0, 1, LN_SOCKET_FM1, str_F12_Fm1_AMD_A4_33, sizeof (str_F12_Fm1_AMD_A4_33)},
{2, 0, 2, LN_SOCKET_FM1, str_F12_Fm1_AMD_E2_32, sizeof (str_F12_Fm1_AMD_E2_32)},
{2, 0, 3, LN_SOCKET_FM1, str_F12_Fm1_AMD_Sempron_II_X2_2, sizeof (str_F12_Fm1_AMD_Sempron_II_X2_2)},
{2, 0, 4, LN_SOCKET_FM1, str_F12_Fm1_AMD_Athlon_II_X2_2, sizeof (str_F12_Fm1_AMD_Athlon_II_X2_2)},
{2, 0, 5, LN_SOCKET_FM1, str_F12_Fm1_AMD_A4_34, sizeof (str_F12_Fm1_AMD_A4_34)},
{2, 0, 6, LN_SOCKET_FM1, str_F12_Fm1_AMD_A4_3, sizeof (str_F12_Fm1_AMD_A4_3)},
{2, 0, 7, LN_SOCKET_FM1, str_F12_Fm1_AMD_E2_3, sizeof (str_F12_Fm1_AMD_E2_3)},
{2, 0, 8, LN_SOCKET_FM1, str_F12_Fm1_AMD_Sempron_II_X2, sizeof (str_F12_Fm1_AMD_Sempron_II_X2)},
{2, 0, 9, LN_SOCKET_FM1, str_F12_Fm1_AMD_Athlon_II_X2, sizeof (str_F12_Fm1_AMD_Athlon_II_X2)},
{2, 0, 0xA, LN_SOCKET_FM1, str_F12_Fm1_AMD_Sempron_FM1_X2, sizeof (str_F12_Fm1_AMD_Sempron_FM1_X2)},
{2, 0, 0xB, LN_SOCKET_FM1, str_F12_Fm1_AMD_Athlon_FM1_X2, sizeof (str_F12_Fm1_AMD_Athlon_FM1_X2)},
{2, 0, 0xC, LN_SOCKET_FM1, str_F12_Fm1_AMD_Sempron_X2_1, sizeof (str_F12_Fm1_AMD_Sempron_X2_1)},
{2, 0, 0xD, LN_SOCKET_FM1, str_F12_Fm1_AMD_Sempron_X2_2, sizeof (str_F12_Fm1_AMD_Sempron_X2_2)},
{3, 0, 1, LN_SOCKET_FM1, str_F12_Fm1_AMD_A6_34, sizeof (str_F12_Fm1_AMD_A6_34)},
{3, 0, 2, LN_SOCKET_FM1, str_F12_Fm1_AMD_Sempron_II_X3_3, sizeof (str_F12_Fm1_AMD_Sempron_II_X3_3)},
{3, 0, 3, LN_SOCKET_FM1, str_F12_Fm1_AMD_Athlon_II_X3_3, sizeof (str_F12_Fm1_AMD_Athlon_II_X3_3)},
{3, 0, 4, LN_SOCKET_FM1, str_F12_Fm1_AMD_A6_36, sizeof (str_F12_Fm1_AMD_A6_36)},
{3, 0, 5, LN_SOCKET_FM1, str_F12_Fm1_AMD_A6_35, sizeof (str_F12_Fm1_AMD_A6_35)},
{3, 0, 6, LN_SOCKET_FM1, str_F12_Fm1_AMD_A6_3, sizeof (str_F12_Fm1_AMD_A6_3)},
{3, 0, 7, LN_SOCKET_FM1, str_F12_Fm1_AMD_Sempron_II_X3, sizeof (str_F12_Fm1_AMD_Sempron_II_X3)},
{3, 0, 8, LN_SOCKET_FM1, str_F12_Fm1_AMD_Athlon_II_X3, sizeof (str_F12_Fm1_AMD_Athlon_II_X3)},
{3, 0, 9, LN_SOCKET_FM1, str_F12_Fm1_AMD_Sempron_FM1_X3, sizeof (str_F12_Fm1_AMD_Sempron_FM1_X3)},
{3, 0, 0xA, LN_SOCKET_FM1, str_F12_Fm1_AMD_Athlon_FM1_X3, sizeof (str_F12_Fm1_AMD_Athlon_FM1_X3)},
{3, 0, 0xB, LN_SOCKET_FM1, str_F12_Fm1_AMD_Athlon_II_X3_4, sizeof (str_F12_Fm1_AMD_Athlon_II_X3_4)},
{4, 0, 1, LN_SOCKET_FM1, str_F12_Fm1_AMD_A8_35, sizeof (str_F12_Fm1_AMD_A8_35)},
{4, 0, 2, LN_SOCKET_FM1, str_F12_Fm1_AMD_A6_34, sizeof (str_F12_Fm1_AMD_A6_34)},
{4, 0, 3, LN_SOCKET_FM1, str_F12_Fm1_AMD_Sempron_II_X4_4, sizeof (str_F12_Fm1_AMD_Sempron_II_X4_4)},
{4, 0, 4, LN_SOCKET_FM1, str_F12_Fm1_AMD_Athlon_II_X4_4, sizeof (str_F12_Fm1_AMD_Athlon_II_X4_4)},
{4, 0, 5, LN_SOCKET_FM1, str_F12_Fm1_AMD_A8_38, sizeof (str_F12_Fm1_AMD_A8_38)},
{4, 0, 6, LN_SOCKET_FM1, str_F12_Fm1_AMD_A6_36, sizeof (str_F12_Fm1_AMD_A6_36)},
{4, 0, 7, LN_SOCKET_FM1, str_F12_Fm1_AMD_A8_3, sizeof (str_F12_Fm1_AMD_A8_3)},
{4, 0, 8, LN_SOCKET_FM1, str_F12_Fm1_AMD_A6_3, sizeof (str_F12_Fm1_AMD_A6_3)},
{4, 0, 9, LN_SOCKET_FM1, str_F12_Fm1_AMD_Sempron_II_X4, sizeof (str_F12_Fm1_AMD_Sempron_II_X4)},
{4, 0, 0xA, LN_SOCKET_FM1, str_F12_Fm1_AMD_Athlon_II_X4, sizeof (str_F12_Fm1_AMD_Athlon_II_X4)},
{4, 0, 0xB, LN_SOCKET_FM1, str_F12_Fm1_AMD_Sempron_FM1_X4, sizeof (str_F12_Fm1_AMD_Sempron_FM1_X4)},
{4, 0, 0xC, LN_SOCKET_FM1, str_F12_Fm1_AMD_Athlon_FM1_X4, sizeof (str_F12_Fm1_AMD_Athlon_FM1_X4)},
{4, 0, 0xD, LN_SOCKET_FM1, str_F12_Fm1_AMD_Athlon_II_X4_6, sizeof (str_F12_Fm1_AMD_Athlon_II_X4_6)},
}; //Cores, page, index, socket, stringstart, stringlength
CONST AMD_CPU_BRAND ROMDATA CpuF12LnBrandIdString2ArrayFm1[] =
{
// FM1
{1, 0, 1, LN_SOCKET_FM1, str_F12_Fm1_APU, sizeof (str_F12_Fm1_APU)},
{1, 0, 2, LN_SOCKET_FM1, str_F12_Fm1_Processor, sizeof (str_F12_Fm1_Processor)},
{1, 0, 3, LN_SOCKET_FM1, str_F12_Fm1_P_APU, sizeof (str_F12_Fm1_P_APU)},
{1, 0, 4, LN_SOCKET_FM1, str_F12_Fm1_0_APU, sizeof (str_F12_Fm1_0_APU)},
{1, 0, 5, LN_SOCKET_FM1, str_F12_Fm1_0P_APU, sizeof (str_F12_Fm1_0P_APU)},
{1, 0, 6, LN_SOCKET_FM1, str_F12_Fm1_0_Processor, sizeof (str_F12_Fm1_0_Processor)},
{2, 0, 1, LN_SOCKET_FM1, str_F12_Fm1_APU, sizeof (str_F12_Fm1_APU)},
{2, 0, 2, LN_SOCKET_FM1, str_F12_Fm1_DC_Processor, sizeof (str_F12_Fm1_DC_Processor)},
{2, 0, 3, LN_SOCKET_FM1, str_F12_Fm1_P_APU, sizeof (str_F12_Fm1_P_APU)},
{2, 0, 4, LN_SOCKET_FM1, str_F12_Fm1_0_APU, sizeof (str_F12_Fm1_0_APU)},
{2, 0, 5, LN_SOCKET_FM1, str_F12_Fm1_0P_APU, sizeof (str_F12_Fm1_0P_APU)},
{2, 0, 6, LN_SOCKET_FM1, str_F12_Fm1_0_DC_Processor, sizeof (str_F12_Fm1_0_DC_Processor)},
{3, 0, 1, LN_SOCKET_FM1, str_F12_Fm1_APU, sizeof (str_F12_Fm1_APU)},
{3, 0, 2, LN_SOCKET_FM1, str_F12_Fm1_P_APU, sizeof (str_F12_Fm1_P_APU)},
{3, 0, 3, LN_SOCKET_FM1, str_F12_Fm1_TC_Processor, sizeof (str_F12_Fm1_TC_Processor)},
{3, 0, 4, LN_SOCKET_FM1, str_F12_Fm1_0_APU, sizeof (str_F12_Fm1_0_APU)},
{3, 0, 5, LN_SOCKET_FM1, str_F12_Fm1_0P_APU, sizeof (str_F12_Fm1_0P_APU)},
{3, 0, 6, LN_SOCKET_FM1, str_F12_Fm1_0_TC_Processor, sizeof (str_F12_Fm1_0_TC_Processor)},
{4, 0, 1, LN_SOCKET_FM1, str_F12_Fm1_APU, sizeof (str_F12_Fm1_APU)},
{4, 0, 2, LN_SOCKET_FM1, str_F12_Fm1_P_APU, sizeof (str_F12_Fm1_P_APU)},
{4, 0, 3, LN_SOCKET_FM1, str_F12_Fm1_QC_Processor, sizeof (str_F12_Fm1_QC_Processor)},
{4, 0, 4, LN_SOCKET_FM1, str_F12_Fm1_0_APU, sizeof (str_F12_Fm1_0_APU)},
{4, 0, 5, LN_SOCKET_FM1, str_F12_Fm1_0P_APU, sizeof (str_F12_Fm1_0P_APU)},
{4, 0, 6, LN_SOCKET_FM1, str_F12_Fm1_0_QC_Processor, sizeof (str_F12_Fm1_0_QC_Processor)},
}; //Cores, page, index, socket, stringstart, stringlength
CONST CPU_BRAND_TABLE ROMDATA F12LnBrandIdString1ArrayFm1 = {
(sizeof (CpuF12LnBrandIdString1ArrayFm1) / sizeof (AMD_CPU_BRAND)),
CpuF12LnBrandIdString1ArrayFm1
};
CONST CPU_BRAND_TABLE ROMDATA F12LnBrandIdString2ArrayFm1 = {
(sizeof (CpuF12LnBrandIdString2ArrayFm1) / sizeof (AMD_CPU_BRAND)),
CpuF12LnBrandIdString2ArrayFm1
};

181
src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12BrandIdFs1.c
View File

@ -1,181 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD CPU BrandId related functions and structures.
*
* Contains code that provides CPU BrandId information
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x12
* @e \$Revision: 46474 $ @e \$Date: 2011-02-03 05:46:17 +0800 (Thu, 03 Feb 2011) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "cpuEarlyInit.h"
#include "F12PackageType.h"
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
// String1
CONST CHAR8 ROMDATA str_F12_Fs1_AMD_A4_35[] = "AMD A4-35";
CONST CHAR8 ROMDATA str_F12_Fs1_AMD_A4_34[] = "AMD A4-34";
CONST CHAR8 ROMDATA str_F12_Fs1_AMD_A4_33[] = "AMD A4-33";
CONST CHAR8 ROMDATA str_F12_Fs1_AMD_A4_32[] = "AMD A4-32";
CONST CHAR8 ROMDATA str_F12_Fs1_AMD_E2_30[] = "AMD E2-30";
CONST CHAR8 ROMDATA str_F12_Fs1_AMD_E2_20[] = "AMD E2-20";
CONST CHAR8 ROMDATA str_F12_Fs1_AMD_E2_10[] = "AMD E2-10";
CONST CHAR8 ROMDATA str_F12_Fs1_AMD_A8_35[] = "AMD A8-35";
CONST CHAR8 ROMDATA str_F12_Fs1_AMD_A8_34[] = "AMD A8-34";
CONST CHAR8 ROMDATA str_F12_Fs1_AMD_A6_34[] = "AMD A6-34";
CONST CHAR8 ROMDATA str_F12_Fs1_AMD_A6_33[] = "AMD A6-33";
// String2
CONST CHAR8 ROMDATA str_F12_Fs1_M_APU[] = "M APU with Radeon(tm) HD Graphics";
CONST CHAR8 ROMDATA str_F12_Fs1_MX_APU[] = "MX APU with Radeon(tm) HD Graphics";
CONST CHAR8 ROMDATA str_F12_Fs1_ML_APU[] = "ML APU with Radeon(tm) HD Graphics";
CONST CHAR8 ROMDATA str_F12_Fs1_MZ_APU[] = "MZ APU with Radeon(tm) HD Graphics";
CONST CHAR8 ROMDATA str_F12_Fs1_MC_APU[] = "MC APU with Radeon(tm) HD Graphics";
CONST CHAR8 ROMDATA str_F12_Fs1_MF_Processor[] = "MF Processor";
CONST CHAR8 ROMDATA str_F12_Fs1_MG_Processor[] = "MG Processor";
CONST CHAR8 ROMDATA str_F12_Fs1_MF_DC_Processor[] = "MF Dual-Core Processor";
CONST CHAR8 ROMDATA str_F12_Fs1_MG_DC_Processor[] = "MG Dual-Core Processor";
CONST CHAR8 ROMDATA str_F12_Fs1_MF_TC_Processor[] = "MF Triple-Core Processor";
CONST CHAR8 ROMDATA str_F12_Fs1_MG_TC_Processor[] = "MG Triple-Core Processor";
CONST CHAR8 ROMDATA str_F12_Fs1_MF_QC_Processor[] = "MF Quad-Core Processor";
CONST CHAR8 ROMDATA str_F12_Fs1_MG_QC_Processor[] = "MG Quad-Core Processor";
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
CONST AMD_CPU_BRAND ROMDATA CpuF12LnBrandIdString1ArrayFs1[] =
{
// FS1
{1, 0, 1, LN_SOCKET_FS1, str_F12_Fs1_AMD_A4_35, sizeof (str_F12_Fs1_AMD_A4_35)},
{2, 0, 1, LN_SOCKET_FS1, str_F12_Fs1_AMD_A4_35, sizeof (str_F12_Fs1_AMD_A4_35)},
{1, 0, 2, LN_SOCKET_FS1, str_F12_Fs1_AMD_A4_34, sizeof (str_F12_Fs1_AMD_A4_34)},
{2, 0, 2, LN_SOCKET_FS1, str_F12_Fs1_AMD_A4_34, sizeof (str_F12_Fs1_AMD_A4_34)},
{1, 0, 3, LN_SOCKET_FS1, str_F12_Fs1_AMD_A4_33, sizeof (str_F12_Fs1_AMD_A4_33)},
{2, 0, 3, LN_SOCKET_FS1, str_F12_Fs1_AMD_A4_33, sizeof (str_F12_Fs1_AMD_A4_33)},
{1, 0, 4, LN_SOCKET_FS1, str_F12_Fs1_AMD_A4_32, sizeof (str_F12_Fs1_AMD_A4_32)},
{2, 0, 4, LN_SOCKET_FS1, str_F12_Fs1_AMD_A4_32, sizeof (str_F12_Fs1_AMD_A4_32)},
{1, 0, 5, LN_SOCKET_FS1, str_F12_Fs1_AMD_E2_30, sizeof (str_F12_Fs1_AMD_E2_30)},
{2, 0, 5, LN_SOCKET_FS1, str_F12_Fs1_AMD_E2_30, sizeof (str_F12_Fs1_AMD_E2_30)},
{1, 0, 6, LN_SOCKET_FS1, str_F12_Fs1_AMD_E2_20, sizeof (str_F12_Fs1_AMD_E2_20)},
{2, 0, 6, LN_SOCKET_FS1, str_F12_Fs1_AMD_E2_20, sizeof (str_F12_Fs1_AMD_E2_20)},
{1, 0, 7, LN_SOCKET_FS1, str_F12_Fs1_AMD_E2_10, sizeof (str_F12_Fs1_AMD_E2_10)},
{2, 0, 7, LN_SOCKET_FS1, str_F12_Fs1_AMD_E2_10, sizeof (str_F12_Fs1_AMD_E2_10)},
{3, 0, 1, LN_SOCKET_FS1, str_F12_Fs1_AMD_A8_35, sizeof (str_F12_Fs1_AMD_A8_35)},
{4, 0, 1, LN_SOCKET_FS1, str_F12_Fs1_AMD_A8_35, sizeof (str_F12_Fs1_AMD_A8_35)},
{3, 0, 2, LN_SOCKET_FS1, str_F12_Fs1_AMD_A8_34, sizeof (str_F12_Fs1_AMD_A8_34)},
{4, 0, 2, LN_SOCKET_FS1, str_F12_Fs1_AMD_A8_34, sizeof (str_F12_Fs1_AMD_A8_34)},
{3, 0, 3, LN_SOCKET_FS1, str_F12_Fs1_AMD_A6_34, sizeof (str_F12_Fs1_AMD_A6_34)},
{4, 0, 3, LN_SOCKET_FS1, str_F12_Fs1_AMD_A6_34, sizeof (str_F12_Fs1_AMD_A6_34)},
{3, 0, 4, LN_SOCKET_FS1, str_F12_Fs1_AMD_A6_33, sizeof (str_F12_Fs1_AMD_A6_33)},
{4, 0, 4, LN_SOCKET_FS1, str_F12_Fs1_AMD_A6_33, sizeof (str_F12_Fs1_AMD_A6_33)},
}; //Cores, page, index, socket, stringstart, stringlength
CONST AMD_CPU_BRAND ROMDATA CpuF12LnBrandIdString2ArrayFs1[] =
{
// FS1
{1, 0, 1, LN_SOCKET_FS1, str_F12_Fs1_M_APU, sizeof (str_F12_Fs1_M_APU)},
{2, 0, 1, LN_SOCKET_FS1, str_F12_Fs1_M_APU, sizeof (str_F12_Fs1_M_APU)},
{3, 0, 1, LN_SOCKET_FS1, str_F12_Fs1_M_APU, sizeof (str_F12_Fs1_M_APU)},
{4, 0, 1, LN_SOCKET_FS1, str_F12_Fs1_M_APU, sizeof (str_F12_Fs1_M_APU)},
{1, 0, 2, LN_SOCKET_FS1, str_F12_Fs1_MX_APU, sizeof (str_F12_Fs1_MX_APU)},
{2, 0, 2, LN_SOCKET_FS1, str_F12_Fs1_MX_APU, sizeof (str_F12_Fs1_MX_APU)},
{3, 0, 2, LN_SOCKET_FS1, str_F12_Fs1_MX_APU, sizeof (str_F12_Fs1_MX_APU)},
{4, 0, 2, LN_SOCKET_FS1, str_F12_Fs1_MX_APU, sizeof (str_F12_Fs1_MX_APU)},
{1, 0, 3, LN_SOCKET_FS1, str_F12_Fs1_ML_APU, sizeof (str_F12_Fs1_ML_APU)},
{2, 0, 3, LN_SOCKET_FS1, str_F12_Fs1_ML_APU, sizeof (str_F12_Fs1_ML_APU)},
{3, 0, 3, LN_SOCKET_FS1, str_F12_Fs1_ML_APU, sizeof (str_F12_Fs1_ML_APU)},
{4, 0, 3, LN_SOCKET_FS1, str_F12_Fs1_ML_APU, sizeof (str_F12_Fs1_ML_APU)},
{1, 0, 4, LN_SOCKET_FS1, str_F12_Fs1_MZ_APU, sizeof (str_F12_Fs1_MZ_APU)},
{2, 0, 4, LN_SOCKET_FS1, str_F12_Fs1_MZ_APU, sizeof (str_F12_Fs1_MZ_APU)},
{3, 0, 4, LN_SOCKET_FS1, str_F12_Fs1_MZ_APU, sizeof (str_F12_Fs1_MZ_APU)},
{4, 0, 4, LN_SOCKET_FS1, str_F12_Fs1_MZ_APU, sizeof (str_F12_Fs1_MZ_APU)},
{1, 0, 5, LN_SOCKET_FS1, str_F12_Fs1_MC_APU, sizeof (str_F12_Fs1_MC_APU)},
{2, 0, 5, LN_SOCKET_FS1, str_F12_Fs1_MC_APU, sizeof (str_F12_Fs1_MC_APU)},
{3, 0, 5, LN_SOCKET_FS1, str_F12_Fs1_MC_APU, sizeof (str_F12_Fs1_MC_APU)},
{4, 0, 5, LN_SOCKET_FS1, str_F12_Fs1_MC_APU, sizeof (str_F12_Fs1_MC_APU)},
{1, 0, 6, LN_SOCKET_FS1, str_F12_Fs1_MF_Processor, sizeof (str_F12_Fs1_MF_Processor)},
{1, 0, 7, LN_SOCKET_FS1, str_F12_Fs1_MG_Processor, sizeof (str_F12_Fs1_MG_Processor)},
{2, 0, 6, LN_SOCKET_FS1, str_F12_Fs1_MF_DC_Processor, sizeof (str_F12_Fs1_MF_DC_Processor)},
{2, 0, 7, LN_SOCKET_FS1, str_F12_Fs1_MG_DC_Processor, sizeof (str_F12_Fs1_MG_DC_Processor)},
{3, 0, 6, LN_SOCKET_FS1, str_F12_Fs1_MF_TC_Processor, sizeof (str_F12_Fs1_MF_TC_Processor)},
{3, 0, 7, LN_SOCKET_FS1, str_F12_Fs1_MG_TC_Processor, sizeof (str_F12_Fs1_MG_TC_Processor)},
{4, 0, 6, LN_SOCKET_FS1, str_F12_Fs1_MF_QC_Processor, sizeof (str_F12_Fs1_MF_QC_Processor)},
{4, 0, 7, LN_SOCKET_FS1, str_F12_Fs1_MG_QC_Processor, sizeof (str_F12_Fs1_MG_QC_Processor)},
}; //Cores, page, index, socket, stringstart, stringlength
CONST CPU_BRAND_TABLE ROMDATA F12LnBrandIdString1ArrayFs1 = {
(sizeof (CpuF12LnBrandIdString1ArrayFs1) / sizeof (AMD_CPU_BRAND)),
CpuF12LnBrandIdString1ArrayFs1
};
CONST CPU_BRAND_TABLE ROMDATA F12LnBrandIdString2ArrayFs1 = {
(sizeof (CpuF12LnBrandIdString2ArrayFs1) / sizeof (AMD_CPU_BRAND)),
CpuF12LnBrandIdString2ArrayFs1
};

130
src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12CacheDefaults.c
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@ -1,130 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_12 ROM Execution Cache Defaults
*
* Contains default values for ROM execution cache setup
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x12
* @e \$Revision: 50761 $ @e \$Date: 2011-04-14 06:16:02 +0800 (Thu, 14 Apr 2011) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuCacheInit.h"
#include "cpuFamilyTranslation.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_CPU_FAMILY_0X12_CPUF12CACHEDEFAULTS_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
GetF12CacheInfo (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **CacheInfoPtr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
#define BSP_STACK_SIZE 16384
#define CORE0_STACK_SIZE 16384
#define CORE1_STACK_SIZE 4096
#define MEM_TRAINING_BUFFER_SIZE 16384
#define VAR_MTRR_MASK 0x000000FFFFFFFFFFull
#define HEAP_BASE_MASK 0x000000FFFFFFFFFFull
#define SHARED_MEM_SIZE 0
CONST CACHE_INFO ROMDATA CpuF12CacheInfo =
{
BSP_STACK_SIZE,
CORE0_STACK_SIZE,
CORE1_STACK_SIZE,
MEM_TRAINING_BUFFER_SIZE,
SHARED_MEM_SIZE,
(UINT64) VAR_MTRR_MASK,
(UINT64) VAR_MTRR_MASK,
(UINT64) HEAP_BASE_MASK,
LimitedByL2Size
};
/*---------------------------------------------------------------------------------------*/
/**
* Returns the family specific properties of the cache, and its usage.
*
* @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[out] CacheInfoPtr Points to the cache info properties on exit.
* @param[out] NumberOfElements Will be one to indicate one entry.
* @param[in] StdHeader Header for library and services.
*
*/
VOID
GetF12CacheInfo (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **CacheInfoPtr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
*NumberOfElements = 1;
*CacheInfoPtr = &CpuF12CacheInfo;
}

352
src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12Dmi.c
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@ -1,352 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD DMI Record Creation API, and related functions.
*
* Contains code that produce the DMI related information.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU
* @e \$Revision: 49028 $ @e \$Date: 2011-03-16 09:20:07 +0800 (Wed, 16 Mar 2011) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "cpuRegisters.h"
#include "cpuLateInit.h"
#include "cpuF12PowerMgmt.h"
#include "cpuFamilyTranslation.h"
#include "cpuPstateTables.h"
#include "Filecode.h"
CODE_GROUP (G3_DXE)
RDATA_GROUP (G3_DXE)
#define FILECODE PROC_CPU_FAMILY_0X12_CPUF12DMI_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable;
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
DmiF12GetInfo (
IN OUT CPU_TYPE_INFO *CpuInfoPtr,
IN AMD_CONFIG_PARAMS *StdHeader
);
UINT8
DmiF12GetVoltage (
IN AMD_CONFIG_PARAMS *StdHeader
);
UINT16
DmiF12GetMaxSpeed (
IN AMD_CONFIG_PARAMS *StdHeader
);
UINT16
DmiF12GetExtClock (
IN AMD_CONFIG_PARAMS *StdHeader
);
VOID
DmiF12GetMemInfo (
IN OUT CPU_GET_MEM_INFO *CpuGetMemInfoPtr,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/* -----------------------------------------------------------------------------*/
/**
*
* DmiF12GetInfo
*
* Get CPU type information
*
* @param[in,out] CpuInfoPtr Pointer to CPU_TYPE_INFO struct.
* @param[in] StdHeader Standard Head Pointer
*
*/
VOID
DmiF12GetInfo (
IN OUT CPU_TYPE_INFO *CpuInfoPtr,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
CPUID_DATA CpuId;
LibAmdCpuidRead (AMD_CPUID_FMF, &CpuId, StdHeader);
CpuInfoPtr->ExtendedFamily = (UINT8) (CpuId.EAX_Reg >> 20) & 0xFF; // bit 27:20
CpuInfoPtr->ExtendedModel = (UINT8) (CpuId.EAX_Reg >> 16) & 0xF; // bit 19:16
CpuInfoPtr->BaseFamily = (UINT8) (CpuId.EAX_Reg >> 8) & 0xF; // bit 11:8
CpuInfoPtr->BaseModel = (UINT8) (CpuId.EAX_Reg >> 4) & 0xF; // bit 7:4
CpuInfoPtr->Stepping = (UINT8) (CpuId.EAX_Reg & 0xF); // bit 3:0
CpuInfoPtr->PackageType = (UINT8) (CpuId.EBX_Reg >> 28) & 0xF; // bit 31:28
CpuInfoPtr->BrandId.Pg = (UINT8) (CpuId.EBX_Reg >> 15) & 0x1; // bit 15
CpuInfoPtr->BrandId.String1 = (UINT8) (CpuId.EBX_Reg >> 11) & 0xF; // bit 14:11
CpuInfoPtr->BrandId.Model = (UINT8) (CpuId.EBX_Reg >> 4) & 0x7F; // bit 10:4
CpuInfoPtr->BrandId.String2 = (UINT8) (CpuId.EBX_Reg & 0xF); // bit 3:0
LibAmdCpuidRead (AMD_CPUID_ASIZE_PCCOUNT, &CpuId, StdHeader);
CpuInfoPtr->TotalCoreNumber = (UINT8) (CpuId.ECX_Reg & 0xFF); // bit 7:0
CpuInfoPtr->EnabledCoreNumber = (UINT8) (CpuId.ECX_Reg & 0xFF); // bit 7:0
switch (CpuInfoPtr->PackageType) {
case LN_SOCKET_FP1:
CpuInfoPtr->ProcUpgrade = P_UPGRADE_NONE;
break;
case LN_SOCKET_FS1:
CpuInfoPtr->ProcUpgrade = P_UPGRADE_FS1;
break;
case LN_SOCKET_FM1:
CpuInfoPtr->ProcUpgrade = P_UPGRADE_FM1;
break;
default:
CpuInfoPtr->ProcUpgrade = P_UPGRADE_UNKNOWN;
break;
}
}
/* -----------------------------------------------------------------------------*/
/**
*
* DmiF12GetVoltage
*
* Get the voltage value according to SMBIOS SPEC's requirement.
*
* @param[in] StdHeader Standard Head Pointer
*
* @retval Voltage - CPU Voltage.
*
*/
UINT8
DmiF12GetVoltage (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 MaxVid;
UINT8 Voltage;
UINT8 NumberBoostStates;
UINT64 MsrData;
PCI_ADDR TempAddr;
CPB_CTRL_REGISTER CpbCtrl;
// Voltage = 0x80 + (voltage at boot time * 10)
TempAddr.AddressValue = CPB_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, TempAddr, &CpbCtrl, StdHeader); // F4x15C
NumberBoostStates = (UINT8) CpbCtrl.NumBoostStates;
LibAmdMsrRead ((MSR_PSTATE_0 + NumberBoostStates), &MsrData, StdHeader);
MaxVid = (UINT8) (((PSTATE_MSR *)&MsrData)->CpuVid);
if ((MaxVid >= 0x7C) && (MaxVid <= 0x7F)) {
Voltage = 0;
} else {
Voltage = (UINT8) ((15500 - (125 * MaxVid) + 500) / 1000);
}
Voltage += 0x80;
return (Voltage);
}
/* -----------------------------------------------------------------------------*/
/**
*
* DmiF12GetMaxSpeed
*
* Get the Max Speed
*
* @param[in] StdHeader Standard Head Pointer
*
* @retval MaxSpeed - CPU Max Speed.
*
*/
UINT16
DmiF12GetMaxSpeed (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 NumBoostStates;
UINT32 P0Frequency;
UINT32 PciData;
PCI_ADDR PciAddress;
PSTATE_CPU_FAMILY_SERVICES *FamilyServices;
FamilyServices = NULL;
GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (const VOID **) &FamilyServices, StdHeader);
ASSERT (FamilyServices != NULL);
PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_4, 0x15C);
LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
NumBoostStates = (UINT8) ((PciData >> 2) & 7);
FamilyServices->GetPstateFrequency (FamilyServices, NumBoostStates, &P0Frequency, StdHeader);
return ((UINT16) P0Frequency);
}
/* -----------------------------------------------------------------------------*/
/**
*
* DmiF12GetExtClock
*
* Get the external clock Speed
*
* @param[in] StdHeader Standard Head Pointer
*
* @retval ExtClock - CPU external clock Speed.
*
*/
UINT16
DmiF12GetExtClock (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
return (EXTERNAL_CLOCK_100MHZ);
}
/* -----------------------------------------------------------------------------*/
/**
*
* DmiF12GetMemInfo
*
* Get memory information.
*
* @param[in,out] CpuGetMemInfoPtr Pointer to CPU_GET_MEM_INFO struct.
* @param[in] StdHeader Standard Head Pointer
*
*/
VOID
DmiF12GetMemInfo (
IN OUT CPU_GET_MEM_INFO *CpuGetMemInfoPtr,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
// Llano does NOT support ECC DIMM
CpuGetMemInfoPtr->EccCapable = FALSE;
// Partition Row Position - 0 is for dual channel memory
CpuGetMemInfoPtr->PartitionRowPosition = 0;
}
/*---------------------------------------------------------------------------------------
* Processor Family Table
*
* Note: 'x' means we don't care this field
* 047h = "E-Series"
* 048h = "A-Series"
* 002h = "Unknown"
*-------------------------------------------------------------------------------------*/
CONST DMI_BRAND_ENTRY ROMDATA Family12BrandList[] =
{
// Brand --> DMI ID translation table
// PackageType, PgOfBrandId, NumberOfCores, String1ofBrandId, ValueSetToDmiTable
{1, 0, 0, 1, 0x48},
{1, 0, 1, 1, 0x48},
{1, 0, 0, 2, 0x48},
{1, 0, 1, 2, 0x48},
{1, 0, 0, 3, 0x48},
{1, 0, 1, 3, 0x48},
{1, 0, 0, 4, 0x48},
{1, 0, 1, 4, 0x48},
{1, 0, 0, 5, 0x47},
{1, 0, 1, 5, 0x47},
{1, 0, 0, 6, 0x47},
{1, 0, 1, 6, 0x47},
{1, 0, 0, 7, 0x47},
{1, 0, 1, 7, 0x47},
{1, 0, 2, 1, 0x48},
{1, 0, 3, 1, 0x48},
{1, 0, 2, 2, 0x48},
{1, 0, 3, 2, 0x48},
{1, 0, 2, 3, 0x48},
{1, 0, 3, 3, 0x48},
{1, 0, 2, 4, 0x48},
{1, 0, 3, 4, 0x48},
{2, 0, 0, 1, 0x47},
{2, 0, 0, 4, 0x47},
{2, 0, 1, 1, 0x48},
{2, 0, 1, 2, 0x47},
{2, 0, 1, 5, 0x48},
{2, 0, 1, 6, 0x48},
{2, 0, 1, 7, 0x47},
{2, 0, 2, 1, 0x48},
{2, 0, 2, 4, 0x48},
{2, 0, 2, 5, 0x48},
{2, 0, 2, 6, 0x48},
{2, 0, 3, 1, 0x48},
{2, 0, 3, 2, 0x48},
{2, 0, 3, 5, 0x48},
{2, 0, 3, 6, 0x48},
{2, 0, 3, 7, 0x48},
{2, 0, 3, 8, 0x48},
{'x', 'x', 'x', 'x', P_FAMILY_UNKNOWN}
};
CONST PROC_FAMILY_TABLE ROMDATA ProcFamily12DmiTable =
{
AMD_FAMILY_12, // ID for Family 12h
&DmiF12GetInfo, // Transfer vectors for family
&DmiGetT4ProcFamilyFromBrandId, // Get type 4 processor family information from CPUID_8000_0001_EBX[BrandId]
&DmiF12GetVoltage, // specific routines (above)
&DmiF12GetMaxSpeed,
&DmiF12GetExtClock,
&DmiF12GetMemInfo, // Get memory information
(sizeof (Family12BrandList) / sizeof (Family12BrandList[0])), // Number of entries in following table
&Family12BrandList[0]
};
/*---------------------------------------------------------------------------------------
* L O C A L F U N C T I O N S
*---------------------------------------------------------------------------------------
*/

115
src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12EarlyNbPstateInit.c
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@ -1,115 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_12 Early NB P-state Initialization
*
* Sets some NB P-state related fields at AmdInitEarly.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F12
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "cpuFamilyTranslation.h"
#include "cpuF12PowerMgmt.h"
#include "cpuF12EarlyNbPstateInit.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_CPU_FAMILY_0X12_CPUF12EARLYNBPSTATEINIT_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
* Family 12h core 0 entry point for performing early NB P-state initialization.
*
* Set up D18F6x94[CpuPstateThrEn, CpuPstateThr] according to the BKDG.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] CpuEarlyParams Service parameters
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
F12NbPstateEarlyInit (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 CpbControl;
UINT32 LocalPciRegister;
PCI_ADDR PciAddress;
PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader);
PciAddress.AddressValue = NB_PSTATE_CFG_HIGH_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
if (((CPB_CTRL_REGISTER *) &CpbControl)->NumBoostStates == 0) {
((NB_PSTATE_CFG_HIGH_REGISTER *) &LocalPciRegister)->CpuPstateThr = 1;
} else {
((NB_PSTATE_CFG_HIGH_REGISTER *) &LocalPciRegister)->CpuPstateThr = 2;
}
((NB_PSTATE_CFG_HIGH_REGISTER *) &LocalPciRegister)->CpuPstateThrEn = 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
}

76
src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12EarlyNbPstateInit.h
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@ -1,76 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_12 Early NB P-state Initialization related functions and structures
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F12
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _CPU_F12_EARLY_NB_PSTATE_INIT_H_
#define _CPU_F12_EARLY_NB_PSTATE_INIT_H_
/*---------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*---------------------------------------------------------------------------------------
*/
VOID
F12NbPstateEarlyInit (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
);
#endif // _CPU_F12_EARLY_NB_PSTATE_INIT_H_

214
src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12MsrTables.c
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@ -1,214 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_12 MSR tables with values as defined in BKDG
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "cpuF12PowerMgmt.h"
#include "Table.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_CPU_FAMILY_0X12_CPUF12MSRTABLES_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F12MsrRegisters[] =
{
// M S R T a b l e s
// ----------------------
// MSR_TOM2 (0xC001001D)
// bits[63:0] - TOP_MEM2 = 0
{
MsrRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MSR_TOM2, // MSR Address
0x0000000000000000ull, // OR Mask
0xFFFFFFFFFFFFFFFFull, // NAND Mask
}}
},
// MSR_SYS_CFG (0xC0010010)
// bit[21] - MtrrTom2En = 1
{
MsrRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MSR_SYS_CFG, // MSR Address
(UINT64) (1 << 21), // OR Mask
(UINT64) (1 << 21), // NAND Mask
}}
},
// MSR_HWCR (0xC0010015)
// bit[4] - INVD_WBINVD = 1
{
MsrRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MSR_HWCR, // MSR Address
0x0000000000000010ull, // OR Mask
0x0000000000000010ull, // NAND Mask
}}
},
// MSR_CSTATE_ADDRESS (0xC0010073)
// bit[15:0] - CstateAddr = 0
{
MsrRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MSR_CSTATE_ADDRESS, // MSR Address
0x0000000000000000ull, // OR Mask
0x000000000000FFFFull, // NAND Mask
}}
},
// MSR_BU_CFG2 (0xC001102A)
// bit[50] - RdMmExtCfgDwDis = 1
// bit[56] - L2ClkGatingEn = 1
// bits[58:57] - L2HystCnt = 3
{
MsrRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MSR_BU_CFG2, // MSR Address
0x0704000000000000ull, // OR Mask
0x0704000000000000ull, // NAND Mask
}}
},
// MSR_OSVW_ID_Length (0xC0010140)
// bit[15:0] = 4
{
MsrRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MSR_OSVW_ID_Length, // MSR Address
0x0000000000000004ull, // OR Mask
0x000000000000FFFFull, // NAND Mask
}}
},
// MSR_OSVW_Status (0xC0010141)
// bits[2:0] = 0 reserved, must be zero
// bit[3] = 1 for Erratum #383
{
MsrRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_LN_Ax // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MSR_OSVW_Status, // MSR Address
0x0000000000000008ull, // OR Mask
0x000000000000000Full, // NAND Mask
}}
},
// This MSR should be set after the code that most errata would be applied in
// MSR_MC0_CTL (0x00000400)
// bits[63:0] = 0xFFFFFFFFFFFFFFFF
{
MsrRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MSR_MC0_CTL, // MSR Address
0xFFFFFFFFFFFFFFFFull, // OR Mask
0xFFFFFFFFFFFFFFFFull, // NAND Mask
}}
}
};
CONST REGISTER_TABLE ROMDATA F12MsrRegisterTable = {
AllCores,
(sizeof (F12MsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
(TABLE_ENTRY_FIELDS *) &F12MsrRegisters,
};

959
src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PciTables.c
View File

@ -1,959 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_12 PCI tables with values as defined in BKDG
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/FAMILY/0x12
* @e \$Revision: 45812 $ @e \$Date: 2011-01-22 07:45:25 +0800 (Sat, 22 Jan 2011) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "Table.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_CPU_FAMILY_0X12_CPUF12PCITABLES_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
// P C I T a b l e s
// ----------------------
STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F12PciRegisters[] =
{
// Function 0 - Link Config
// D18F0x68 - Link Transaction Control
// bit[11] RespPassPW = 1
// bits[19:17] for 8bit APIC config
// bits[22:21] DsNpReqLmt = 1
{
PciRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68), // Address
0x002E0800ull, // regData
0x006E0800ull, // regMask
}}
},
// Function 3 - Misc. Control
// D18F3x40 - MCA NB Control
// bit[8] MstrAbortEn = 1
{
PciRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x40), // Address
0x00000100ull, // regData
0x00000100ull, // regMask
}}
},
// D18F3x44 - MCA NB Configuration
// bit[27] NbMcaToMstCpuEn = 1
// bit[25] DisPciCfgCpuErrRsp = 1
// bit[21] SyncOnAnyErrEn = 1
// bit[20] SyncOnWDTEn = 1
// bits[13:12] WDTBaseSel = 0
// bits[11:9] WDTCntSel[2:0] = 0
// bit[6] CpuErrDis = 1
{
PciRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x44), // Address
0x0A300040ull, // regData
0x0A303E40ull, // regMask
}}
},
// D18F3x6C - Upstream Data Buffer Count
// bits[3:0] UpLoPreqDBC = 0x0E
// bits[7:4] UpLoNpreqDBC = 1
// bits[11:8] UpLoRespDBC = 1
// bits[19:16] UpHiPreqDBC = 0
// bits[23:20] UpHiNpreqDBC = 0
{
PciRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO(0, 0, 24, FUNC_3, 0x6C), // Address
0x0000011Eull, // regData
0x00FF0FFFull, // regMask
}}
},
// D18F3x74 - Upstream Command Buffer Count
// bits[3:0] UpLoPreqCBC = 7
// bits[7:4] UpLoNpreqCBC = 9
// bits[11:8] UpLoRespCBC = 8
// bits[19:16] UpHiPreqCBC = 0
// bits[23:20] UpHiNpreqCBC = 0
{
PciRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO(0, 0, 24, FUNC_3, 0x74), // Address
0x00000897ull, // regData
0x00FF0FFFull, // regMask
}}
},
// D18F3x7C - In-Flight Queue Buffer Allocation
// bits[5:0] CpuBC = 1
// bits[13:8] LoPriPBC = 1
// bits[21:16] LoPriNPBC = 1
// bits[29:24] FreePoolBC = 0x19
{
PciRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address
0x19010101ull, // regData
0x3F3F3F3Full, // regMask
}}
},
// D18F3x84 - ACPI Power State Control High
// bit[18] Smaf6DramMemClkTri = 1
// bit[17] Smaf6DramSr = 1
// bit[2] Smaf4DramMemClkTri = 1
// bit[1] Smaf4DramSr = 1
{
PciRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x84), // Address
0x00060006ull, // regData
0x00060006ull, // regMask
}}
},
// D18F3x8C - NB Configuration High
// bit[26] EnConvertToNonIsoc = 1
{
PciRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x8C), // Address
0x04000000ull, // regData
0x04000000ull, // regMask
}}
},
// D18F3xA0 - Power Control Miscellaneous
// bit[9] SviHighFreqSel = 1
{
PciRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0), // Address
0x00000200ull, // regData
0x00000200ull, // regMask
}}
},
// D18F3xA4 - Reported Temperature Control
// bits[12:8] PerStepTimeDn = 0xF
// bit [7] TmpSlewDnEn = 1
// bits[6:5] TmpMaxDiffUp = 0x3
// bits[4:0] PerStepTimeUp = 0xF
{
PciRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA4), // Address
0x00000FEFull, // regData
0x00001FFFull, // regMask
}}
},
// D18F3xD4 - Clock Power Timing Control 0
// bits[11:8] ClkRampHystSel = 0xF
// bits[15:12] OnionOutHyst = 0x4
// bit[17] ClockGatingEnDram = 1
{
PciRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0xD4), // Address
0x00024F00ull, // regData
0x0002FF00ull, // regMask
}}
},
// D18F3xD4 - Clock Power Timing Control 0
// bit[7] ShallowHaltDidAllow = 1
{
PciRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_LN_Bx // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0xD4), // Address
0x00000080ull, // regData
0x00000080ull, // regMask
}}
},
// D18F3xDC - Clock Power Timing Control 2
// bits[29:27] NbClockGateHyst = 3
// bit[30] NbClockGateEn = 0 - erratum #596
// bit[31] CnbCifClockGateEn = 1
{
PciRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC), // Address
0x98000000ull, // regData
0xF8000000ull, // regMask
}}
},
// D18F3x17C - In-Flight Queue Extended Buffer Allocation
// bits[5:0] HiPriPBC = 0
// bits[13:8] HiPriNPBC = 0
{
PciRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x17C), // Address
0x00000000ull, // regData
0x00003F3Full, // regMask
}}
},
// D18F3x180 - Extended NB MCA Configuration
// bit[2] WDTCntSel[3] = 0
// bit[5] DisPciCfgCpuMstAbtRsp = 1
// bit[21] SyncFloodOnCpuLeakErr = 1
{
PciRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x180), // Address
0x00200020ull, // regData
0x00200024ull, // regMask
}}
},
// D18F3x188 - NB Extended Configuration
// bit[21] EnCpuSerWrBehindIoRd = 0
// bit[23] EnCpuSerRdBehindIoRd = 0
// bits[27:24] FeArbCpuWeightOverLoPrio = 0x0B
// bits[31:28] FeArbCpuWeightOverHiPrio = 1
{
PciRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x188), // Address
0x1B000000ull, // regData
0xFFA00000ull, // regMask
}}
},
// Function 4 - Extended Misc. Control
// D18F4x104 - TDP Lock Accumulator
// bits[1:0] TdpLockDivVal = 1
// bits[13:2] TdpLockDivRate = 0x190
// bits[16:15] TdpLockDivValCpu = 1
// bits[28:17] TdpLockDivRateCpu = 0x190
{
PciRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_4, 0x104), // Address
0x03208641ull, // regData
0x1FFFBFFFull, // regMask
}}
},
// D18F4x118 - C-state Control 1
// bits[10:8] CstAct1 = 0
// bits[2:0] CstAct0 = 0
{
PciRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_4, 0x118), // Address
0x00000000ull, // regData
0x00000707ull, // regMask
}}
},
// D18F4x120 - C-state Policy Control 1
// bit[31] CstateMsgDis = 1
{
PciRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_4, 0x120), // Address
0x80000000ull, // regData
0x80000000ull, // regMask
}}
},
// D18F4x124 - C-state Monitor Control 1
// bit[15] TimerTickIntvlScale = 1
// bit[16] TrackTimerTickInterEn = 1
// bit[17] IntMonCC6En = 1
// bits[21:18] IntMonCC6Lmt = 4
// bit[22] IntMonPkgC6En = 0
// bits[26:23] IntMonPkgC6Lmt = 0xA
{
PciRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_4, 0x124), // Address
0x05138000ull, // regData
0x07FF8000ull, // regMask
}}
},
// D18F4x134 - C-state Monitor Control 3
// bits[3:0] IntRatePkgC6MaxDepth = 0
// bits[7:4] IntRatePkgC6Threshold = 0
// bits[10:8] IntRatePkgC6BurstLen = 1
// bits[15:11] IntRatePkgC6DecrRate = 0x0A
// bits[19:16] IntRateCC6MaxDepth = 5
// bits[23:20] IntRateCC6Threshold = 4
// bits[26:24] IntRateCC6BurstLen = 5
// bits[31:27] IntRateCC6DecrRate = 0x18
{
PciRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_4, 0x134), // Address
0xC5455100ull, // regData
0xFFFFFFFFull, // regMask
}}
},
// D18F4x13C - SMAF Code DID 1
// bits[4:0] Smaf4Did = 0x0F
// bits[20:16] Smaf6Did = 0x0F
{
PciRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_4, 0x13C), // Address
0x000F000Full, // regData
0x001F001Full, // regMask
}}
},
// D18F4x14C - LPMV Scalar 2
// bits[25:24] ApmCstExtPol = 1
{
PciRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_4, 0x14C), // Address
0x01000000ull, // regData
0x03000000ull, // regMask
}}
},
// D18F4x14C - LPMV Scalar 2
// bit[26] CstatePowerSel = 1
{
PciRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_LN_Bx // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_4, 0x14C), // Address
0x04000000ull, // regData
0x04000000ull, // regMask
}}
},
// D18F4x15C - Core Performance Boost Control
// bits[1:0] BoostSrc = 0
// bit[29] BoostEnAllCores = 1
{
PciRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_4, 0x15C), // Address
0x20000000ull, // regData
0x20000003ull, // regMask
}}
},
// D18F4x15C - Core Performance Boost Control
// bit[28] IgnoreBoostThresh = 1
{
PciRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_LN_Bx // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_4, 0x15C), // Address
0x10000000ull, // regData
0x10000000ull, // regMask
}}
},
// D18F4x1A4 - C-state Monitor Mask
// bits[7:0] IntRateMonMask = 0xFC
// bits[15:8] TimerTickMonMask = 0xFF
// bits[23:16] NonC0MonMask = 0xFF
// bits[31:24] C0MonMask = 0xFF
{
PciRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_4, 0x1A4), // Address
0xFFFFFFFCull, // regData
0xFFFFFFFFull, // regMask
}}
},
// D18F4x1A8 - CPU State Power Management Dynamic Control 0
// bits[4:0] SingleHaltCpuDid = 8
// bits[9:5] AllHaltCpuDid = 0x0F
// bit[15] CpuProbEn = 0
// bits[22:20] PServiceTmr = 1
// bit[23] PServiceTmrEn = 1
{
PciRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_4, 0x1A8), // Address
0x009001E8ull, // regData
0x00F083FFull, // regMask
}}
},
// D18F4x1AC - CPU State Power Management Dynamic Control 1
// bits[9:5] C6Did = 0x0F
{
PciRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_4, 0x1AC), // Address
0x000001E0ull, // regData
0x000003E0ull, // regMask
}}
},
// D18F6x50 - Configuration Register Access Control
// bit[1] CfgAccAddrMode = 0
{
PciRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x50), // Address
0x00000000ull, // regData
0x00000002ull, // regMask
}}
},
// D18F6x54 - Dram Arbitration Control FEQ Collision
// bits[7:0] FeqLoPrio = 0x20
// bits[15:8] FeqMedPrio = 0x10
// bits[23:16] FeqHiPrio = 8
// bit[31] PpMode = 0
{
PciRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x54), // Address
0x00081020ull, // regData
0x80FFFFFFull, // regMask
}}
},
// D18F6x154 - Dram Arbitration Control FEQ Collision
// bits[7:0] FeqLoPrio = 0x20
// bits[15:8] FeqMedPrio = 0x10
// bits[23:16] FeqHiPrio = 8
// bit[31] PpMode = 0
{
PciRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x154), // Address
0x00081020ull, // regData
0x80FFFFFFull, // regMask
}}
},
// D18F6x58 - Dram Arbitration Control Display Collision
// bits[7:0] DispLoPrio = 0x40
// bits[15:8] DispMedPrio = 0x20
// bits[23:16] DispHiPrio = 0x10
// bits[31:24] DispUrgPrio = 0
{
PciRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x58), // Address
0x00102040ull, // regData
0xFFFFFFFFull, // regMask
}}
},
// D18F6x158 - Dram Arbitration Control Display Collision
// bits[7:0] DispLoPrio = 0x40
// bits[15:8] DispMedPrio = 0x20
// bits[23:16] DispHiPrio = 0x10
// bits[31:24] DispUrgPrio = 0
{
PciRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x158), // Address
0x00102040ull, // regData
0xFFFFFFFFull, // regMask
}}
},
// D18F6x5C - Dram Arbitration Control FEQ Write Protect
// bits[7:0] FeqLoPrio = 0x20
// bits[15:8] FeqMedPrio = 0x10
// bits[23:16] FeqHiPrio = 8
// bit[31] PpMode = 0
{
PciRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x5C), // Address
0x00081020ull, // regData
0x80FFFFFFull, // regMask
}}
},
// D18F6x15C - Dram Arbitration Control FEQ Write Protect
// bits[7:0] FeqLoPrio = 0x20
// bits[15:8] FeqMedPrio = 0x10
// bits[23:16] FeqHiPrio = 8
// bit[31] PpMode = 0
{
PciRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x15C), // Address
0x00081020ull, // regData
0x80FFFFFFull, // regMask
}}
},
// D18F6x60 - Dram Arbitration Control Diplay Write Protect
// bits[7:0] DispLoPri = 0x20
// bits[15:8] DispMedPrio = 0x10
// bits[23:16] DispHiPrio = 8
// bits[31:24] DispUrgPrio = 0
{
PciRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x60), // Address
0x00081020ull, // regData
0xFFFFFFFFull, // regMask
}}
},
// D18F6x160 - Dram Arbitration Control Diplay Write Protect
// bits[7:0] DispLoPri = 0x20
// bits[15:8] DispMedPrio = 0x10
// bits[23:16] DispHiPrio = 8
// bits[31:24] DispUrgPrio = 0
{
PciRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x160), // Address
0x00081020ull, // regData
0xFFFFFFFFull, // regMask
}}
},
// D18F6x64 - Dram Arbitration Control FEQ Read Protect
// bits[7:0] FeqLoPrio = 0x10
// bits[15:8] FeqMedPrio = 8
// bits[23:16] FeqHiPrio = 4
// bit[31] PpMode = 0
{
PciRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x64), // Address
0x00040810ull, // regData
0x80FFFFFFull, // regMask
}}
},
// D18F6x164 - Dram Arbitration Control FEQ Read Protect
// bits[7:0] FeqLoPrio = 0x10
// bits[15:8] FeqMedPrio = 8
// bits[23:16] FeqHiPrio = 4
// bit[31] PpMode = 0
{
PciRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x164), // Address
0x00040810ull, // regData
0x80FFFFFFull, // regMask
}}
},
// D18F6x68 - Dram Arbitration Control Display Read Protect
// bits[7:0] DispLoPrio = 0x10
// bits[15:8] DispMedPrio = 8
// bits[23:16] DispHiPrio = 4
// bits[31:24] DispUrgPrio = 0
{
PciRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x68), // Address
0x00040810ull, // regData
0xFFFFFFFFull, // regMask
}}
},
// D18F6x168 - Dram Arbitration Control Display Read Protect
// bits[7:0] DispLoPrio = 0x10
// bits[15:8] DispMedPrio = 8
// bits[23:16] DispHiPrio = 4
// bits[31:24] DispUrgPrio = 0
{
PciRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x168), // Address
0x00040810ull, // regData
0xFFFFFFFFull, // regMask
}}
},
// D18F6x6C - Dram Arbitration Control FEQ Fairness Timer
// bits[7:0] FeqLoPrio = 0x80
// bits[15:8] FeqMedPrio = 0x40
// bits[23:16] FeqHiPrio = 0x20
{
PciRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x6C), // Address
0x00204080ull, // regData
0x00FFFFFFull, // regMask
}}
},
// D18F6x16C - Dram Arbitration Control FEQ Fairness Timer
// bits[7:0] FeqLoPrio = 0x80
// bits[15:8] FeqMedPrio = 0x40
// bits[23:16] FeqHiPrio = 0x20
{
PciRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x16C), // Address
0x00204080ull, // regData
0x00FFFFFFull, // regMask
}}
},
// D18F6x70 - Dram Arbitration Control Display Fairness Timer
// bits[7:0] DispLoPrio = 0x80
// bits[15:8] DispMedPrio = 0x40
// bits[23:16] DispHiPrio = 0x20
// bits[31:24] DispUrPrio = 0
{
PciRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x70), // Address
0x00204080ull, // regData
0xFFFFFFFFull, // regMask
}}
},
// D18F6x170 - Dram Arbitration Control Display Fairness Timer
// bits[7:0] DispLoPrio = 0x80
// bits[15:8] DispMedPrio = 0x40
// bits[23:16] DispHiPrio = 0x20
// bits[31:24] DispUrPrio = 0
{
PciRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x170), // Address
0x00204080ull, // regData
0xFFFFFFFFull, // regMask
}}
},
// D18F6x78 - Dram Prioritization and Arbitration Control
// bits[1:0] DispDbePrioEn = 3
// bit[2] FeqDbePrioEn = 1
// bit[3] DispArbCtrl = 0
// bits[5:4] GlcEosDet = 3
// bit[6] GlcEosDetDis = 0
{
PciRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x78), // Address
0x00000037ull, // regData
0x0000007Full, // regMask
}}
},
// D18F6x90 - NB P-state Config Low
// bit[30] NbPsCtrlDis = 1
// bit[29] NbPsForceSel = 0
// bit[28] NbPsForceReq = 1
{
PciRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x90), // Address
0x50000000ull, // regData
0x70000000ull, // regMask
}}
},
// D18F6x94 - NB P-state Config High
// bit[4] NbPs1NoTransOnDma = 0
// bits[25:23] NbPsC0Timer = 4
{
PciRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x94), // Address
0x02000000ull, // regData
0x03800010ull, // regMask
}}
},
// D18F6x9C - NCLK Reduction Control
// bits[6:0] NclkRedDiv = 0x78
// bit[7] NclkRedSelfRefrAlways = 1
{
PciRegister,
{
AMD_FAMILY_12, // CpuFamily
AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x9C), // Address
0x000000F8ull, // regData
0x000000FFull, // regMask
}}
}
};
CONST REGISTER_TABLE ROMDATA F12PciRegisterTable = {
PrimaryCores,
(sizeof (F12PciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
F12PciRegisters,
};

104
src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PerCorePciTables.c
View File

@ -1,104 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_12 Per Core PCI tables with values as defined in BKDG
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/FAMILY/0x12
* @e \$Revision: 36764 $ @e \$Date: 2010-08-25 22:51:27 +0800 (Wed, 25 Aug 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "Table.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_CPU_FAMILY_0X12_CPUF12PERCOREPCITABLES_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
// Per Core P C I T a b l e s
// ----------------------
STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F12PerCorePciRegisters[] =
{
// D18F3x1CC - IBS Control
// bits[3:0] LvtOffset = 0
// bit[8] LvtOffsetVal = 1
{
PciRegister,
{
(UINT64) AMD_FAMILY_12, // CpuFamily
(UINT64) AMD_F12_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1CC), // Address
0x00000100ull, // regData
0x0000010Full, // regMask
}}
}
};
CONST REGISTER_TABLE ROMDATA F12PerCorePciRegisterTable = {
AllCores,
(sizeof (F12PerCorePciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
F12PerCorePciRegisters,
};

364
src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12PowerCheck.c
View File

@ -1,364 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_12 P-State power check
*
* Performs the "Processor-Systemboard Power Delivery Compatibility Check" as
* described in the BKDG.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F12
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "cpuF12PowerMgmt.h"
#include "cpuRegisters.h"
#include "cpuApicUtilities.h"
#include "cpuServices.h"
#include "GeneralServices.h"
#include "cpuEarlyInit.h"
#include "cpuFamilyTranslation.h"
#include "cpuF12PowerCheck.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_CPU_FAMILY_0X12_CPUF12POWERCHECK_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
STATIC
F12PmPwrCheckCore (
IN VOID *ErrorData,
IN AMD_CONFIG_PARAMS *StdHeader
);
VOID
STATIC
F12PmPwrChkCopyPstate (
IN UINT8 Dest,
IN UINT8 Src,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
* Family 12h core 0 entry point for performing the family 12h Processor-
* Systemboard Power Delivery Check.
*
* The steps are as follows:
* 1. Starting with P0, loop through all P-states until a passing state is
* found. A passing state is one in which the current required by the
* CPU is less than the maximum amount of current that the system can
* provide to the CPU. If P0 is under the limit, no further action is
* necessary.
* 2. If at least one P-State is under the limit & at least one P-State is
* over the limit, the BIOS must:
* a. Clear both D18F4x15C[BoostSrc] and D18F4x15C[NumBoostStates] to 0.
* b. If the processor's current P-State is disabled by the power check,
* then the BIOS must request a transition to an enabled P-state
* using MSRC001_0062[PstateCmd] and wait for MSRC001_0063[CurPstate]
* to reflect the new value.
* c. Copy the contents of the enabled P-state MSRs to the highest
* performance P-state locations.
* d. Request a P-state transition to the P-state MSR containing the
* COF/VID values currently applied.
* e. Adjust the following P-state parameters affected by the P-state
* MSR copy by subtracting the number of P-states that are disabled
* by the power check.
* 1. D18F3x64[HtcPstateLimit]
* 2. D18F3xDC[PstateMaxVal]
* 3. If all P-States are over the limit, the BIOS must:
* a. Clear both D18F4x15C[BoostSrc] and D18F4x15C[NumBoostStates] to 0.
* b. If the processor's current P-State is != D18F3xDC[PstateMaxVal], then
* write D18F3xDC[PstateMaxVal] to MSRC001_0062[PstateCmd] and wait for
* MSRC001_0063[CurPstate] to reflect the new value.
* c. If D18F3xDC[PstateMaxVal]!= 000b, copy the contents of the P-state
* MSR pointed to by D18F3xDC[PstateMaxVal] to MSRC001_0064 and set
* MSRC001_0064[PstateEn]
* d. Write 000b to MSRC001_0062[PstateCmd] and wait for MSRC001_0063
* [CurPstate] to reflect the new value.
* e. Adjust the following P-state parameters to zero:
* 1. D18F3x64[HtcPstateLimit]
* 2. D18F3xDC[PstateMaxVal]
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] CpuEarlyParams Service parameters.
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
F12PmPwrCheck (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 DisPsNum;
UINT8 PsMaxVal;
UINT8 Pstate;
UINT32 ProcIddMax;
UINT32 LocalPciRegister;
UINT32 Socket;
UINT32 Module;
UINT32 Core;
UINT32 PstateLimit;
PCI_ADDR PciAddress;
UINT64 LocalMsrRegister;
AP_TASK TaskPtr;
AGESA_STATUS IgnoredSts;
PWRCHK_ERROR_DATA ErrorData;
// get the socket number
IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
ErrorData.SocketNumber = (UINT8) Socket;
ASSERT (Core == 0);
// get the Max P-state value
for (PsMaxVal = NM_PS_REG - 1; PsMaxVal != 0; --PsMaxVal) {
LibAmdMsrRead (PS_REG_BASE + PsMaxVal, &LocalMsrRegister, StdHeader);
if (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) {
break;
}
}
ErrorData.HwPstateNumber = (UINT8) (PsMaxVal + 1);
DisPsNum = 0;
for (Pstate = 0; Pstate < ErrorData.HwPstateNumber; Pstate++) {
if (FamilySpecificServices->GetProcIddMax (FamilySpecificServices, Pstate, &ProcIddMax, StdHeader)) {
if (ProcIddMax > CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].CurrentLimit) {
// Add to event log the Pstate that exceeded the current limit
PutEventLog (AGESA_WARNING,
CPU_EVENT_PM_PSTATE_OVERCURRENT,
Socket, Pstate, 0, 0, StdHeader);
DisPsNum++;
} else {
break;
}
}
}
// If all P-state registers are disabled, move P[PsMaxVal] to P0
// and transition to P0, then wait for CurPstate = 0
ErrorData.AllowablePstateNumber = ((PsMaxVal + 1) - DisPsNum);
// We only need to log this event on the BSC
if (ErrorData.AllowablePstateNumber == 0) {
PutEventLog (AGESA_FATAL,
CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT,
Socket, 0, 0, 0, StdHeader);
}
if (DisPsNum != 0) {
// Clear both D18F4x15C[BoostSrc] and D18F4x15C[NumBoostStates] to 0
PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
((CPB_CTRL_REGISTER *) &LocalPciRegister)->BoostSrc = 0;
((CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates = 0;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
TaskPtr.FuncAddress.PfApTaskI = F12PmPwrCheckCore;
TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (PWRCHK_ERROR_DATA);
TaskPtr.DataTransfer.DataPtr = &ErrorData;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.ExeFlags = WAIT_FOR_CORE;
ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParams);
// Final Step
// D18F3x64[HtPstatelimit] -= disPsNum
// D18F3xDC[PstateMaxVal]-= disPsNum
PciAddress.AddressValue = HTC_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // D18F3x64
PstateLimit = ((HTC_REGISTER *) &LocalPciRegister)->HtcPstateLimit;
if (PstateLimit > DisPsNum) {
PstateLimit -= DisPsNum;
} else {
PstateLimit = 0;
}
((HTC_REGISTER *) &LocalPciRegister)->HtcPstateLimit = PstateLimit;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // D18F3x64
PciAddress.AddressValue = CPTC2_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // D18F3xDC
PstateLimit = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->PstateMaxVal;
if (PstateLimit > DisPsNum) {
PstateLimit -= DisPsNum;
} else {
PstateLimit = 0;
}
((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->PstateMaxVal = PstateLimit;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // D18F3xDC
}
}
/*---------------------------------------------------------------------------------------*/
/**
* Core-level error handler called if any p-states were determined to be out
* of range for the mother board.
*
* This function implements steps 2b-d and 3b-d on each core.
*
* @param[in] ErrorData Details about the error condition.
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
STATIC
F12PmPwrCheckCore (
IN VOID *ErrorData,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 i;
UINT8 PsMaxVal;
UINT8 DisPsNum;
UINT8 CurrentPs;
UINT64 LocalMsrRegister;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **) &FamilySpecificServices, StdHeader);
PsMaxVal = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber - 1);
DisPsNum = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber -
((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber);
LibAmdMsrRead (MSR_PSTATE_STS, &LocalMsrRegister, StdHeader);
CurrentPs = (UINT8) (((PSTATE_STS_MSR *) &LocalMsrRegister)->CurPstate);
if (((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber == 0) {
// Step 1
// Transition to Pstate Max if not there already
if (CurrentPs != PsMaxVal) {
FamilySpecificServices->TransitionPstate (FamilySpecificServices, PsMaxVal, (BOOLEAN) TRUE, StdHeader);
}
// Step 2
// If Pstate Max is not P0, copy Pstate max contents to P0 and switch
// to P0.
if (PsMaxVal != 0) {
F12PmPwrChkCopyPstate (0, PsMaxVal, StdHeader);
FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 0, (BOOLEAN) TRUE, StdHeader);
}
} else {
// move remaining P-state register(s) up
// Step 1
// Transition to a valid Pstate if current Pstate has been disabled
if (CurrentPs < DisPsNum) {
FamilySpecificServices->TransitionPstate (FamilySpecificServices, DisPsNum, (BOOLEAN) TRUE, StdHeader);
CurrentPs = DisPsNum;
}
// Step 2
// Move enabled Pstates up and disable the remainder
for (i = 0; (i + DisPsNum) <= PsMaxVal; ++i) {
F12PmPwrChkCopyPstate (i, (i + DisPsNum), StdHeader);
}
// Step 3
// Transition to current COF/VID at shifted location
CurrentPs = (CurrentPs - DisPsNum);
FamilySpecificServices->TransitionPstate (FamilySpecificServices, CurrentPs, (BOOLEAN) TRUE, StdHeader);
}
i = ((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber;
if (i == 0) {
i++;
}
while (i <= PsMaxVal) {
FamilySpecificServices->DisablePstate (FamilySpecificServices, i, StdHeader);
i++;
}
}
/*---------------------------------------------------------------------------------------*/
/**
* Copies the contents of one P-State MSR to another.
*
* @param[in] Dest Destination p-state number
* @param[in] Src Source p-state number
* @param[in] StdHeader Config handle for library and services
*
*/
VOID
STATIC
F12PmPwrChkCopyPstate (
IN UINT8 Dest,
IN UINT8 Src,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 LocalMsrRegister;
LibAmdMsrRead ((UINT32) (PS_REG_BASE + Src), &LocalMsrRegister, StdHeader);
LibAmdMsrWrite ((UINT32) (PS_REG_BASE + Dest), &LocalMsrRegister, StdHeader);
}

81
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@ -1,81 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_12 Power related functions and structures
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F12
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _CPU_F12_POWER_CHECK_H_
#define _CPU_F12_POWER_CHECK_H_
/*---------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
/// Power Check Error Data
typedef struct {
UINT8 SocketNumber; ///< Socket Number
UINT8 HwPstateNumber; ///< Hardware P-state Number
UINT8 AllowablePstateNumber; ///< Allowable P-state Number
} PWRCHK_ERROR_DATA;
/*---------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*---------------------------------------------------------------------------------------
*/
VOID
F12PmPwrCheck (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
);
#endif // _CPU_F12_POWER_CHECK_H_

511
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@ -1,511 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_12 Power Management related stuff
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F12
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _CPUF12POWERMGMT_H_
#define _CPUF12POWERMGMT_H_
/*
* Family 12h CPU Power Management MSR definitions
*
*/
/* P-state Current Limit Register 0xC0010061 */
#define MSR_PSTATE_CURRENT_LIMIT 0xC0010061
/// Pstate Current Limit MSR Register
typedef struct {
UINT64 CurPstateLimit:3; ///< Current Pstate Limit
UINT64 :1; ///< Reserved
UINT64 PstateMaxVal:3; ///< Pstate Max Value
UINT64 :57; ///< Reserved
} PSTATE_CURLIM_MSR;
/* P-state Control Register 0xC0010062 */
#define MSR_PSTATE_CTL 0xC0010062
/// Pstate Control MSR Register
typedef struct {
UINT64 PstateCmd:3; ///< Pstate change command
UINT64 :61; ///< Reserved
} PSTATE_CTRL_MSR;
/* P-state Status Register 0xC0010063 */
#define MSR_PSTATE_STS 0xC0010063
/// Pstate Status MSR Register
typedef struct {
UINT64 CurPstate:3; ///< Current Pstate
UINT64 :61; ///< Reserved
} PSTATE_STS_MSR;
/* P-state Registers 0xC001006[B:4] */
#define MSR_PSTATE_0 0xC0010064
#define MSR_PSTATE_1 0xC0010065
#define MSR_PSTATE_2 0xC0010066
#define MSR_PSTATE_3 0xC0010067
#define MSR_PSTATE_4 0xC0010068
#define MSR_PSTATE_5 0xC0010069
#define MSR_PSTATE_6 0xC001006A
#define MSR_PSTATE_7 0xC001006B
#define PS_REG_BASE MSR_PSTATE_0 /* P-state Register base */
#define PS_MAX_REG MSR_PSTATE_7 /* Maximum P-State Register */
#define PS_MIN_REG MSR_PSTATE_0 /* Minimum P-State Register */
#define NM_PS_REG 8 /* number of P-state MSR registers */
/// Pstate MSR
typedef struct {
UINT64 CpuDid:4; ///< CPU core divisor identifier
UINT64 CpuFid:5; ///< CPU core frequency identifier
UINT64 CpuVid:7; ///< CPU core VID
UINT64 :16; ///< Reserved
UINT64 IddValue:8; ///< Current value field
UINT64 IddDiv:2; ///< Current divisor field
UINT64 :21; ///< Reserved
UINT64 PsEnable:1; ///< P-state Enable
} PSTATE_MSR;
/* COFVID Control Register 0xC0010070 */
#define MSR_COFVID_CTL 0xC0010070
/// COFVID Control MSR Register
typedef struct {
UINT64 CpuDid:4; ///< CPU core divisor identifier
UINT64 CpuDidMSD:5; ///< CPU core frequency identifier
UINT64 CpuVid:7; ///< CPU core VID
UINT64 PstateId:3; ///< P-state identifier
UINT64 IgnoreFidVidDid:1; ///< Ignore FID, VID, and DID
UINT64 :44; ///< Reserved
} COFVID_CTRL_MSR;
/* COFVID Status Register 0xC0010071 */
#define MSR_COFVID_STS 0xC0010071
/// COFVID Status MSR Register
typedef struct {
UINT64 CurCpuDid:4; ///< Current CPU core divisor ID
UINT64 CurCpuDidMSD:5; ///< Current CPU core frequency ID
UINT64 CurCpuVid:7; ///< Current CPU core VID
UINT64 CurPstate:3; ///< Current P-state
UINT64 :1; ///< Reserved
UINT64 PstateInProgress:1; ///< P-state change in progress
UINT64 :4; ///< Reserved
UINT64 CurNbVid:7; ///< Current northbridge VID
UINT64 StartupPstate:3; ///< Startup P-state number
UINT64 MaxVid:7; ///< Maximum voltage
UINT64 MinVid:7; ///< Minimum voltage
UINT64 MainPllOpFreqIdMax:6; ///< Main PLL operating frequency ID maximum
UINT64 :1; ///< Reserved
UINT64 CurPstateLimit:3; ///< Current P-state Limit
UINT64 :5; ///< Reserved
} COFVID_STS_MSR;
/* C-state Address Register 0xC0010073 */
#define MSR_CSTATE_ADDRESS 0xC0010073
/// C-state Address MSR Register
typedef struct {
UINT64 CstateAddr:16; ///< C-state address
UINT64 :48; ///< Reserved
} CSTATE_ADDRESS_MSR;
/* CPU Watchdog Timer Register 0xC0010074 */
#define MSR_CPU_WDT 0xC0010074
/// CPU Watchdog Timer Register
typedef struct {
UINT64 CpuWdtEn:1; ///< CPU watchdog timer enable
UINT64 CpuWdtTimeBase:2; ///< CPU watchdog timer time base
UINT64 CpuWdtCountSel:4; ///< CPU watchdog timer count select
UINT64 :57; ///< Reserved
} CPU_WDT_MSR;
/*
* Family 12h CPU Power Management PCI definitions
*
*/
/* Memory controller configuration low register D18F2x118 */
#define MEM_CFG_LOW_REG 0x118
#define MEM_CFG_LOW_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_2, MEM_CFG_LOW_REG))
/// Memory Controller Configuration Low
typedef struct {
UINT32 MctPriCpuRd:2; ///< CPU read priority
UINT32 MctPriCpuWr:2; ///< CPU write priority
UINT32 MctPriHiRd:2; ///< High-priority VC set read priority
UINT32 MctPriHiWr:2; ///< High-priority VC set write priority
UINT32 MctPriDefault:2; ///< Default non-write priority
UINT32 MctPriWr:2; ///< Default write priority
UINT32 :7; ///< Reserved
UINT32 C6DramLock:1; ///< C6 DRAM lock
UINT32 :8; ///< Reserved
UINT32 MctVarPriCntLmt:4; ///< Variable priority time limit
} MEM_CFG_LOW_REGISTER;
/* Hardware thermal control register D18F3x64 */
#define HTC_REG 0x64
#define HTC_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, HTC_REG))
/// Hardware Thermal Control PCI Register
typedef struct {
UINT32 HtcEn:1; ///< HTC Enable
UINT32 :3; ///< Reserved
UINT32 HtcAct:1; ///< HTC Active State
UINT32 HtcActSts:1; ///< HTC Active Status
UINT32 PslApicHiEn:1; ///< P-state limit higher APIC int enable
UINT32 PslApicLoEn:1; ///< P-state limit lower APIC int enable
UINT32 :8; ///< Reserved
UINT32 HtcTmpLmt:7; ///< HTC temperature limit
UINT32 HtcSlewSel:1; ///< HTC slew-controlled temp select
UINT32 HtcHystLmt:4; ///< HTC hysteresis
UINT32 HtcPstateLimit:3; ///< HTC P-state limit select
UINT32 HtcLock:1; ///< HTC lock
} HTC_REGISTER;
/* Power Control Miscellaneous Register D18F3xA0 */
#define PW_CTL_MISC_REG 0xA0
#define PW_CTL_MISC_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, PW_CTL_MISC_REG))
/// Power Control Miscellaneous PCI Register
typedef struct {
UINT32 PsiVid:7; ///< PSI_L VID threshold
UINT32 PsiVidEn:1; ///< PSI_L VID enable
UINT32 :1; ///< Reserved
UINT32 SviHighFreqSel:1; ///< SVI high frequency select
UINT32 :6; ///< Reserved
UINT32 ConfigId:12; ///< Configuration Identifier
UINT32 :3; ///< Reserved
UINT32 CofVidProg:1; ///< COF and VID of P-states programmed
} POWER_CTRL_MISC_REGISTER;
/* Clock Power/Timing Control 0 Register D18F3xD4 */
#define CPTC0_REG 0xD4
#define CPTC0_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, CPTC0_REG))
/// Clock Power Timing Control PCI Register
typedef struct {
UINT32 MainPllOpFreqId:6; ///< Main PLL Fid
UINT32 :1; ///< Main PLL Fid Enable
UINT32 ShallowHaltDidAllow:1; ///< Allow Shallow Halt Did
UINT32 ClkRampHystSel:4; ///< Clock Ramp Hysteresis Select
UINT32 OnionOutHyst:4; ///< ONION outbound hysteresis
UINT32 DisNclkGatingIdle:1; ///< Disable NCLK gating when idle
UINT32 ClkGatingEnDram:1; ///< Clock gating enable DRAM
UINT32 :1; ///< Reserved
UINT32 PstateSpecFuseSel:8; ///< P-State Specification Fuse Select
UINT32 :5; ///< Reserved
} CLK_PWR_TIMING_CTRL_REGISTER;
/* Clock Power/Timing Control 1 Register D18F3xD8 */
#define CPTC1_REG 0xD8
#define CPTC1_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, CPTC1_REG))
/// Clock Power Timing Control 1 PCI Register
typedef struct {
UINT32 :4; ///< Reserved
UINT32 VSRampSlamTime:3; ///< Voltage stabilization slam time
UINT32 ExtndTriDly:5; ///< Extend tri-state delay
UINT32 :20; ///< Reserved
} CLK_PWR_TIMING_CTRL1_REGISTER;
#define CPTC1_VSRAMPSLAMTIME_START (4)
#define CPTC1_VSRAMPSLAMTIME_END (6)
/* Clock Power/Timing Control 2 Register D18F3xDC */
#define CPTC2_REG 0xDC
#define CPTC2_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, CPTC2_REG))
/// Clock Power Timing Control 2 PCI Register
typedef struct {
UINT32 :8; ///< Reserved
UINT32 PstateMaxVal:3; ///< P-state maximum value
UINT32 :1; ///< Reserved
UINT32 NbPs0Vid:7; ///< NB VID
UINT32 NclkFreqDone:1; ///< NCLK frequency change done
UINT32 NbPs0NclkDiv:7; ///< NCLK divisor
UINT32 NbClockGateHyst:3; ///< Northbridge clock gating hysteresis
UINT32 NbClockGateEn:1; ///< Northbridge clock gating enable
UINT32 CnbCifClockGateEn:1; ///< CNB CIF clock gating enable
} CLK_PWR_TIMING_CTRL2_REGISTER;
/* Northbridge Capabilities Register D18F3xE8 */
#define NB_CAPS_REG 0xE8
#define NB_CAPS_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, NB_CAPS_REG))
/// Northbridge Capabilities PCI Register
typedef struct {
UINT32 DctDualCap:1; ///< Two-channel DRAM capable
UINT32 :4; ///< Reserved
UINT32 DdrMaxRate:3; ///< Maximum DRAM data rate
UINT32 MctCap:1; ///< Memory controller capable
UINT32 SvmCapable:1; ///< SVM capable
UINT32 HtcCapable:1; ///< HTC capable
UINT32 :1; ///< Reserved
UINT32 CmpCap:2; ///< CMP capable
UINT32 :14; ///< Reserved
UINT32 LHtcCapable:1; ///< LHTC capable
UINT32 :3; ///< Reserved
} NB_CAPS_REGISTER;
/* Clock Power/Timing Control 3 Register D18F3x128 */
#define CPTC3_REG 0x128
#define CPTC3_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, CPTC3_REG))
/// Clock Power Timing Control 3 PCI Register
typedef struct {
UINT32 C6Vid:7; ///< C6 VID
UINT32 :1; ///< Reserved
UINT32 NbPsiVid:7; ///< NB PSI_L VID threshold
UINT32 NbPsiVidEn:1; ///< NB PSI_L enable
UINT32 :16; ///< Reserved
} CLK_PWR_TIMING_CTRL3_REGISTER;
/* Local hardware thermal control register D18F3x138 */
#define LHTC_REG 0x138
#define LHTC_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, LHTC_REG))
/// Local Hardware Thermal Control PCI Register
typedef struct {
UINT32 LHtcEn:1; ///< Local HTC Enable
UINT32 :7; ///< Reserved
UINT32 LHtcAct:1; ///< Local HTC Active State
UINT32 :3; ///< Reserved
UINT32 LHtcActSts:1; ///< Local HTC Active Status
UINT32 :3; ///< Reserved
UINT32 LHtcTmpLmt:7; ///< Local HTC temperature limit
UINT32 LHtcSlewSel:1; ///< Local HTC slew-controlled temp select
UINT32 LHtcHystLmt:4; ///< Local HTC hysteresis
UINT32 LHtcPstateLimit:3; ///< Local HTC P-state limit select
UINT32 LHtcLock:1; ///< HTC lock
} LHTC_REGISTER;
/* C-state Control 1 Register D18F4x118 */
#define CSTATE_CTRL1_REG 0x118
#define CSTATE_CTRL1_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CSTATE_CTRL1_REG))
/// C-state Control 1 Register
typedef struct {
UINT32 CstAct0:3; ///< C-state action field 0
UINT32 :5; ///< Reserved
UINT32 CstAct1:3; ///< C-state action field 1
UINT32 :5; ///< Reserved
UINT32 CstAct2:3; ///< C-state action field 2
UINT32 :5; ///< Reserved
UINT32 CstAct3:3; ///< C-state action field 3
UINT32 :5; ///< Reserved
} CSTATE_CTRL1_REGISTER;
/* C-state Control 2 Register D18F4x11C */
#define CSTATE_CTRL2_REG 0x11C
#define CSTATE_CTRL2_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CSTATE_CTRL2_REG))
/// C-state Control 2 Register
typedef struct {
UINT32 CstAct4:3; ///< C-state action field 4
UINT32 :5; ///< Reserved
UINT32 CstAct5:3; ///< C-state action field 5
UINT32 :5; ///< Reserved
UINT32 CstAct6:3; ///< C-state action field 6
UINT32 :5; ///< Reserved
UINT32 CstAct7:3; ///< C-state action field 7
UINT32 :5; ///< Reserved
} CSTATE_CTRL2_REGISTER;
/* Core Performance Boost Control Register D18F4x15C */
#define CPB_CTRL_REG 0x15C
#define CPB_CTRL_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CPB_CTRL_REG))
/// Core Performance Boost Control Register
typedef struct {
UINT32 BoostSrc:2; ///< Boost source
UINT32 NumBoostStates:3; ///< Number of boosted states
UINT32 :23; ///< Reserved
UINT32 IgnoreBoostThresh:1; ///< Ignore boost threshold
UINT32 BoostEnAllCores:1; ///< Boost enable all cores
UINT32 :2; ///< Reserved
} CPB_CTRL_REGISTER;
/* CPU State Power Management Dynamic Control 0 Register D18F4x1A8 */
#define CPU_STATE_PM_CTRL0_REG 0x1A8
#define CPU_STATE_PM_CTRL0_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CPU_STATE_PM_CTRL0_REG))
/// CPU State Power Management Dynamic Control 0 Register
typedef struct {
UINT32 SingleHaltCpuDid:5; ///< Single hlt CPU DID
UINT32 AllHaltCpuDid:5; ///< All hlt CPU DID
UINT32 :5; ///< Reserved
UINT32 CpuProbEn:1; ///< CPU probe enable
UINT32 :1; ///< Reserved
UINT32 PService:3; ///< Service P-state
UINT32 PServiceTmr:3; ///< Service P-state timer
UINT32 PServiceTmrEn:1; ///< Service P-state timer enable
UINT32 DramSrEn:1; ///< DRAM self-refresh enable
UINT32 MemTriStateEn:1; ///< Memory clock tri-state enable
UINT32 DramSrHyst:3; ///< DRAM self-refresh hysteresis time
UINT32 DramSrHystEnable:1; ///< DRAM self-refresh hysteresis enable
UINT32 :2; ///< Reserved
} CPU_STATE_PM_CTRL0_REGISTER;
/* CPU State Power Management Dynamic Control 1 Register D18F4x1AC */
#define CPU_STATE_PM_CTRL1_REG 0x1AC
#define CPU_STATE_PM_CTRL1_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CPU_STATE_PM_CTRL1_REG))
/// CPU State Power Management Dynamic Control 1 Register
typedef struct {
UINT32 :5; ///< Reserved
UINT32 C6Did:5; ///< CC6 divisor
UINT32 :6; ///< Reserved
UINT32 PstateIdCoreOffExit:3; ///< P-state ID core-off exit
UINT32 :7; ///< Reserved
UINT32 PkgC6Cap:1; ///< Package C6 capable
UINT32 CoreC6Cap:1; ///< Core C6 capable
UINT32 PkgC6Dis:1; ///< Package C6 disable
UINT32 CoreC6Dis:1; ///< Core C6 disable
UINT32 CstPminEn:1; ///< C-state Pmin enable
UINT32 :1; ///< Reserved
} CPU_STATE_PM_CTRL1_REGISTER;
/* C6 Base Register D18F4x1AC */
#define C6_BASE_REG 0x12C
#define C6_BASE_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, C6_BASE_REG))
/// C6 Base Register
typedef struct {
UINT32 C6Base:16; ///< C6 base[39:24]
UINT32 :16; ///< Reserved
} C6_BASE_REGISTER;
/* NB P-state Config Low Register D18F6x90 */
#define NB_PSTATE_CFG_LOW_REG 0x90
#define NB_PSTATE_CFG_LOW_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_6, NB_PSTATE_CFG_LOW_REG))
/// NB P-state Config Low Register
typedef struct {
UINT32 NbPs1NclkDiv:7; ///< NBP1 NCLK divisor
UINT32 :1; ///< Reserved
UINT32 NbPs1Vid:7; ///< NBP1 NCLK VID
UINT32 :1; ///< Reserved
UINT32 NbPs1GnbSlowIgn:1; ///< NB P-state ignore GNB slow signal
UINT32 :3; ///< Reserved
UINT32 NbPsLock:1; ///< NB P-state lock
UINT32 :7; ///< Reserved
UINT32 NbPsForceReq:1; ///< NB P-state force request
UINT32 NbPsForceSel:1; ///< NB P-state force selection
UINT32 NbPsCtrlDis:1; ///< NB P-state control disable
UINT32 NbPsCap:1; ///< NB P-state capable
} NB_PSTATE_CFG_LOW_REGISTER;
/* NB P-state Config High Register D18F6x94 */
#define NB_PSTATE_CFG_HIGH_REG 0x94
#define NB_PSTATE_CFG_HIGH_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_6, NB_PSTATE_CFG_HIGH_REG))
/// NB P-state Config High Register
typedef struct {
UINT32 CpuPstateThr:3; ///< CPU P-state threshold
UINT32 CpuPstateThrEn:1; ///< CPU P-state threshold enable
UINT32 NbPs1NoTransOnDma:1; ///< NB P-state no transitions on DMA
UINT32 :15; ///< Reserved
UINT32 NbPsNonC0Timer:3; ///< NB P-state non-C0 timer
UINT32 NbPsC0Timer:3; ///< NB P-state C0 timer
UINT32 NbPs1ResTmrMin:3; ///< NBP1 minimum residency timer
UINT32 NbPs0ResTmrMin:3; ///< NBP0 minimum residency timer
} NB_PSTATE_CFG_HIGH_REGISTER;
/* NB P-state Control and Status Register D18F6x98 */
#define NB_PSTATE_CTRL_STS_REG 0x98
#define NB_PSTATE_CTRL_STS_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_6, NB_PSTATE_CTRL_STS_REG))
/// NB P-state Control and Status Register
typedef struct {
UINT32 NbPsTransInFlight:1; ///< NB P-state transition in flight
UINT32 NbPs1ActSts:1; ///< NB P-state 1 active status
UINT32 NbPs1Act:1; ///< NB P-state 1 active
UINT32 :27; ///< Reserved
UINT32 NbPsCsrAccSel:1; ///< NB P-state register accessibility select
UINT32 NbPsDbgEn:1; ///< NB P-state debug enable
} NB_PSTATE_CTRL_STS_REGISTER;
/* NCLK Reduction Control D18F6x9C */
#define NCLK_REDUCTION_CTRL_REG 0x9C
#define NCLK_REDUCTION_CTRL_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_6, NCLK_REDUCTION_CTRL_REG))
/// NCLK Reduction Control
typedef struct {
UINT32 NclkRedDiv:7; ///< NCLK reduction divisor
UINT32 NclkRedSelfRefrAlways:1; ///< NCLK reduction always self refresh
UINT32 NclkRampWithDllRelock:1; ///< NCLK ramp mode
UINT32 :23; ///< Reserved
} NCLK_REDUCTION_CTRL_REGISTER;
/// enum for DSM workaround control
typedef enum {
CC6_DSM_WORK_AROUND_DISABLE = 0, ///< work around disable
CC6_DSM_WORK_AROUND_NORMAL_TRAFFIC, ///< work around With Normal Traffic
CC6_DSM_WORK_AROUND_HIGH_PRIORITY_CHANNEL, ///< work around With High Priority Channel
} CC6_DSM_WORK_AROUND;
#endif /* _CPUF12POWERMGMT_H */

150
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@ -1,150 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_12 Power Management Initialization Steps
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F12
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "Ids.h"
#include "cpuRegisters.h"
#include "cpuApicUtilities.h"
#include "cpuFamilyTranslation.h"
//#include "IdsF12AllService.h"
#include "cpuPowerMgmtSystemTables.h"
#include "cpuF12SoftwareThermal.h"
#include "cpuF12PowerPlane.h"
#include "cpuF12PowerCheck.h"
#include "cpuF12EarlyNbPstateInit.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_CPU_FAMILY_0X12_CPUF12POWERMGMTSYSTEMTABLES_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
GetF12SysPmTable (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **SysPmTblPtr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/* Family 12h Table */
/* ---------------------- */
CONST SYS_PM_TBL_STEP ROMDATA CpuF12SysPmTableArray[] =
{
IDS_INITIAL_F12_PM_STEP
// Step 1 - Power Plane Initialization
// Execute both cold & warm
{
0, // ExeFlags
F12PmPwrPlaneInit // Function Pointer
},
// Step 2 - Current Delivery Check
// Execute both cold & warm
{
0, // ExeFlags
F12PmPwrCheck // Function Pointer
},
// Step x - Nb P-state init
// Execute both cold & warm
{
0, // ExeFlags
F12NbPstateEarlyInit // Function Pointer
},
// Step x - Software Thermal Control Init
// Execute both cold & warm
{
0, // ExeFlags
F12PmThermalInit // Function Pointer
},
};
/*---------------------------------------------------------------------------------------*/
/**
* Returns the appropriate table of steps to perform to initialize the power management
* subsystem.
*
* @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[out] SysPmTblPtr Points to the first entry in the table.
* @param[out] NumberOfElements Number of valid entries in the table.
* @param[in] StdHeader Header for library and services.
*
*/
VOID
GetF12SysPmTable (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **SysPmTblPtr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
*NumberOfElements = (sizeof (CpuF12SysPmTableArray) / sizeof (SYS_PM_TBL_STEP));
*SysPmTblPtr = CpuF12SysPmTableArray;
}

312
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@ -1,312 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_12 Power Plane Initialization
*
* Performs the "BIOS Requirements for Power Plane Initialization" as described
* in the BKDG.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F12
* @e \$Revision: 47330 $ @e \$Date: 2011-02-18 10:39:06 +0800 (Fri, 18 Feb 2011) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "cpuRegisters.h"
#include "cpuFamilyTranslation.h"
#include "cpuServices.h"
#include "cpuF12PowerMgmt.h"
#include "cpuF12PowerPlane.h"
#include "OptionFamily12hEarlySample.h"
#include "GnbRegistersLN.h"
#include "NbSmuLib.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_CPU_FAMILY_0X12_CPUF12POWERPLANE_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
extern F12_ES_CORE_SUPPORT F12EarlySampleCoreSupport;
// Register encodings for D18F3xD8[VSRampSlamTime]
STATIC CONST UINT32 ROMDATA F12VSRampSlamWaitTimes[8] =
{
625, // 000b: 6.25us
500, // 001b: 5.00us
417, // 010b: 4.17us
313, // 011b: 3.13us
250, // 100b: 2.50us
167, // 101b: 1.67us
125, // 110b: 1.25us
100 // 111b: 1.00us
};
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
STATIC
F12PmVrmLowPowerModeEnable (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
IN PCI_ADDR PciAddress,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
* Family 12h core 0 entry point for performing power plane initialization.
*
* The steps are as follows:
* 1. BIOS must initialize D18F3xD8[VSRampSlamTime].
* 2. BIOS must configure D18F3xA0[PsiVidEn & PsiVid] and
* D18F3x128[NbPsiVidEn & NbPsiVid].
* 3. BIOS must program D18F3xDC[NbPs0Vid] = FCRxFE00_6000[NbPs0Vid] - 1.
* BIOS must program D18F3xDC[NbPs0Vid] = FCRxFE00_6000[NbPs0Vid].
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] CpuEarlyParams Service parameters
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
F12PmPwrPlaneInit (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 SystemSlewRate;
UINT32 WaitTime;
UINT32 VSRampSlamTime;
UINT32 LocalPciRegister;
UINT32 VoltageDifference;
UINT32 SingleVidStepTransitionTime;
UINT32 TransitionTime;
PCI_ADDR PciAddress;
FCRxFE00_6000_STRUCT FCRxFE00_6000;
// Step 1 - Configure D18F3xD8[VSRampSlamTime] based on platform requirements.
// Voltage Ramp Time = maximum time to change voltage by 12.5mV rounded to the next higher encoding.
SystemSlewRate = (CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].SlewRate <=
CpuEarlyParams->PlatformConfig.VrmProperties[NbVrm].SlewRate) ?
CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].SlewRate :
CpuEarlyParams->PlatformConfig.VrmProperties[NbVrm].SlewRate;
ASSERT (SystemSlewRate != 0);
// First, calculate the time it takes to change 12.5mV using the VRM slew rate.
WaitTime = (12500 * 100) / SystemSlewRate;
if (((12500 * 100) % SystemSlewRate) != 0) {
WaitTime++;
}
// Next, round it to the appropriate encoded value. We will start from encoding 111b which corresponds
// to the fastest slew rate, and work our way down to 000b, which represents the slowest an acceptable
// VRM can be.
for (VSRampSlamTime = ((sizeof (F12VSRampSlamWaitTimes) / sizeof (F12VSRampSlamWaitTimes[0])) - 1); VSRampSlamTime > 0; VSRampSlamTime--) {
if (WaitTime <= F12VSRampSlamWaitTimes[VSRampSlamTime]) {
break;
}
}
if (WaitTime > F12VSRampSlamWaitTimes[0]) {
// The VRMs on this motherboard are too slow for this CPU.
IDS_ERROR_TRAP;
}
// Lastly, program D18F3xD8[VSRampSlamTime] with the appropriate encoded value.
PciAddress.AddressValue = CPTC1_PCI_ADDR;
LibAmdPciWriteBits (PciAddress, CPTC1_VSRAMPSLAMTIME_END, CPTC1_VSRAMPSLAMTIME_START, &VSRampSlamTime, StdHeader);
// Step 2 - Configure D18F3xA0[PsiVidEn & PsiVid] and D18F3x128[NbPsiVidEn & NbPsiVid].
F12PmVrmLowPowerModeEnable (FamilySpecificServices, CpuEarlyParams, PciAddress, StdHeader);
// Step 3 - Program D18F3xDC[NbPs0Vid] = FCRxFE00_6000[NbPs0Vid] - 1.
// Wait out the appropriate voltage stabilization time.
// Program D18F3xDC[NbPs0Vid] = FCRxFE00_6000[NbPs0Vid].
// Wait out the appropriate voltage stabilization time.
FCRxFE00_6000.Value = NbSmuReadEfuse (FCRxFE00_6000_ADDRESS, StdHeader);
F12EarlySampleCoreSupport.F12PowerPlaneInitHook (&FCRxFE00_6000, StdHeader);
PciAddress.AddressValue = CPTC2_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
if (((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->NbPs0Vid >= FCRxFE00_6000.Field.NbPs0Vid) {
VoltageDifference = ((((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->NbPs0Vid - FCRxFE00_6000.Field.NbPs0Vid) + 1);
} else {
VoltageDifference = ((FCRxFE00_6000.Field.NbPs0Vid - ((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->NbPs0Vid) - 1);
}
SingleVidStepTransitionTime = WaitTime / 100;
if ((WaitTime % 100) != 0) {
SingleVidStepTransitionTime++;
}
TransitionTime = SingleVidStepTransitionTime * VoltageDifference;
((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->NbPs0Vid = FCRxFE00_6000.Field.NbPs0Vid - 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
WaitMicroseconds (TransitionTime, StdHeader);
((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->NbPs0Vid = FCRxFE00_6000.Field.NbPs0Vid;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
WaitMicroseconds (SingleVidStepTransitionTime, StdHeader);
}
/*---------------------------------------------------------------------------------------*/
/**
* Sets up PSI_L operation.
*
* This function implements the AMD_CPU_EARLY_PARAMS.VrmLowPowerThreshold parameter.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] CpuEarlyParams Contains VrmLowPowerThreshold parameter.
* @param[in] PciAddress PCI address of the executing core's config space.
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
STATIC
F12PmVrmLowPowerModeEnable (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
IN PCI_ADDR PciAddress,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 Pstate;
UINT32 PstateMaxVal;
UINT32 PstateCurrent;
UINT32 NextPstateCurrent;
UINT32 NextPstateCurrentRaw;
UINT32 LocalPciRegister;
UINT32 PreviousVid;
UINT32 CurrentVid;
UINT32 C6Vid;
UINT32 HwPsMaxVal;
UINT64 PstateMsr;
BOOLEAN IsPsiEnabled;
// Set up PSI_L for VDD
IsPsiEnabled = FALSE;
PreviousVid = 0x7F;
CurrentVid = 0x7F;
PciAddress.Address.Function = FUNC_3;
PciAddress.Address.Register = CPTC2_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &HwPsMaxVal, StdHeader);
if (CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].LowPowerThreshold != 0) {
PstateMaxVal = (UINT32) ((CLK_PWR_TIMING_CTRL2_REGISTER *) &HwPsMaxVal)->PstateMaxVal;
FamilySpecificServices->GetProcIddMax (FamilySpecificServices, (UINT8) 0, &PstateCurrent, StdHeader);
for (Pstate = 0; Pstate <= PstateMaxVal; Pstate++) {
LibAmdMsrRead ((UINT32) (Pstate + PS_REG_BASE), &PstateMsr, StdHeader);
CurrentVid = (UINT32) ((PSTATE_MSR *) &PstateMsr)->CpuVid;
if (Pstate == PstateMaxVal) {
NextPstateCurrentRaw = 0;
NextPstateCurrent = 0;
} else {
FamilySpecificServices->GetProcIddMax (FamilySpecificServices, (UINT8) (Pstate + 1), &NextPstateCurrentRaw, StdHeader);
NextPstateCurrent = NextPstateCurrentRaw + CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].InrushCurrentLimit;
}
if ((PstateCurrent <= CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].LowPowerThreshold) &&
(NextPstateCurrent <= CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].LowPowerThreshold) &&
(CurrentVid != PreviousVid)) {
IsPsiEnabled = TRUE;
break;
} else {
PstateCurrent = NextPstateCurrentRaw;
PreviousVid = CurrentVid;
}
}
// At this point, if IsPsiEnabled is still FALSE, then a suitable threshold
// is not found.
if (!IsPsiEnabled) {
PciAddress.AddressValue = CPTC3_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
C6Vid = ((CLK_PWR_TIMING_CTRL3_REGISTER *) &LocalPciRegister)->C6Vid;
// Set threshold to C6Vid and set IsPsiEnabled to TRUE only if C6Vid value
// is larger than the last seen VID code.
if (C6Vid > PreviousVid) {
CurrentVid = C6Vid;
IsPsiEnabled = TRUE;
}
}
}
PciAddress.AddressValue = PW_CTL_MISC_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
if (IsPsiEnabled) {
((POWER_CTRL_MISC_REGISTER *) &LocalPciRegister)->PsiVid = CurrentVid;
((POWER_CTRL_MISC_REGISTER *) &LocalPciRegister)->PsiVidEn = 1;
} else {
((POWER_CTRL_MISC_REGISTER *) &LocalPciRegister)->PsiVidEn = 0;
}
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
// Set up NBPSI_L for VDDNB
PciAddress.AddressValue = CPTC3_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
if (CpuEarlyParams->PlatformConfig.VrmProperties[NbVrm].LowPowerThreshold != 0) {
((CLK_PWR_TIMING_CTRL3_REGISTER *) &LocalPciRegister)->NbPsiVid = 0;
((CLK_PWR_TIMING_CTRL3_REGISTER *) &LocalPciRegister)->NbPsiVidEn = 1;
} else {
((CLK_PWR_TIMING_CTRL3_REGISTER *) &LocalPciRegister)->NbPsiVidEn = 0;
}
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
}

76
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@ -1,76 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_12 Power Plane related functions and structures
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F12
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _CPU_F12_POWER_PLANE_H_
#define _CPU_F12_POWER_PLANE_H_
/*---------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*---------------------------------------------------------------------------------------
*/
VOID
F12PmPwrPlaneInit (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
);
#endif // _CPU_F12_POWER_PLANE_H_

481
src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12Pstate.c
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@ -1,481 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_12 Pstate feature support functions.
*
* Provides the functions necessary to initialize the Pstate feature.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F12
* @e \$Revision: 44702 $ @e \$Date: 2011-01-05 06:54:00 +0800 (Wed, 05 Jan 2011) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "cpuPstateTables.h"
#include "cpuFamilyTranslation.h"
#include "cpuRegisters.h"
#include "cpuF12Utilities.h"
#include "cpuF12PowerMgmt.h"
#include "CommonReturns.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_CPU_FAMILY_0X12_CPUF12PSTATE_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
AGESA_STATUS
F12GetPstateTransLatency (
IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
IN PSTATE_LEVELING *PStateLevelingBufferStructPtr,
IN PCI_ADDR *PciAddress,
OUT UINT32 *TransitionLatency,
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
F12GetPstateFrequency (
IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
IN UINT8 StateNumber,
OUT UINT32 *FrequencyInMHz,
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
F12GetPstatePower (
IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
IN UINT8 StateNumber,
OUT UINT32 *PowerInMw,
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
F12GetPstateMaxState (
IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
OUT UINT32 *MaxPStateNumber,
OUT UINT8 *NumberOfBoostStates,
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
F12GetPstateRegisterInfo (
IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
IN UINT32 PState,
OUT BOOLEAN *PStateEnabled,
IN OUT UINT32 *IddVal,
IN OUT UINT32 *IddDiv,
OUT UINT32 *SwPstateNumber,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
* Family specific call to check if Pstate PSD is dependent.
*
* @param[in] PstateCpuServices Pstate CPU services.
* @param[in,out] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] StdHeader Config Handle for library, services.
*
* @retval TRUE PSD is dependent.
* @retval FALSE PSD is independent.
*
*/
BOOLEAN
STATIC
F12IsPstatePsdDependent (
IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
IN OUT PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
// F12h defaults to dependent PSD; allow Platform Configuration to
// overwrite the default setting.
if (PlatformConfig->ForcePstateIndependent) {
return FALSE;
}
return TRUE;
}
/**
* Family specific call to set core TscFreqSel.
*
* @param[in] PstateCpuServices Pstate CPU services.
* @param[in] StdHeader Config Handle for library, services.
*
*/
VOID
STATIC
F12SetTscFreqSel (
IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 MsrValue;
LibAmdMsrRead (MSR_HWCR, &MsrValue, StdHeader);
MsrValue = MsrValue | BIT24;
LibAmdMsrWrite (MSR_HWCR, &MsrValue, StdHeader);
}
/*---------------------------------------------------------------------------------------*/
/**
* Family specific call to get Pstate Transition Latency.
*
* Follow BKDG, return zero currently.
*
* @param[in] PstateCpuServices Pstate CPU services.
* @param[in] PStateLevelingBufferStructPtr Pstate row data buffer pointer
* @param[in] PciAddress Pci address
* @param[out] TransitionLatency The transition latency.
* @param[in] StdHeader Header for library and services
*
* @retval AGESA_SUCCESS Always succeeds.
*/
AGESA_STATUS
F12GetPstateTransLatency (
IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
IN PSTATE_LEVELING *PStateLevelingBufferStructPtr,
IN PCI_ADDR *PciAddress,
OUT UINT32 *TransitionLatency,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
//
// TransitionLatency (us) = BusMasterLatency (us) = 0 us, calculation may
// change due to a potential new encoding.
//
*TransitionLatency = 0;
return (AGESA_SUCCESS);
}
/*---------------------------------------------------------------------------------------*/
/**
* Family specific call to calculates the frequency in megahertz of the desired P-state.
*
* @param[in] PstateCpuServices Pstate CPU services.
* @param[in] StateNumber The P-State to analyze.
* @param[out] FrequencyInMHz The P-State's frequency in MegaHertz
* @param[in] StdHeader Header for library and services
*
* @retval AGESA_SUCCESS Always Succeeds.
*/
AGESA_STATUS
F12GetPstateFrequency (
IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
IN UINT8 StateNumber,
OUT UINT32 *FrequencyInMHz,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 CpuDid;
UINT32 CpuFid;
UINT32 LocalPciRegister;
UINT64 LocalMsrRegister;
BOOLEAN FrequencyCalculated;
PCI_ADDR PciAddress;
ASSERT (StateNumber < NM_PS_REG);
LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &LocalMsrRegister, StdHeader);
ASSERT (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1);
CpuDid = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->CpuDid);
CpuFid = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->CpuFid);
FrequencyCalculated = FALSE;
switch (CpuDid) {
case 0:
CpuDid = 10;
break;
case 1:
CpuDid = 15;
break;
case 2:
CpuDid = 20;
break;
case 3:
CpuDid = 30;
break;
case 4:
CpuDid = 40;
break;
case 5:
CpuDid = 60;
break;
case 6:
CpuDid = 80;
break;
case 7:
CpuDid = 120;
break;
case 8:
CpuDid = 160;
break;
case 14:
if (CpuFid != 0) {
CpuDid = 160;
} else {
FrequencyCalculated = TRUE;
*FrequencyInMHz = 100;
}
break;
default:
// CpuDid is set to an undefined value. This is due to either a misfused CPU, or
// an invalid P-state MSR write.
ASSERT (FALSE);
CpuDid = 1;
break;
}
if (!FrequencyCalculated) {
PciAddress.AddressValue = MAKE_SBDFO (0, 0, PCI_DEV_BASE, 4, 0x15C);
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
if ((LocalPciRegister & BIT30) != 0) {
CpuFid += 0x20;
} else {
CpuFid += 0x10;
}
*FrequencyInMHz = (((100 * 10) * CpuFid) / CpuDid);
}
return (AGESA_SUCCESS);
}
/*--------------------------------------------------------------------------------------*/
/**
*
* Family specific call to calculates the power in milliWatts of the desired P-state.
*
* @param[in] PstateCpuServices Pstate CPU services.
* @param[in] StateNumber Which P-state to analyze
* @param[out] PowerInMw The Power in milliWatts of that P-State
* @param[in] StdHeader Header for library and services
*
* @retval AGESA_SUCCESS Always succeeds.
*/
AGESA_STATUS
F12GetPstatePower (
IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
IN UINT8 StateNumber,
OUT UINT32 *PowerInMw,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 CpuVid;
UINT32 IddValue;
UINT32 IddDiv;
UINT32 V_x10000;
UINT32 Power;
UINT64 LocalMsrRegister;
ASSERT (StateNumber < NM_PS_REG);
LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &LocalMsrRegister, StdHeader);
ASSERT (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1);
CpuVid = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->CpuVid);
IddValue = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->IddValue);
IddDiv = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->IddDiv);
if (CpuVid >= 0x7C) {
V_x10000 = 0;
} else {
V_x10000 = 15500L - (125L * CpuVid);
}
Power = V_x10000 * IddValue;
switch (IddDiv) {
case 0:
*PowerInMw = Power / 10L;
break;
case 1:
*PowerInMw = Power / 100L;
break;
case 2:
*PowerInMw = Power / 1000L;
break;
default:
// IddDiv is set to an undefined value. This is due to either a misfused CPU, or
// an invalid P-state MSR write.
ASSERT (FALSE);
*PowerInMw = 0;
break;
}
return (AGESA_SUCCESS);
}
/*---------------------------------------------------------------------------------------*/
/**
* Family specific call to get CPU pstate max state.
*
* @param[in] PstateCpuServices Pstate CPU services.
* @param[out] MaxPStateNumber The max hw pstate value on the current socket.
* @param[out] NumberOfBoostStates The number of boosted P-states on the current socket.
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
* @retval AGESA_SUCCESS Always succeeds.
*/
AGESA_STATUS
F12GetPstateMaxState (
IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
OUT UINT32 *MaxPStateNumber,
OUT UINT8 *NumberOfBoostStates,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 NumBoostStates;
UINT64 MsrValue;
UINT32 LocalPciRegister;
PCI_ADDR PciAddress;
// For F12 CPU, skip boosted p-state. The boosted p-state number = D18F4x15C[NumBoostStates].
PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // D18F4x15C
NumBoostStates = ((CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates;
*NumberOfBoostStates = (UINT8) NumBoostStates;
//
// Read PstateMaxVal [6:4] from MSR C001_0061
// So, we will know the max pstate state in this socket.
//
LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &MsrValue, StdHeader);
*MaxPStateNumber = (UINT32) (((PSTATE_CURLIM_MSR *) &MsrValue)->PstateMaxVal) + NumBoostStates;
return (AGESA_SUCCESS);
}
/*---------------------------------------------------------------------------------------*/
/**
* Family specific call to get CPU pstate register information.
*
* @param[in] PstateCpuServices Pstate CPU services.
* @param[in] PState Input Pstate number for query.
* @param[out] PStateEnabled Boolean flag return pstate enable.
* @param[in,out] IddVal Pstate current value.
* @param[in,out] IddDiv Pstate current divisor.
* @param[out] SwPstateNumber Software P-state number.
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
* @retval AGESA_SUCCESS Always succeeds.
*/
AGESA_STATUS
F12GetPstateRegisterInfo (
IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
IN UINT32 PState,
OUT BOOLEAN *PStateEnabled,
IN OUT UINT32 *IddVal,
IN OUT UINT32 *IddDiv,
OUT UINT32 *SwPstateNumber,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 LocalMsrRegister;
UINT32 LocalPciRegister;
PCI_ADDR PciAddress;
ASSERT (PState < NM_PS_REG);
// For F12 CPU, skip boosted p-state. The boosted p-state number = D18F4x15C[NumBoostStates].
PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // D18F4x15C
// Read PSTATE MSRs
LibAmdMsrRead (PS_REG_BASE + (UINT32) PState, &LocalMsrRegister, StdHeader);
*SwPstateNumber = PState;
if (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) {
// PState enable = bit 63
*PStateEnabled = TRUE;
//
// Check input pstate belongs to Boosted-Pstate, if yes, return *PStateEnabled = FALSE.
//
if (PState < ((CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates) {
*PStateEnabled = FALSE;
} else {
*SwPstateNumber = PState - ((CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates;
}
} else {
*PStateEnabled = FALSE;
}
// Bits 39:32 (high 32 bits [7:0])
*IddVal = (UINT32) ((PSTATE_MSR *) &LocalMsrRegister)->IddValue;
// Bits 41:40 (high 32 bits [9:8])
*IddDiv = (UINT32) ((PSTATE_MSR *) &LocalMsrRegister)->IddDiv;
return (AGESA_SUCCESS);
}
CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F12PstateServices =
{
0,
(PF_PSTATE_PSD_IS_NEEDED) CommonReturnTrue,
F12IsPstatePsdDependent,
F12SetTscFreqSel,
F12GetPstateTransLatency,
F12GetPstateFrequency,
(PF_CPU_SET_PSTATE_LEVELING_REG) CommonReturnAgesaSuccess,
F12GetPstatePower,
F12GetPstateMaxState,
F12GetPstateRegisterInfo
};

128
src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12SoftwareThermal.c
View File

@ -1,128 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_12 thermal initialization
*
* Performs processor thermal initialization.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F12
* @e \$Revision: 48183 $ @e \$Date: 2011-03-04 15:53:58 +0800 (Fri, 04 Mar 2011) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "cpuRegisters.h"
#include "cpuFamilyTranslation.h"
#include "cpuF12PowerMgmt.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_CPU_FAMILY_0X12_CPUF12SOFTWARETHERMAL_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
F12PmThermalInit (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------*/
/**
* Main entry point for initializing the SW Thermal Control
* safety net feature.
*
* This must be run by all Family 12h core 0s in the system.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] CpuEarlyParamsPtr Service parameters.
* @param[in] StdHeader Config handle for library and services.
*/
VOID
F12PmThermalInit (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 NbCaps;
UINT32 LocalPciRegister;
PCI_ADDR PciAddress;
PciAddress.AddressValue = NB_CAPS_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &NbCaps, StdHeader);
if (((NB_CAPS_REGISTER *) &NbCaps)->HtcCapable == 1) {
PciAddress.AddressValue = HTC_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
if (((HTC_REGISTER *) &LocalPciRegister)->HtcTmpLmt != 0) {
// Enable HTC
((HTC_REGISTER *) &LocalPciRegister)->HtcEn = 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
}
}
if (((NB_CAPS_REGISTER *) &NbCaps)->LHtcCapable == 1) {
PciAddress.AddressValue = LHTC_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
if (((LHTC_REGISTER *) &LocalPciRegister)->LHtcTmpLmt != 0) {
// Enable local HTC
((LHTC_REGISTER *) &LocalPciRegister)->LHtcEn = 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
}
}
}

78
src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12SoftwareThermal.h
View File

@ -1,78 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_12 thermal initialization related functions and structures
*
* Performs processor thermal initialization.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F12
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _CPU_F12_SOFTWARE_THERMAL_H_
#define _CPU_F12_SOFTWARE_THERMAL_H_
/*---------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*---------------------------------------------------------------------------------------
*/
VOID
F12PmThermalInit (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
IN AMD_CONFIG_PARAMS *StdHeader
);
#endif // _CPU_F12_SOFTWARE_THERMAL_H_

594
src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12Utilities.c
View File

@ -1,594 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_12 specific utility functions.
*
* Provides numerous utility functions specific to family 12h.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F12
* @e \$Revision: 44870 $ @e \$Date: 2011-01-08 14:23:12 +0800 (Sat, 08 Jan 2011) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "cpuRegisters.h"
#include "cpuFamilyTranslation.h"
#include "cpuPstateTables.h"
#include "cpuF12PowerMgmt.h"
#include "cpuServices.h"
#include "cpuF12Utilities.h"
#include "cpuPostInit.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_CPU_FAMILY_0X12_CPUF12UTILITIES_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable;
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
F12ConvertEnabledBitsIntoCount (
OUT UINT8 *EnabledCoreCountPtr,
IN UINT8 FusedCoreCount,
IN UINT8 EnabledCores
);
BOOLEAN
F12GetNbPstateInfo (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN PCI_ADDR *PciAddress,
IN UINT32 NbPstate,
OUT UINT32 *FreqNumeratorInMHz,
OUT UINT32 *FreqDivisor,
OUT UINT32 *VoltageInuV,
IN AMD_CONFIG_PARAMS *StdHeader
);
BOOLEAN
F12IsNbPstateEnabled (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
);
BOOLEAN
F12GetProcIddMax (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN UINT8 Pstate,
OUT UINT32 *ProcIddMax,
IN AMD_CONFIG_PARAMS *StdHeader
);
UINT8
F12GetNumberOfPhysicalCores (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
F12ConvertEnabledBitsIntoCount (
OUT UINT8 *EnabledCoreCountPtr,
IN UINT8 FusedCoreCount,
IN UINT8 EnabledCores
)
{
UINT8 i;
UINT8 j;
UINT8 EnabledCoreCount;
EnabledCoreCount = 0;
for (i = 0; i < FusedCoreCount+1; i++) {
j = 1;
if (!((BOOLEAN) (EnabledCores) & (j << i))) {
EnabledCoreCount++;
}
}
*EnabledCoreCountPtr = EnabledCoreCount;
}
/*---------------------------------------------------------------------------------------*/
/**
* Disables the desired P-state.
*
* @CpuServiceMethod{::F_CPU_DISABLE_PSTATE}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] StateNumber The P-State to disable.
* @param[in] StdHeader Header for library and services
*
* @retval AGESA_SUCCESS Always succeeds.
*/
AGESA_STATUS
F12DisablePstate (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN UINT8 StateNumber,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 LocalMsrRegister;
ASSERT (StateNumber < NM_PS_REG);
LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &LocalMsrRegister, StdHeader);
((PSTATE_MSR *) &LocalMsrRegister)->PsEnable = 0;
LibAmdMsrWrite (PS_REG_BASE + (UINT32) StateNumber, &LocalMsrRegister, StdHeader);
return (AGESA_SUCCESS);
}
/*---------------------------------------------------------------------------------------*/
/**
* Transitions the executing core to the desired P-state.
*
* @CpuServiceMethod{::F_CPU_TRANSITION_PSTATE}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] StateNumber The new P-State to make effective.
* @param[in] WaitForTransition True if the caller wants the transition completed upon return.
* @param[in] StdHeader Header for library and services
*
* @retval AGESA_SUCCESS Always Succeeds
*/
AGESA_STATUS
F12TransitionPstate (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN UINT8 StateNumber,
IN BOOLEAN WaitForTransition,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 LocalMsrRegister;
LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &LocalMsrRegister, StdHeader);
ASSERT (((PSTATE_CURLIM_MSR *) &LocalMsrRegister)->PstateMaxVal >= StateNumber);
LibAmdMsrRead (MSR_PSTATE_CTL, &LocalMsrRegister, StdHeader);
((PSTATE_CTRL_MSR *) &LocalMsrRegister)->PstateCmd = (UINT64) StateNumber;
LibAmdMsrWrite (MSR_PSTATE_CTL, &LocalMsrRegister, StdHeader);
if (WaitForTransition) {
do {
LibAmdMsrRead (MSR_PSTATE_STS, &LocalMsrRegister, StdHeader);
} while (((PSTATE_STS_MSR *) &LocalMsrRegister)->CurPstate != (UINT64) StateNumber);
}
return (AGESA_SUCCESS);
}
/*---------------------------------------------------------------------------------------*/
/**
* Determines the rate at which the executing core's time stamp counter is
* incrementing.
*
* @CpuServiceMethod{::F_CPU_GET_TSC_RATE}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[out] FrequencyInMHz TSC actual frequency.
* @param[in] StdHeader Header for library and services.
*
* @return The most severe status of all called services
*/
AGESA_STATUS
F12GetTscRate (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT UINT32 *FrequencyInMHz,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 NumBoostStates;
UINT32 LocalPciRegister;
UINT64 LocalMsrRegister;
PCI_ADDR PciAddress;
PSTATE_CPU_FAMILY_SERVICES *FamilyServices;
LibAmdMsrRead (0xC0010015, &LocalMsrRegister, StdHeader);
if ((LocalMsrRegister & 0x01000000) != 0) {
FamilyServices = NULL;
GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (const VOID **) &FamilyServices, StdHeader);
ASSERT (FamilyServices != NULL);
PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
NumBoostStates = (UINT8) ((CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates;
return (FamilyServices->GetPstateFrequency (FamilyServices, NumBoostStates, FrequencyInMHz, StdHeader));
} else {
return (FamilySpecificServices->GetCurrentNbFrequency (FamilySpecificServices, FrequencyInMHz, StdHeader));
}
}
/*---------------------------------------------------------------------------------------*/
/**
* Determines the NB clock on the desired node.
*
* @CpuServiceMethod{::F_CPU_GET_NB_FREQ}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[out] FrequencyInMHz Northbridge clock frequency in MHz.
* @param[in] StdHeader Header for library and services
*
* @retval AGESA_SUCCESS Always succeeds.
*/
AGESA_STATUS
F12GetCurrentNbFrequency (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT UINT32 *FrequencyInMHz,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 LocalPciRegister;
UINT32 MainPllFid;
PCI_ADDR PciAddress;
PciAddress.AddressValue = CPTC0_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
MainPllFid = ((CLK_PWR_TIMING_CTRL_REGISTER *) &LocalPciRegister)->MainPllOpFreqId;
*FrequencyInMHz = ((MainPllFid + 0x10) * 100);
return (AGESA_SUCCESS);
}
/*---------------------------------------------------------------------------------------*/
/**
* Determines the NB clock on the desired node.
*
* @CpuServiceMethod{::F_CPU_GET_NB_PSTATE_INFO}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] PlatformConfig Platform profile/build option config structure.
* @param[in] PciAddress The segment, bus, and device numbers of the CPU in question.
* @param[in] NbPstate The NB P-state number to check.
* @param[out] FreqNumeratorInMHz The desired node's frequency numerator in megahertz.
* @param[out] FreqDivisor The desired node's frequency divisor.
* @param[out] VoltageInuV The desired node's voltage in microvolts.
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
* @retval TRUE NbPstate is valid
* @retval FALSE NbPstate is disabled or invalid
*/
BOOLEAN
F12GetNbPstateInfo (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN PCI_ADDR *PciAddress,
IN UINT32 NbPstate,
OUT UINT32 *FreqNumeratorInMHz,
OUT UINT32 *FreqDivisor,
OUT UINT32 *VoltageInuV,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 NbVid;
UINT32 LocalPciRegister;
UINT32 MainPllFreq;
BOOLEAN PstateIsValid;
PstateIsValid = FALSE;
if ((NbPstate == 0) || ((NbPstate == 1) && FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, PlatformConfig, StdHeader))) {
FamilySpecificServices->GetCurrentNbFrequency (FamilySpecificServices, &MainPllFreq, StdHeader);
*FreqNumeratorInMHz = (MainPllFreq * 4);
if (NbPstate == 0) {
PciAddress->Address.Function = FUNC_3;
PciAddress->Address.Register = CPTC2_REG;
LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader);
*FreqDivisor = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->NbPs0NclkDiv;
NbVid = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->NbPs0Vid;
} else {
PciAddress->Address.Function = FUNC_6;
PciAddress->Address.Register = NB_PSTATE_CFG_LOW_REG;
LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader);
*FreqDivisor = ((NB_PSTATE_CFG_LOW_REGISTER *) &LocalPciRegister)->NbPs1NclkDiv;
NbVid = ((NB_PSTATE_CFG_LOW_REGISTER *) &LocalPciRegister)->NbPs1Vid;
}
*VoltageInuV = (1550000 - (12500 * NbVid));
PstateIsValid = TRUE;
}
return PstateIsValid;
}
/*---------------------------------------------------------------------------------------*/
/**
* Is the Northbridge PState feature enabled?
*
* @CpuServiceMethod{::F_IS_NB_PSTATE_ENABLED}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] PlatformConfig Platform profile/build option config structure.
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
* @retval TRUE The NB PState feature is enabled.
* @retval FALSE The NB PState feature is not enabled.
*/
BOOLEAN
F12IsNbPstateEnabled (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 LocalPciRegister;
PCI_ADDR PciAddress;
PciAddress.AddressValue = NB_PSTATE_CFG_LOW_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
return ((BOOLEAN) (((NB_PSTATE_CFG_LOW_REGISTER *) &LocalPciRegister)->NbPsCap == 1));
}
/*---------------------------------------------------------------------------------------*/
/**
* Returns whether or not BIOS is responsible for configuring the NB COFVID.
*
* @CpuServiceMethod{::F_CPU_IS_NBCOF_INIT_NEEDED}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] PciAddress The northbridge to query by pci base address.
* @param[out] NbCofVidUpdateRequired TRUE, perform northbridge frequency and voltage config,
* FALSE, do not configure them.
* @param[in] StdHeader Header for library and services
*
* @retval AGESA_SUCCESS Always succeeds.
*/
AGESA_STATUS
F12GetNbCofVidUpdate (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN PCI_ADDR *PciAddress,
OUT BOOLEAN *NbCofVidUpdateRequired,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
*NbCofVidUpdateRequired = FALSE;
return (AGESA_SUCCESS);
}
/*---------------------------------------------------------------------------------------*/
/**
* Initially launches the desired core to run from the reset vector.
*
* @CpuServiceMethod{::F_CPU_AP_INITIAL_LAUNCH}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] SocketNum The Processor on which the core is to be launched
* @param[in] ModuleNum The Module in that processor containing that core
* @param[in] CoreNum The Core to launch
* @param[in] PrimaryCoreNum The id of the module's primary core.
* @param[in] StdHeader Header for library and services
*
* @retval TRUE The core was launched
* @retval FALSE The core was previously launched
*/
BOOLEAN
F12LaunchApCore (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN UINT32 SocketNum,
IN UINT32 ModuleNum,
IN UINT32 CoreNum,
IN UINT32 PrimaryCoreNum,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 NodeRelativeCoreNum;
UINT32 LocalPciRegister;
PCI_ADDR PciAddress;
BOOLEAN LaunchFlag;
// Code Start
LaunchFlag = FALSE;
NodeRelativeCoreNum = CoreNum - PrimaryCoreNum;
PciAddress.AddressValue = MAKE_SBDFO (0, 0, PCI_DEV_BASE, FUNC_0, 0);
switch (NodeRelativeCoreNum) {
case 1:
PciAddress.Address.Register = HT_TRANS_CTRL;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
if ((LocalPciRegister & HT_TRANS_CTRL_CPU1_EN) == 0) {
LocalPciRegister |= HT_TRANS_CTRL_CPU1_EN;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
LaunchFlag = TRUE;
} else {
LaunchFlag = FALSE;
}
break;
case 2:
PciAddress.Address.Register = ECS_HT_TRANS_CTRL;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
if ((LocalPciRegister & ECS_HT_TRANS_CTRL_CPU2_EN) == 0) {
LocalPciRegister |= ECS_HT_TRANS_CTRL_CPU2_EN;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister,
StdHeader);
LaunchFlag = TRUE;
} else {
LaunchFlag = FALSE;
}
break;
case 3:
PciAddress.Address.Register = ECS_HT_TRANS_CTRL;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
if ((LocalPciRegister & ECS_HT_TRANS_CTRL_CPU3_EN) == 0) {
LocalPciRegister |= ECS_HT_TRANS_CTRL_CPU3_EN;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
LaunchFlag = TRUE;
} else {
LaunchFlag = FALSE;
}
break;
default:
break;
}
return (LaunchFlag);
}
/*---------------------------------------------------------------------------------------*/
/**
* Get CPU Specific Platform Type Info.
*
* @CpuServiceMethod{::F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO}.
*
* This function returns Returns the platform features.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in,out] Features The Features supported by this platform.
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
* @retval AGESA_SUCCESS Always succeeds.
*/
AGESA_STATUS
F12GetPlatformTypeSpecificInfo (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN OUT PLATFORM_FEATS *Features,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
return (AGESA_SUCCESS);
}
/*---------------------------------------------------------------------------------------*/
/**
* Get CPU pstate current.
*
* @CpuServiceMethod{::F_CPU_GET_IDD_MAX}.
*
* This function returns the ProcIddMax.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] Pstate The P-state to check.
* @param[out] ProcIddMax P-state current in mA.
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
* @retval TRUE P-state is enabled
* @retval FALSE P-state is disabled
*/
BOOLEAN
F12GetProcIddMax (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN UINT8 Pstate,
OUT UINT32 *ProcIddMax,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 IddDiv;
UINT32 CmpCap;
UINT32 LocalPciRegister;
UINT32 MsrAddress;
UINT64 PstateMsr;
BOOLEAN IsPstateEnabled;
PCI_ADDR PciAddress;
IsPstateEnabled = FALSE;
MsrAddress = (UINT32) (Pstate + PS_REG_BASE);
ASSERT (MsrAddress <= PS_MAX_REG);
LibAmdMsrRead (MsrAddress, &PstateMsr, StdHeader);
if (((PSTATE_MSR *) &PstateMsr)->PsEnable == 1) {
PciAddress.AddressValue = NB_CAPS_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3xE8
CmpCap = (UINT32) (((NB_CAPS_REGISTER *) &LocalPciRegister)->CmpCap);
CmpCap++;
switch (((PSTATE_MSR *) &PstateMsr)->IddDiv) {
case 0:
IddDiv = 1000;
break;
case 1:
IddDiv = 100;
break;
case 2:
IddDiv = 10;
break;
default: // IddDiv = 3 is reserved. Use 10
ASSERT (FALSE);
IddDiv = 10;
break;
}
*ProcIddMax = (UINT32) ((PSTATE_MSR *) &PstateMsr)->IddValue * IddDiv * CmpCap;
IsPstateEnabled = TRUE;
}
return IsPstateEnabled;
}
/*---------------------------------------------------------------------------------------*/
/**
* Get the number of physical cores of current processor.
*
* @CpuServiceMethod{::F_CPU_NUMBER_OF_PHYSICAL_CORES}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
* @return The number of physical cores.
*/
UINT8
F12GetNumberOfPhysicalCores (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
CPUID_DATA CpuId;
//
//CPUID.80000008h.ECX.NC + 1, 000b = 1, 001b = 2, etc.
//
LibAmdCpuidRead (CPUID_LONG_MODE_ADDR, &CpuId, StdHeader);
return ((UINT8) ((CpuId.ECX_Reg & 0xff) + 1));
}

130
src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12Utilities.h
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@ -1,130 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_12 specific utility functions.
*
* Provides numerous utility functions specific to family 12h.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _CPU_F12_UTILITES_H_
#define _CPU_F12_UTILITES_H_
/*---------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*---------------------------------------------------------------------------------------
*/
AGESA_STATUS
F12DisablePstate (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN UINT8 StateNumber,
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
F12TransitionPstate (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN UINT8 StateNumber,
IN BOOLEAN WaitForTransition,
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
F12GetTscRate (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT UINT32 *FrequencyInMHz,
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
F12GetCurrentNbFrequency (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT UINT32 *FrequencyInMHz,
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
F12GetNbCofVidUpdate (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN PCI_ADDR *PciAddress,
OUT BOOLEAN *NbCofVidUpdateRequired,
IN AMD_CONFIG_PARAMS *StdHeader
);
BOOLEAN
F12LaunchApCore (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN UINT32 SocketNum,
IN UINT32 ModuleNum,
IN UINT32 CoreNum,
IN UINT32 PrimaryCoreNum,
IN AMD_CONFIG_PARAMS *StdHeader
);
CORE_ID_POSITION
F12CpuAmdCoreIdPositionInInitialApicId (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
F12GetPlatformTypeSpecificInfo (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN OUT PLATFORM_FEATS *Features,
IN AMD_CONFIG_PARAMS *StdHeader
);
#endif // _CPU_F12_UTILITES_H_

126
src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12WheaInitDataTables.c
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@ -1,126 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_12 WHEA initial Data
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuLateInit.h"
#include "cpuFamilyTranslation.h"
#include "Filecode.h"
CODE_GROUP (G3_DXE)
RDATA_GROUP (G3_DXE)
#define FILECODE PROC_CPU_FAMILY_0X12_CPUF12WHEAINITDATATABLES_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
GetF12WheaInitData (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **F12WheaInitDataPtr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
AMD_HEST_BANK_INIT_DATA F12HestBankInitData[] = {
{0xFFFFFFFF,0xFFFFFFFF,0x400,0x401,0x402,0x403},
{0xFFFFFFFF,0xFFFFFFFF,0x404,0x405,0x406,0x407},
{0xFFFFFFFF,0xFFFFFFFF,0x408,0x409,0x40A,0x40B},
{0xFFFFFFFF,0xFFFFFFFF,0x40C,0x40D,0x40E,0x40F},
{0xFFFFFFFF,0xFFFFFFFF,0x410,0x411,0x412,0x413},
{0xFFFFFFFF,0xFFFFFFFF,0x414,0x415,0x416,0x417},
};
AMD_WHEA_INIT_DATA F12WheaInitData = {
0x000000000, // AmdGlobCapInitDataLsd
0x000000000, // AmdGlobCapInitDataMsd
0x00000003F, // AmdGlobCtrlInitDataLsd
0x000000000, // AmdGlobCtrlInitDataMsd
0x00, // AmdMcbClrStatusOnInit
0x02, // AmdMcbStatusDataFormat
0x00, // AmdMcbConfWriteEn
(sizeof (F12HestBankInitData) / sizeof (F12HestBankInitData[0])), // HestBankNum
&F12HestBankInitData[0] // Pointer to Initial data of HEST Bank
};
/*---------------------------------------------------------------------------------------*/
/**
* Returns the family specific WHEA table properties.
*
* @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[out] F12WheaInitDataPtr Points to the family 12h WHEA properties.
* @param[out] NumberOfElements Will be one to indicate one structure.
* @param[in] StdHeader Header for library and services.
*
*/
VOID
GetF12WheaInitData (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **F12WheaInitDataPtr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
*NumberOfElements = 1;
*F12WheaInitDataPtr = &F12WheaInitData;
}

226
src/vendorcode/amd/agesa/f12/Proc/CPU/Family/cpuFamRegisters.h
View File

@ -1,226 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD CPU Register Table Related Functions
*
* Contains the definition of the CPU CPUID MSRs and PCI registers with BKDG recommended values
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU
* @e \$Revision: 45026 $ @e \$Date: 2011-01-12 05:00:20 +0800 (Wed, 12 Jan 2011) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _CPU_FAM_REGISTERS_H_
#define _CPU_FAM_REGISTERS_H_
/*
*--------------------------------------------------------------
*
* M O D U L E S U S E D
*
*---------------------------------------------------------------
*/
/*
*--------------------------------------------------------------
*
* D E F I N I T I O N S / M A C R O S
*
*---------------------------------------------------------------
*/
// This define should be equal to the total number of families
// in the cpuFamily enum.
#define MAX_CPU_FAMILIES 64
#define MAX_CPU_REVISIONS 63 // Max Cpu Revisions Per Family
// CPU_LOGICAL_ID.Family equates
// Family 10h equates
#define AMD_FAMILY_10_RB 0x0000000000000001ull
#define AMD_FAMILY_10_BL 0x0000000000000002ull
#define AMD_FAMILY_10_DA 0x0000000000000004ull
#define AMD_FAMILY_10_HY 0x0000000000000008ull
#define AMD_FAMILY_10_PH 0x0000000000000010ull
#define AMD_FAMILY_10_C32 AMD_FAMILY_10_HY
#define AMD_FAMILY_10 (AMD_FAMILY_10_RB | AMD_FAMILY_10_BL | AMD_FAMILY_10_DA | AMD_FAMILY_10_HY | AMD_FAMILY_10_PH)
#define AMD_FAMILY_GH (AMD_FAMILY_10)
// Family 12h equates
#define AMD_FAMILY_12_LN 0x0000000000000020ull
#define AMD_FAMILY_12 (AMD_FAMILY_12_LN)
#define AMD_FAMILY_LN (AMD_FAMILY_12_LN)
// Family 14h equates
#define AMD_FAMILY_14_ON 0x0000000000000040ull
#define AMD_FAMILY_14 (AMD_FAMILY_14_ON)
#define AMD_FAMILY_ON (AMD_FAMILY_14_ON)
// Family 15h equates
#define AMD_FAMILY_15_OR 0x0000000000000100ull
#define AMD_FAMILY_OR (AMD_FAMILY_15_OR)
#define AMD_FAMILY_15 (AMD_FAMILY_15_OR)
// Family 16h equates
#define AMD_FAMILY_16 0x0000000000000800ull
#define AMD_FAMILY_WF (AMD_FAMILY_16)
// Family Unknown
#define AMD_FAMILY_UNKNOWN 0x8000000000000000ull
// Family Group equates
#define AMD_FAMILY_GE_12 (AMD_FAMILY_12 | AMD_FAMILY_14 | AMD_FAMILY_15 | AMD_FAMILY_16)
// Family 10h CPU_LOGICAL_ID.Revision equates
// -------------------------------------
// Family 10h RB steppings
#define AMD_F10_RB_C0 0x0000000000000001ull
#define AMD_F10_RB_C1 0x0000000000000002ull
#define AMD_F10_RB_C2 0x0000000000000004ull
#define AMD_F10_RB_C3 0x0000000000000008ull
// Family 10h BL steppings
#define AMD_F10_BL_C2 0x0000000000000010ull
#define AMD_F10_BL_C3 0x0000000000000020ull
// Family 10h DA steppings
#define AMD_F10_DA_C2 0x0000000000000040ull
#define AMD_F10_DA_C3 0x0000000000000080ull
// Family 10h HY SCM steppings
#define AMD_F10_HY_SCM_D0 0x0000000000000100ull
#define AMD_F10_HY_SCM_D1 0x0000000000000400ull
// Family 10h HY MCM steppings
#define AMD_F10_HY_MCM_D0 0x0000000000000200ull
#define AMD_F10_HY_MCM_D1 0x0000000000000800ull
// Family 10h PH steppings
#define AMD_F10_PH_E0 0x0000000000001000ull
// Family 10h Unknown stepping
#define AMD_F10_UNKNOWN 0x8000000000000000ull
// Family 10h Miscellaneous equates
#define AMD_F10_C0 (AMD_F10_RB_C0)
#define AMD_F10_C1 (AMD_F10_RB_C1)
#define AMD_F10_C2 (AMD_F10_RB_C2 | AMD_F10_DA_C2 | AMD_F10_BL_C2)
#define AMD_F10_C3 (AMD_F10_RB_C3 | AMD_F10_DA_C3 | AMD_F10_BL_C3)
#define AMD_F10_Cx (AMD_F10_C0 | AMD_F10_C1 | AMD_F10_C2 | AMD_F10_C3)
#define AMD_F10_RB_ALL (AMD_F10_RB_C0 | AMD_F10_RB_C1 | AMD_F10_RB_C2 | AMD_F10_RB_C3)
#define AMD_F10_BL_ALL (AMD_F10_BL_C2 | AMD_F10_BL_C3)
#define AMD_F10_BL_Cx (AMD_F10_BL_C2 | AMD_F10_BL_C3)
#define AMD_F10_DA_ALL (AMD_F10_DA_C2 | AMD_F10_DA_C3)
#define AMD_F10_DA_Cx (AMD_F10_DA_C2 | AMD_F10_DA_C3)
#define AMD_F10_D0 (AMD_F10_HY_SCM_D0 | AMD_F10_HY_MCM_D0)
#define AMD_F10_D1 (AMD_F10_HY_SCM_D1 | AMD_F10_HY_MCM_D1)
#define AMD_F10_Dx (AMD_F10_D0 | AMD_F10_D1)
#define AMD_F10_PH_ALL (AMD_F10_PH_E0)
#define AMD_F10_Ex (AMD_F10_PH_E0)
#define AMD_F10_HY_ALL (AMD_F10_Dx)
#define AMD_F10_C32_ALL (AMD_F10_HY_SCM_D0 | AMD_F10_HY_SCM_D1)
#define AMD_F10_GT_B0 (AMD_F10_Cx | AMD_F10_Dx | AMD_F10_Ex)
#define AMD_F10_GT_Bx (AMD_F10_Cx | AMD_F10_Dx | AMD_F10_Ex)
#define AMD_F10_GT_A2 (AMD_F10_Cx | AMD_F10_Dx | AMD_F10_Ex)
#define AMD_F10_GT_Ax (AMD_F10_Cx | AMD_F10_Dx | AMD_F10_Ex)
#define AMD_F10_GT_C0 ((AMD_F10_Cx & ~AMD_F10_C0) | AMD_F10_Dx | AMD_F10_Ex)
#define AMD_F10_GT_D0 (AMD_F10_Dx & ~AMD_F10_D0 | AMD_F10_Ex)
#define AMD_F10_ALL (AMD_F10_Cx | AMD_F10_Dx | AMD_F10_Ex | AMD_F10_UNKNOWN)
// Family 12h CPU_LOGICAL_ID.Revision equates
// -------------------------------------
// Family 12h LN steppings
#define AMD_F12_LN_A0 0x0000000000000001ull
#define AMD_F12_LN_A1 0x0000000000000002ull
#define AMD_F12_LN_B0 0x0000000000000004ull
// Family 12h Unknown stepping
#define AMD_F12_UNKNOWN 0x8000000000000000ull
#define AMD_F12_LN_Ax (AMD_F12_LN_A0 | AMD_F12_LN_A1)
#define AMD_F12_LN_Bx (AMD_F12_LN_B0)
#define AMD_F12_ALL (AMD_F12_LN_Ax | AMD_F12_LN_Bx | AMD_F12_UNKNOWN)
// Family 14h CPU_LOGICAL_ID.Revision equates
// -------------------------------------
// Family 14h ON steppings
#define AMD_F14_ON_A0 0x0000000000000001ull
#define AMD_F14_ON_A1 0x0000000000000002ull
#define AMD_F14_ON_B0 0x0000000000000004ull
#define AMD_F14_ON_C0 0x0000000000000008ull
// Family 14h KR steppings
#define AMD_F14_KR_A0 0x0000000000000100ull
#define AMD_F14_KR_A1 0x0000000000000200ull
#define AMD_F14_KR_B0 0x0000000000000400ull
// Family 14h Unknown stepping
#define AMD_F14_UNKNOWN 0x8000000000000000ull
#define AMD_F14_ON_Ax (AMD_F14_ON_A0 | AMD_F14_ON_A1)
#define AMD_F14_ON_Bx (AMD_F14_ON_B0)
#define AMD_F14_ON_Cx (AMD_F14_ON_C0)
#define AMD_F14_ON_ALL (AMD_F14_ON_Ax | AMD_F14_ON_Bx | AMD_F14_ON_Cx)
#define AMD_F14_ALL (AMD_F14_ON_ALL | AMD_F14_UNKNOWN)
// Family 15h CPU_LOGICAL_ID.Revision equates
// -------------------------------------
// Family 15h OROCHI steppings
#define AMD_F15_OR_A0 0x0000000000000001ull
#define AMD_F15_OR_A1 0x0000000000000002ull
#define AMD_F15_OR_B0 0x0000000000000004ull
// Family 15h TN steppings
#define AMD_F15_TN_A0 0x0000000000000100ull
// Family 15h Unknown stepping
#define AMD_F15_UNKNOWN 0x8000000000000000ull
#define AMD_F15_OR_Ax (AMD_F15_OR_A0 | AMD_F15_OR_A1)
#define AMD_F15_OR_Bx AMD_F15_OR_B0
#define AMD_F15_OR_GT_Ax (AMD_F15_OR_Bx)
#define AMD_F15_OR_LT_B1 (AMD_F15_OR_Ax | AMD_F15_OR_B0)
#define AMD_F15_OR_ALL (AMD_F15_OR_Ax | AMD_F15_OR_Bx)
#define AMD_F15_ALL (AMD_F15_OR_ALL | AMD_F15_UNKNOWN)
// Family 16h CPU_LOGICAL_ID.Revision equates
// TBD
#endif // _CPU_FAM_REGISTERS_H_

20
src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/Makefile.inc
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@ -1,20 +0,0 @@
libagesa-y += PreserveMailbox.c
libagesa-y += cpuC6State.c
libagesa-y += cpuCacheFlushOnHalt.c
libagesa-y += cpuCacheInit.c
libagesa-y += cpuCoreLeveling.c
libagesa-y += cpuCpb.c
libagesa-y += cpuDmi.c
libagesa-y += cpuFeatureLeveling.c
libagesa-y += cpuFeatures.c
libagesa-y += cpuHwC1e.c
libagesa-y += cpuIoCstate.c
libagesa-y += cpuL3Features.c
libagesa-y += cpuLowPwrPstate.c
libagesa-y += cpuPstateGather.c
libagesa-y += cpuPstateLeveling.c
libagesa-y += cpuPstateTables.c
libagesa-y += cpuSlit.c
libagesa-y += cpuSrat.c
libagesa-y += cpuSwC1e.c
libagesa-y += cpuWhea.c

218
src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/PreserveMailbox.c
View File

@ -1,218 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD AGESA CPU Preserve Registers used for AP Mailbox.
*
* Save and Restore the normal feature content of the registers being used for
* the AP Mailbox.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Feature
* @e \$Revision: 50096 $ @e \$Date: 2011-04-02 06:17:10 +0800 (Sat, 02 Apr 2011) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "Topology.h"
#include "GeneralServices.h"
#include "OptionMultiSocket.h"
#include "cpuRegisters.h"
#include "cpuApicUtilities.h"
#include "cpuServices.h"
#include "cpuFamilyTranslation.h"
#include "cpuFeatures.h"
#include "PreserveMailbox.h"
#include "heapManager.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_CPU_FEATURE_PRESERVEMAILBOX_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
extern CPU_FAMILY_SUPPORT_TABLE PreserveMailboxFamilyServiceTable;
/*---------------------------------------------------------------------------------------*/
/**
* The contents of the mailbox registers should always be preserved.
*
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] StdHeader Config Handle for library, services.
*
* @retval TRUE Always TRUE
*
*/
BOOLEAN
STATIC
IsPreserveAroundMailboxEnabled (
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
return TRUE;
}
/*---------------------------------------------------------------------------------------*/
/**
* Save and Restore or Initialize the content of the mailbox registers.
*
* The registers used for AP mailbox should have the content related to their function
* preserved.
*
* @param[in] EntryPoint Timepoint designator.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] StdHeader Config Handle for library, services.
*
* @return AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
PreserveMailboxes (
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
PRESERVE_MAILBOX_FAMILY_SERVICES *FamilySpecificServices;
UINT32 Socket;
UINT32 Module;
PCI_ADDR BaseAddress;
PCI_ADDR MailboxRegister;
PRESERVE_MAILBOX_FAMILY_REGISTER *NextRegister;
AGESA_STATUS IgnoredStatus;
AGESA_STATUS HeapStatus;
UINT32 Value;
ALLOCATE_HEAP_PARAMS AllocateParams;
LOCATE_HEAP_PTR LocateParams;
UINT32 RegisterEntryIndex;
BaseAddress.AddressValue = ILLEGAL_SBDFO;
if (EntryPoint == CPU_FEAT_AFTER_COHERENT_DISCOVERY) {
// The save step. Save either the register content or zero (for cold boot, if family specifies that).
AllocateParams.BufferHandle = PRESERVE_MAIL_BOX_HANDLE;
AllocateParams.RequestedBufferSize = (sizeof (UINT32) * (MAX_PRESERVE_REGISTER_ENTRIES * (MAX_SOCKETS * MAX_DIES)));
AllocateParams.Persist = HEAP_SYSTEM_MEM;
HeapStatus = HeapAllocateBuffer (&AllocateParams, StdHeader);
ASSERT ((HeapStatus == AGESA_SUCCESS) && (AllocateParams.BufferPtr != NULL));
LibAmdMemFill (AllocateParams.BufferPtr, 0xFF, AllocateParams.RequestedBufferSize, StdHeader);
RegisterEntryIndex = 0;
for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
if (GetPciAddress (StdHeader, Socket, Module, &BaseAddress, &IgnoredStatus)) {
GetFeatureServicesOfSocket (&PreserveMailboxFamilyServiceTable, Socket, (const VOID **)&FamilySpecificServices, StdHeader);
ASSERT (FamilySpecificServices != NULL);
NextRegister = FamilySpecificServices->RegisterList;
while (NextRegister->Register.AddressValue != ILLEGAL_SBDFO) {
ASSERT (RegisterEntryIndex <
(MAX_PRESERVE_REGISTER_ENTRIES * GetPlatformNumberOfSockets () * GetPlatformNumberOfModules ()));
if (FamilySpecificServices->IsZeroOnCold && (!IsWarmReset (StdHeader))) {
Value = 0;
} else {
MailboxRegister = BaseAddress;
MailboxRegister.Address.Function = NextRegister->Register.Address.Function;
MailboxRegister.Address.Register = NextRegister->Register.Address.Register;
LibAmdPciRead (AccessWidth32, MailboxRegister, &Value, StdHeader);
Value &= NextRegister->Mask;
}
(* (MAILBOX_REGISTER_SAVE_ENTRY) AllocateParams.BufferPtr) [RegisterEntryIndex] = Value;
RegisterEntryIndex++;
NextRegister++;
}
}
}
}
} else if ((EntryPoint == CPU_FEAT_INIT_LATE_END) || (EntryPoint == CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) {
// The restore step. Just write out the saved content in the buffer.
LocateParams.BufferHandle = PRESERVE_MAIL_BOX_HANDLE;
HeapStatus = HeapLocateBuffer (&LocateParams, StdHeader);
ASSERT ((HeapStatus == AGESA_SUCCESS) && (LocateParams.BufferPtr != NULL));
RegisterEntryIndex = 0;
for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
if (GetPciAddress (StdHeader, Socket, Module, &BaseAddress, &IgnoredStatus)) {
GetFeatureServicesOfSocket (&PreserveMailboxFamilyServiceTable, Socket, (const VOID **)&FamilySpecificServices, StdHeader);
NextRegister = FamilySpecificServices->RegisterList;
while (NextRegister->Register.AddressValue != ILLEGAL_SBDFO) {
ASSERT (RegisterEntryIndex <
(MAX_PRESERVE_REGISTER_ENTRIES * GetPlatformNumberOfSockets () * GetPlatformNumberOfModules ()));
MailboxRegister = BaseAddress;
MailboxRegister.Address.Function = NextRegister->Register.Address.Function;
MailboxRegister.Address.Register = NextRegister->Register.Address.Register;
LibAmdPciRead (AccessWidth32, MailboxRegister, &Value, StdHeader);
Value = ((Value & ~NextRegister->Mask) | (* (MAILBOX_REGISTER_SAVE_ENTRY) LocateParams.BufferPtr) [RegisterEntryIndex]);
LibAmdPciWrite (AccessWidth32, MailboxRegister, &Value, StdHeader);
RegisterEntryIndex++;
NextRegister++;
}
}
}
}
HeapStatus = HeapDeallocateBuffer (PRESERVE_MAIL_BOX_HANDLE, StdHeader);
}
return AGESA_SUCCESS;
}
CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeaturePreserveAroundMailbox =
{
PreserveAroundMailbox,
(CPU_FEAT_AFTER_COHERENT_DISCOVERY | CPU_FEAT_INIT_LATE_END | CPU_FEAT_AFTER_RESUME_MTRR_SYNC),
IsPreserveAroundMailboxEnabled,
PreserveMailboxes
};

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