From a129f8f2fe41dcb1ffbedb062818c2f1664dea1f Mon Sep 17 00:00:00 2001
From: Tim Crawford <tcrawford@system76.com>
Date: Fri, 11 Aug 2023 13:21:04 -0600
Subject: [PATCH] soc/intel/alderlake: add GPIO definitions for RPL PCH

The RPL PCH uses a different ACPI Device ID than ADL PCH.

Ref: Intel 700 Series Chipset Family PCH Datasheet, Volume 1 (#743835)
Change-Id: I03f47a43ff985213ad617e834db7f974f687d877
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
---
 src/soc/intel/alderlake/include/soc/gpio.h | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/alderlake/include/soc/gpio.h b/src/soc/intel/alderlake/include/soc/gpio.h
index 14338e9024..1cea6cc766 100644
--- a/src/soc/intel/alderlake/include/soc/gpio.h
+++ b/src/soc/intel/alderlake/include/soc/gpio.h
@@ -3,7 +3,11 @@
 #ifndef _SOC_ALDERLAKE_GPIO_H_
 #define _SOC_ALDERLAKE_GPIO_H_
 
-#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)
+#if CONFIG(SOC_INTEL_RAPTORLAKE) && CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)
+#include <soc/gpio_defs_pch_s.h>
+#define CROS_GPIO_NAME		"INTC1085"
+#define CROS_GPIO_DEVICE_NAME	"INTC1085:00"
+#elif CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)
 #include <soc/gpio_defs_pch_s.h>
 #define CROS_GPIO_NAME		"INTC1056"
 #define CROS_GPIO_DEVICE_NAME	"INTC1056:00"