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i945.h: Add some more comments, align data for better readability (trivial).

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Also, add missing C1DRA2 #define (as per public datasheet).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3738 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann
2008-11-09 10:57:26 +00:00
parent 160361a1df
commit a163729862
1 changed files with 23 additions and 22 deletions
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21
src/northbridge/intel/i945/i945.h
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@@ -31,15 +31,15 @@
#define X60BAR 0x60
/* Northbridge BARs */
#define DEFAULT_PCIEXBAR 0xf0000000
#define DEFAULT_PCIEXBAR 0xf0000000 /* 4 KB per PCIe device */
#define DEFAULT_X60BAR 0xfed13000
#define DEFAULT_MCHBAR 0xfed14000
#define DEFAULT_DMIBAR 0xfed18000
#define DEFAULT_EPBAR 0xfed19000
#define DEFAULT_MCHBAR 0xfed14000 /* 16 KB */
#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */
#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
#define GGC 0x52
#define GGC 0x52 /* GMCH Graphics Control */
#define DEVEN 0x54
#define DEVEN 0x54 /* Device Enable */
#define DEVEN_D0F0 (1 << 0)
#define DEVEN_D1F0 (1 << 1)
#define DEVEN_D2F0 (1 << 3)
@@ -58,12 +58,12 @@
#define LAC 0x97 /* Legacy Access Control */
#define TOLUD 0x9c /* Top of Low Used Memory */
#define SMRAM 0x9d
#define ESMRAM 0x9e
#define SMRAM 0x9d /* System Management RAM Control */
#define ESMRAM 0x9e /* Extended System Management RAM Control */
#define TOM 0xa0
#define SKPAD 0xdc /* Scratchpad */
#define SKPAD 0xdc /* Scratchpad Data */
/* Device 0:1.0 PCI configuration space (PCI Express) */
@@ -72,7 +72,7 @@
/* Device 0:2.0 PCI configuration space (Graphics Device) */
#define GCFC 0xf0 /* Graphics Clock Frequency and Gating Control */
#define GCFC 0xf0 /* Graphics Clock Frequency & Gating Control */
/*
@@ -119,6 +119,7 @@
#define C1DRB2 0x182 /* 8bit */
#define C1DRB3 0x183 /* 8bit */
#define C1DRA0 0x188 /* 8bit */
#define C1DRA2 0x189 /* 8bit */
#define C1DCLKDIS 0x18c /* 8bit */
#define C1BNKARC 0x18e /* 16bit */
#define C1DRT0 0x190 /* 32bit */