soc/intel/{skl,cnl}: replace PM ACPI timer dt option by Kconfig

Select `PM_ACPI_TIMER_OPTIONAL` to enable the new PM ACPI Kconfig and
set the FSP option for PM ACPI timer enablement from its value instead
of using the old devicetree option.

Also drop the obsolete devicetree option from soc code and from the
mainboards and add a corresponding Kconfig entry instead.

Change-Id: I10724ccf1647594404cec15c2349ab05b6c9714f
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45955
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/intel/kblrvp/Kconfig

@@ -84,4 +84,9 @@ config DIMM_SPD_SIZE
 config UART_FOR_CONSOLE
 	int
 	default 2
+
+config USE_PM_ACPI_TIMER
+	default n if BOARD_INTEL_KBLRVP3
+	default n if BOARD_INTEL_KBLRVP7
+
 endif

src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb

@@ -3,7 +3,6 @@ chip soc/intel/skylake
 	# FSP Configuration
 	register "DspEnable" = "0"
 	register "ScsEmmcHs400Enabled" = "0"
-	register "PmTimerDisabled" = "0"
 
 	register "serirq_mode" = "SERIRQ_CONTINUOUS"
 

src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb

@@ -8,7 +8,6 @@ chip soc/intel/skylake
 
 	# FSP Configuration
 	register "DspEnable" = "1"
-	register "PmTimerDisabled" = "1"
 
 	# VR Settings Configuration for 4 Domains
 	#+----------------+-------+-------+-------+-------+

src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb

@@ -12,9 +12,6 @@ chip soc/intel/skylake
 	# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
 	register "gen2_dec" = "0x000c0201"
 
-	# FSP Configuration
-	register "PmTimerDisabled" = "1"
-
 	# VR Settings Configuration for 4 Domains
 	#+----------------+-------+-------+-------+-------+
 	#| Domain/Setting |  SA   |  IA   | GTUS  |  GTS  |

src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb

@@ -6,7 +6,6 @@ chip soc/intel/skylake
 
 	# FSP Configuration
 	register "ScsEmmcHs400Enabled" = "0"
-	register "PmTimerDisabled" = "0"
 
 	register "serirq_mode" = "SERIRQ_CONTINUOUS"
 

src/mainboard/intel/kunimitsu/Kconfig

@@ -60,4 +60,8 @@ config INCLUDE_NHLT_BLOBS
 config UART_FOR_CONSOLE
 	int
 	default 2
+
+config USE_PM_ACPI_TIMER
+	default n
+
 endif

src/mainboard/intel/kunimitsu/devicetree.cb

@@ -27,7 +27,6 @@ chip soc/intel/skylake
 	register "SkipExtGfxScan" = "1"
 	register "HeciEnabled" = "0"
 	register "SaGv" = "SaGv_Enabled"
-	register "PmTimerDisabled" = "1"
 
 	# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
 	# SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s

src/mainboard/intel/saddlebrook/devicetree.cb

@@ -21,7 +21,6 @@ chip soc/intel/skylake
 	register "SkipExtGfxScan" = "1"
 
 	register "SaGv" = "SaGv_Enabled"
-	register "PmTimerDisabled" = "0"
 
 	# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
 	# SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s