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intel/apollolake: Enable prefetching and caching for BIOS reads

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Change-Id: I6afcc17ec8511d3fd4c1ac3b15d523d9b6752120
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15321
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
This commit is contained in:
Furquan Shaikh 2016-06-22 14:00:09 -07:00
parent f359997f86
commit a1850bafbf
2 changed files with 10 additions and 4 deletions
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9
src/soc/intel/apollolake/include/soc/spi.h
View File

@ -19,14 +19,15 @@
/* PCI configuration registers */ /* PCI configuration registers */
#define SPIBAR_BIOS_CONTROL 0xdc #define SPIBAR_BIOS_CONTROL 0xdc
/* Bit definitions for BIOS_CONTROL */
#define SPIBAR_BIOS_CONTROL_WPD (1 << 0)
#define SPIBAR_BIOS_CONTROL_CACHE_DISABLE (1 << 2)
#define SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE (1 << 3)
#define SPIBAR_BIOS_CONTROL_EISS (1 << 5)
/* Maximum bytes of data that can fit in FDATAn registers */ /* Maximum bytes of data that can fit in FDATAn registers */
#define SPIBAR_FDATA_FIFO_SIZE 0x40 #define SPIBAR_FDATA_FIFO_SIZE 0x40
/* Bit definitions for BIOS_CONTROL */
#define SPIBAR_BIOS_CONTROL_WPD (1 << 0)
#define SPIBAR_BIOS_CONTROL_EISS (1 << 5)
/* Register offsets from the MMIO region base (PCI_BASE_ADDRESS_0) */ /* Register offsets from the MMIO region base (PCI_BASE_ADDRESS_0) */
#define SPIBAR_BIOS_BFPREG 0x00 #define SPIBAR_BIOS_BFPREG 0x00
#define SPIBAR_HSFSTS_CTL 0x04 #define SPIBAR_HSFSTS_CTL 0x04

5
src/soc/intel/apollolake/spi.c
View File

@ -203,6 +203,11 @@ void spi_init(void)
bios_ctl = pci_read_config32(ctx->pci_dev, SPIBAR_BIOS_CONTROL); bios_ctl = pci_read_config32(ctx->pci_dev, SPIBAR_BIOS_CONTROL);
bios_ctl |= SPIBAR_BIOS_CONTROL_WPD; bios_ctl |= SPIBAR_BIOS_CONTROL_WPD;
bios_ctl &= ~SPIBAR_BIOS_CONTROL_EISS; bios_ctl &= ~SPIBAR_BIOS_CONTROL_EISS;
/* Enable Prefetching and caching. */
bios_ctl |= SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE;
bios_ctl &= ~SPIBAR_BIOS_CONTROL_CACHE_DISABLE;
pci_write_config32(ctx->pci_dev, SPIBAR_BIOS_CONTROL, bios_ctl); pci_write_config32(ctx->pci_dev, SPIBAR_BIOS_CONTROL, bios_ctl);
} }