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AGESA fam12 fam14 fam15: Use common agesa_readSpd()

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Remove northbridge specific callouts for AGESA_READ_SPD.

Move low-level SMBus code to southbridge.

Change-Id: I5fc91c49d9ef8e0af1c4d8194f857c61ce417d1d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7113
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
Kyösti Mälkki
2014-10-17 22:33:22 +03:00
parent c5cc9f233c
commit a1ebbc42ad
33 changed files with 559 additions and 636 deletions
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2
src/southbridge/amd/cimx/sb700/Makefile.inc
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@@ -21,7 +21,7 @@
# SB700 Platform Files
romstage-y += early.c
romstage-y += smbus.c
romstage-y += smbus.c smbus_spd.c
romstage-y += reset.c
ramstage-y += late.c

164
src/southbridge/amd/cimx/sb700/smbus_spd.c Normal file
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@@ -0,0 +1,164 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <device/pci_def.h>
#include <device/device.h>
#include <stdlib.h>
#include "OEM.h" /* SMBUS0_BASE_ADDRESS */
/* warning: Porting.h includes an open #pragma pack(1) */
#include "Porting.h"
#include "AGESA.h"
#include "amdlib.h"
#include "chip.h"
#include "smbus_spd.h"
#include <northbridge/amd/agesa/dimmSpd.h>
/* uncomment for source level debug - GDB gets really confused otherwise. */
//#pragma optimize ("", off)
/**
* Read a single SPD byte. If the first byte is being read, set up the
* address and offset. Following bytes auto increment.
*/
static UINT8 readSmbusByte(UINT16 iobase, UINT8 address, char *buffer,
int offset, int initial_offset)
{
unsigned int status = -1;
UINT64 time_limit;
/* clear status register */
__outbyte(iobase + SMBUS_STATUS_REG, 0xFF);
__outbyte(iobase + SMBUS_SLAVE_STATUS_REG, 0x1F);
if (offset == initial_offset) {
/* Set offset, set slave address and start reading */
__outbyte(iobase + SMBUS_CONTROL_REG, offset);
__outbyte(iobase + SMBUS_HOST_CMD_REG, address | READ_BIT);
__outbyte(iobase + SMBUS_COMMAND_REG, SMBUS_READ_BYTE_COMMAND);
} else {
/* Issue read command - auto increments to next byte */
__outbyte(iobase + SMBUS_COMMAND_REG, SMBUS_READ_COMMAND);
}
/* time limit to avoid hanging for unexpected error status */
time_limit = __rdtsc() + MAX_READ_TSC_COUNT;
while (__rdtsc() <= time_limit) {
status = __inbyte(iobase + SMBUS_STATUS_REG);
if ((status & SMBUS_INTERRUPT_MASK) == 0)
continue; /* SMBusInterrupt not set, keep waiting */
if ((status & HOSTBUSY_MASK) != 0)
continue; /* HostBusy set, keep waiting */
break;
}
if (status != STATUS__COMPLETED_SUCCESSFULLY)
return AGESA_ERROR;
buffer[0] = __inbyte(iobase + SMBUS_DATA0_REG);
return AGESA_SUCCESS;
}
/**
* Write a single smbus byte.
*/
UINT8 writeSmbusByte(UINT16 iobase, UINT8 address, UINT8 buffer,
int offset)
{
unsigned int status = -1;
UINT64 time_limit;
/* clear status register */
__outbyte(iobase + SMBUS_STATUS_REG, 0xFF);
__outbyte(iobase + SMBUS_SLAVE_STATUS_REG, 0x1F);
/* set offset, set slave address, set data and start writing */
__outbyte(iobase + SMBUS_CONTROL_REG, offset);
__outbyte(iobase + SMBUS_HOST_CMD_REG, address & (~READ_BIT));
__outbyte(iobase + SMBUS_DATA0_REG, buffer);
__outbyte(iobase + SMBUS_COMMAND_REG, SMBUS_WRITE_BYTE_COMMAND);
/* time limit to avoid hanging for unexpected error status */
time_limit = __rdtsc() + MAX_READ_TSC_COUNT;
while (__rdtsc() <= time_limit) {
status = __inbyte(iobase + SMBUS_STATUS_REG);
if ((status & SMBUS_INTERRUPT_MASK) == 0)
continue; /* SMBusInterrupt not set, keep waiting */
if ((status & HOSTBUSY_MASK) != 0)
continue; /* HostBusy set, keep waiting */
break;
}
if (status != STATUS__COMPLETED_SUCCESSFULLY)
return AGESA_ERROR;
return AGESA_SUCCESS;
}
static void setupFch(UINT16 ioBase)
{
AMD_CONFIG_PARAMS StdHeader;
UINT32 PciData32;
UINT8 PciData8;
PCI_ADDR PciAddress;
/* Set SMBus MMIO. */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0x90);
PciData32 = (ioBase & 0xFFFFFFF0) | BIT0;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData32, &StdHeader);
/* Enable SMBus MMIO. */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0xD2);
LibAmdPciRead(AccessWidth8, PciAddress, &PciData8, &StdHeader); ;
PciData8 |= BIT0;
LibAmdPciWrite(AccessWidth8, PciAddress, &PciData8, &StdHeader);
/* Set SMBus clock to 400 KHz */
__outbyte(ioBase + SMBUS_CLOCK_REG, SMBUS_FREQUENCY_CONST / 400000);
}
/**
* Read one or more SPD bytes from a DIMM.
* Start with offset zero and read sequentially.
* Reads 128 bytes in 7-8 ms at 400 KHz.
*/
static UINT8 readspd(UINT16 iobase, UINT8 SmbusSlaveAddress, char *buffer,
UINT16 count)
{
UINT16 index;
UINT8 status;
UINT8 initial_offset = 0;
setupFch(iobase);
for (index = initial_offset; index < count; index++) {
status = readSmbusByte(iobase, SmbusSlaveAddress, &buffer[index], index,
initial_offset);
if (status != AGESA_SUCCESS)
return status;
}
return status;
}
int smbus_readSpd(int spdAddress, char *buf, size_t len)
{
int ioBase = SMBUS0_BASE_ADDRESS;
setupFch (ioBase);
return readspd (ioBase, spdAddress, buf, len);
}

65
src/southbridge/amd/cimx/sb700/smbus_spd.h Normal file
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@@ -0,0 +1,65 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA02110-1301 USA
*/
#ifndef _SMBUS_SPD_H_
#define _SMBUS_SPD_H_
#define READ_BIT 0x01
#define SMBUS_INTERRUPT_MASK 0x02
#define HOSTBUSY_MASK 0x01
#define SMBUS_READ_BYTE_COMMAND 0x48
#define SMBUS_READ_COMMAND 0x44
#define SMBUS_WRITE_BYTE_COMMAND 0x48
#define MAX_READ_TSC_COUNT (2000000000 / 10)
#define PMIO_INDEX_REG 0xCD6
#define PMIO_DATA_REG 0xCD7
#define SMBUS_BAR_LOW_BYTE 0x2C
#define SMBUS_BAR_HIGH_BYTE 0x2D
#define SMBUS_STATUS_REG 0x00
#define SMBUS_SLAVE_STATUS_REG 0x01
#define SMBUS_COMMAND_REG 0x02
#define SMBUS_CONTROL_REG 0x03
#define SMBUS_HOST_CMD_REG 0x04
#define SMBUS_DATA0_REG 0x05
#define SMBUS_CLOCK_REG 0x0E
#define STATUS__COMPLETED_SUCCESSFULLY 0x02
#define SMBUS_FREQUENCY_CONST 66000000 / 4
/*
* This function prototype is only used by the AMD Dinar mainboard. The SMBus
* write is used to select which socket's SPD will be read by the subsequent
* SPD read call. This function is being placed in the F15 wrapper code with
* the other SPD read functions because the next step of the SPD read clean-up
* will be to move the SMBus read/write functions into the southbridge to make
* them more generic. Having the writeSmbusByte() function in the same file as
* the readSmbusByte() function will ensure that the writeSmbusByte() function
* is not overlooked.
*/
UINT8 writeSmbusByte(UINT16 iobase, UINT8 address, UINT8 buffer, int offset);
#endif

2
src/southbridge/amd/cimx/sb800/Makefile.inc
View File

@@ -22,7 +22,7 @@
romstage-y += cfg.c
romstage-y += early.c
romstage-y += smbus.c
romstage-y += smbus.c smbus_spd.c
romstage-y += reset.c
ramstage-y += cfg.c

123
src/southbridge/amd/cimx/sb800/smbus_spd.c Normal file
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@@ -0,0 +1,123 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <device/pci_def.h>
#include <device/device.h>
#include <stdlib.h>
#include "OEM.h" /* SMBUS0_BASE_ADDRESS */
/* warning: Porting.h includes an open #pragma pack(1) */
#include "Porting.h"
#include "AGESA.h"
#include "chip.h"
#include "smbus_spd.h"
#include <northbridge/amd/agesa/dimmSpd.h>
/* uncomment for source level debug - GDB gets really confused otherwise. */
//#pragma optimize ("", off)
/**
* Read a single SPD byte. If the first byte is being read, set up the
* address and offset. Following bytes auto increment.
*/
static UINT8 readSmbusByte(UINT16 iobase, UINT8 address, char *buffer,
int offset, int initial_offset)
{
unsigned int status = -1;
UINT64 time_limit;
/* clear status register */
__outbyte(iobase + SMBUS_STATUS_REG, 0x1E);
if (offset == initial_offset) {
/* Clear slave status, set offset, set slave address and start reading */
__outbyte(iobase + SMBUS_SLAVE_STATUS_REG, 0x3E);
__outbyte(iobase + SMBUS_CONTROL_REG, offset);
__outbyte(iobase + SMBUS_HOST_CMD_REG, address | READ_BIT);
__outbyte(iobase + SMBUS_COMMAND_REG, SMBUS_READ_BYTE_COMMAND);
} else {
/* Issue read command - auto increments to next byte */
__outbyte(iobase + SMBUS_COMMAND_REG, SMBUS_READ_COMMAND);
}
/* time limit to avoid hanging for unexpected error status */
time_limit = __rdtsc() + MAX_READ_TSC_COUNT;
while (__rdtsc() <= time_limit) {
status = __inbyte(iobase + SMBUS_STATUS_REG);
if ((status & SMBUS_INTERRUPT_MASK) == 0)
continue; /* SMBusInterrupt not set, keep waiting */
if ((status & HOSTBUSY_MASK) != 0)
continue; /* HostBusy set, keep waiting */
break;
}
if (status != STATUS__COMPLETED_SUCCESSFULLY)
return AGESA_ERROR;
buffer[0] = __inbyte(iobase + SMBUS_DATA0_REG);
return AGESA_SUCCESS;
}
static void writePmReg(UINT8 reg, UINT8 data)
{
__outbyte(PMIO_INDEX_REG, reg);
__outbyte(PMIO_DATA_REG, data);
}
static void setupFch(UINT16 ioBase)
{
/* set up SMBUS - Set to SMBUS 0 & set base address */
/* For SB800 & Hudson1 to SB900 & Hudson 2/3 */
writePmReg(SMBUS_BAR_HIGH_BYTE, ioBase >> 8);
writePmReg(SMBUS_BAR_LOW_BYTE, (ioBase & 0xe0) | 1);
/* set SMBus clock to 400 KHz */
__outbyte(ioBase + SMBUS_CLOCK_REG, SMBUS_FREQUENCY_CONST / 400000);
}
/**
* Read one or more SPD bytes from a DIMM.
* Start with offset zero and read sequentially.
* Reads 128 bytes in 7-8 ms at 400 KHz.
*/
static UINT8 readspd(UINT16 iobase, UINT8 SmbusSlaveAddress, char *buffer,
UINT16 count)
{
UINT16 index;
UINT8 status;
UINT8 initial_offset = 0;
setupFch(iobase);
for (index = initial_offset; index < count; index++) {
status = readSmbusByte(iobase, SmbusSlaveAddress, &buffer[index], index,
initial_offset);
if (status != AGESA_SUCCESS)
return status;
}
return status;
}
int smbus_readSpd(int spdAddress, char *buf, size_t len)
{
int ioBase = SMBUS0_BASE_ADDRESS;
setupFch (ioBase);
return readspd (ioBase, spdAddress, buf, len);
}

51
src/southbridge/amd/cimx/sb800/smbus_spd.h Normal file
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@@ -0,0 +1,51 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA02110-1301 USA
*/
#ifndef _SMBUS_SPD_H_
#define _SMBUS_SPD_H_
#define READ_BIT 0x01
#define SMBUS_INTERRUPT_MASK 0x02
#define HOSTBUSY_MASK 0x01
#define SMBUS_READ_BYTE_COMMAND 0x48
#define SMBUS_READ_COMMAND 0x44
#define MAX_READ_TSC_COUNT (2000000000 / 10)
#define PMIO_INDEX_REG 0xCD6
#define PMIO_DATA_REG 0xCD7
#define SMBUS_BAR_LOW_BYTE 0x2C
#define SMBUS_BAR_HIGH_BYTE 0x2D
#define SMBUS_STATUS_REG 0x00
#define SMBUS_SLAVE_STATUS_REG 0x01
#define SMBUS_COMMAND_REG 0x02
#define SMBUS_CONTROL_REG 0x03
#define SMBUS_HOST_CMD_REG 0x04
#define SMBUS_DATA0_REG 0x05
#define SMBUS_CLOCK_REG 0x0E
#define STATUS__COMPLETED_SUCCESSFULLY 0x02
#define SMBUS_FREQUENCY_CONST 66000000 / 4
#endif

2
src/southbridge/amd/cimx/sb900/Makefile.inc
View File

@@ -22,7 +22,7 @@
romstage-y += cfg.c
romstage-y += early.c
romstage-y += smbus.c
romstage-y += smbus.c smbus_spd.c
romstage-y += reset.c
ramstage-y += cfg.c

177
src/southbridge/amd/cimx/sb900/smbus_spd.c Normal file
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@@ -0,0 +1,177 @@
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#include "Porting.h"
#include "AGESA.h"
#include "amdlib.h"
#include <northbridge/amd/agesa/dimmSpd.h>
#define SMBUS_BASE_ADDR 0xB00
STATIC
VOID
WritePmReg (
IN UINT8 Reg,
IN UINT8 Data
)
{
__outbyte (0xCD6, Reg);
__outbyte (0xCD7, Data);
}
STATIC
VOID
SetupFch (
IN UINT16
IN IoBase
)
{
WritePmReg (0x2D, IoBase >> 8);
WritePmReg (0x2C, IoBase | 1);
WritePmReg (0x29, 0x80);
WritePmReg (0x28, 0x61);
/* set SMBus clock to 400 KHz */
__outbyte (IoBase + 0x0E, 66000000 / 400000 / 4);
}
/*
*
* ReadSmbusByteData - read a single SPD byte from any offset
*
*/
STATIC
AGESA_STATUS
ReadSmbusByteData (
IN UINT16 Iobase,
IN UINT8 Address,
OUT UINT8 *Buffer,
IN UINTN Offset
)
{
UINTN Status;
UINT64 Limit;
Address |= 1; // set read bit
__outbyte (Iobase + 0, 0xFF); // clear error status
__outbyte (Iobase + 1, 0x1F); // clear error status
__outbyte (Iobase + 3, Offset); // offset in eeprom
__outbyte (Iobase + 4, Address); // slave address and read bit
__outbyte (Iobase + 2, 0x48); // read byte command
/* time limit to avoid hanging for unexpected error status (should never happen) */
Limit = __rdtsc () + 2000000000 / 10;
for (;;) {
Status = __inbyte (Iobase);
if (__rdtsc () > Limit) break;
if ((Status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting
if ((Status & 1) == 1) continue; // HostBusy set, keep waiting
break;
}
Buffer [0] = __inbyte (Iobase + 5);
if (Status == 2) Status = 0; // check for done with no errors
return Status;
}
/*
*
* ReadSmbusByte - read a single SPD byte from the default offset
* this function is faster function readSmbusByteData
*
*/
STATIC
AGESA_STATUS
ReadSmbusByte (
IN UINT16 Iobase,
IN UINT8 Address,
OUT UINT8 *Buffer
)
{
UINTN Status;
UINT64 Limit;
__outbyte (Iobase + 0, 0xFF); // clear error status
__outbyte (Iobase + 2, 0x44); // read command
// time limit to avoid hanging for unexpected error status
Limit = __rdtsc () + 2000000000 / 10;
for (;;) {
Status = __inbyte (Iobase);
if (__rdtsc () > Limit) break;
if ((Status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting
if ((Status & 1) == 1) continue; // HostBusy set, keep waiting
break;
}
Buffer [0] = __inbyte (Iobase + 5);
if (Status == 2) Status = 0; // check for done with no errors
return Status;
}
/*
*
* ReadSpd - Read one or more SPD bytes from a DIMM.
* Start with offset zero and read sequentially.
* Optimization relies on autoincrement to avoid
* sending offset for every byte.
* Reads 128 bytes in 7-8 ms at 400 KHz.
*
*/
STATIC
AGESA_STATUS
ReadSpd (
IN UINT16 IoBase,
IN UINT8 SmbusSlaveAddress,
OUT UINT8 *Buffer,
IN UINTN Count
)
{
UINTN Index, Status;
/* read the first byte using offset zero */
Status = ReadSmbusByteData (IoBase, SmbusSlaveAddress, Buffer, 0);
if (Status) return Status;
/* read the remaining bytes using auto-increment for speed */
for (Index = 1; Index < Count; Index++){
Status = ReadSmbusByte (IoBase, SmbusSlaveAddress, &Buffer [Index]);
if (Status) return Status;
}
return 0;
}
int smbus_readSpd(int spdAddress, char *buf, size_t len)
{
SetupFch (SMBUS_BASE_ADDR);
return ReadSpd (SMBUS_BASE_ADDR, spdAddress, (UINT8 *) buf, len);
}