soc/intel/apollolake: Set PL1 limits for RAPL MSR registers

This patch sets the package power limit (PL1) value in RAPL MSR
and disables MMIO register. Added configurable PL1 override
parameter to leverage full TDP capacity.

BUG=chrome-os-partner:56922
TEST=webGL performance(fps) not impacted before and after S3.

Change-Id: I34208048a6d4a127e9b1267d2df043cb2c46cf77
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/16884
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/intel/apollolake/chip.h

@@ -107,6 +107,9 @@ struct soc_intel_apollolake_config {
 	/* Enable DPTF support */
 	int dptf_enable;
 
+	/* PL1 override value in mW for APL */
+	uint16_t tdp_pl1_override_mw;
+
 	/* Configure Audio clk gate and power gate
 	 * IOSF-SB port ID 92 offset 0x530 [5] and [3]
 	 */