soc/intel/skylake: Use newly added pmc_read_pm1_control
BUG=b:67874513 Change-Id: I298065f30647ae9bba8f6a8481bd34eec64f1d8e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22083 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -140,7 +140,7 @@ static void southbridge_smi_sleep(void)
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pmc_disable_smi(SLP_SMI_EN);
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pmc_disable_smi(SLP_SMI_EN);
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/* Figure out SLP_TYP */
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/* Figure out SLP_TYP */
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reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT);
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reg32 = pmc_read_pm1_control();
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printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32);
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printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32);
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slp_typ = acpi_sleep_from_pm1(reg32);
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slp_typ = acpi_sleep_from_pm1(reg32);
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@ -213,8 +213,7 @@ static void southbridge_smi_sleep(void)
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* the line above. However, if we entered sleep state S1 and wake
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* the line above. However, if we entered sleep state S1 and wake
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* up again, we will continue to execute code in this function.
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* up again, we will continue to execute code in this function.
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*/
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*/
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reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT);
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if (pmc_read_pm1_control() & SCI_EN) {
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if (reg32 & SCI_EN) {
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/* The OS is not an ACPI OS, so we set the state to S0 */
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/* The OS is not an ACPI OS, so we set the state to S0 */
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pmc_disable_pm1_control(SLP_EN | SLP_TYP);
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pmc_disable_pm1_control(SLP_EN | SLP_TYP);
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}
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}
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