haswell: unify romstage logic
This commit pulls in all the common logic for romstage into the Haswell cpu directory. The bits specific to the mainboard still reside under their respective directories. The calling sequence bounces from the cpu directory to mainboard then back to the cpu directory. The reasoning is that Haswell systems use cache-as-ram for backing memory in romstage. The stack is used to allocate structures. However, now changes can be made to the romstage for Haswell and apply to all boards. Change-Id: I2bf08013c46a99235ffe4bde88a935c3378eb341 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2754 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Aaron Durbin
committed by
Ronald G. Minnich
Ronald G. Minnich
parent
9b7f9b9768
commit
a267161362
@@ -19,29 +19,12 @@
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*/
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#include <stdint.h>
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#include <string.h>
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#include <lib.h>
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#include <timestamp.h>
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#include <arch/io.h>
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#include <arch/romcc_io.h>
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#include <device/pci_def.h>
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#include <device/pnp_def.h>
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#include <cpu/x86/lapic.h>
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#include <pc80/mc146818rtc.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include "cpu/intel/haswell/haswell.h"
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#include "northbridge/intel/haswell/haswell.h"
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#include "northbridge/intel/haswell/raminit.h"
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#include "southbridge/intel/lynxpoint/pch.h"
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#include "southbridge/intel/lynxpoint/me.h"
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#include <arch/cpu.h>
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#include <cpu/x86/bist.h>
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#include <cpu/x86/msr.h>
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#include "gpio.h"
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#if CONFIG_CHROMEOS
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#include <vendorcode/google/chromeos/chromeos.h>
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#endif
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const struct rcba_config_instruction rcba_config[] = {
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/*
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@@ -83,21 +66,8 @@ const struct rcba_config_instruction rcba_config[] = {
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RCBA_END_CONFIG,
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};
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void romstage_main(unsigned long bist)
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void mainboard_romstage_entry(unsigned long bist)
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{
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int boot_mode = 0;
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int wake_from_s3;
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int cbmem_was_initted;
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#if CONFIG_COLLECT_TIMESTAMPS
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tsc_t start_romstage_time;
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tsc_t before_dram_time;
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tsc_t after_dram_time;
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tsc_t base_time = {
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.lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
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.hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
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};
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#endif
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struct pei_data pei_data = {
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pei_version: PEI_VERSION,
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mchbar: DEFAULT_MCHBAR,
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@@ -141,101 +111,13 @@ void romstage_main(unsigned long bist)
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},
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};
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#if CONFIG_COLLECT_TIMESTAMPS
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start_romstage_time = rdtsc();
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#endif
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struct romstage_params romstage_params = {
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.pei_data = &pei_data,
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.gpio_map = &mainboard_gpio_map,
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.rcba_config = &rcba_config[0],
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.bist = bist,
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};
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if (bist == 0)
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enable_lapic();
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wake_from_s3 = early_pch_init(&mainboard_gpio_map, &rcba_config[0]);
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/* Halt if there was a built in self test failure */
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report_bist_failure(bist);
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/* Perform some early chipset initialization required
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* before RAM initialization can work
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*/
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haswell_early_initialization(HASWELL_MOBILE);
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printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n");
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if (wake_from_s3) {
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#if CONFIG_HAVE_ACPI_RESUME
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printk(BIOS_DEBUG, "Resume from S3 detected.\n");
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boot_mode = 2;
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#else
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printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
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#endif
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}
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/* Prepare USB controller early in S3 resume */
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if (boot_mode == 2)
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enable_usb_bar();
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post_code(0x3a);
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pei_data.boot_mode = boot_mode;
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#if CONFIG_COLLECT_TIMESTAMPS
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before_dram_time = rdtsc();
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#endif
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report_platform_info();
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sdram_initialize(&pei_data);
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#if CONFIG_COLLECT_TIMESTAMPS
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after_dram_time = rdtsc();
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#endif
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post_code(0x3b);
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intel_early_me_status();
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quick_ram_check();
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post_code(0x3e);
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MCHBAR16(SSKPD) = 0xCAFE;
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#if CONFIG_EARLY_CBMEM_INIT
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cbmem_was_initted = !cbmem_initialize();
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#else
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cbmem_was_initted = cbmem_reinit((uint64_t) (get_top_of_ram()
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- HIGH_MEMORY_SIZE));
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#endif
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#if CONFIG_HAVE_ACPI_RESUME
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/* If there is no high memory area, we didn't boot before, so
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* this is not a resume. In that case we just create the cbmem toc.
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*/
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*(u32 *)CBMEM_BOOT_MODE = 0;
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*(u32 *)CBMEM_RESUME_BACKUP = 0;
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if ((boot_mode == 2) && cbmem_was_initted) {
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void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
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if (resume_backup_memory) {
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*(u32 *)CBMEM_BOOT_MODE = boot_mode;
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*(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory;
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}
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/* Magic for S3 resume */
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pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
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} else if (boot_mode == 2) {
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/* Failed S3 resume, reset to come up cleanly */
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outb(0x6, 0xcf9);
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while (1) {
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hlt();
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}
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} else {
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pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe);
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}
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#endif
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post_code(0x3f);
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#if CONFIG_CHROMEOS
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init_chromeos(boot_mode);
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#endif
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#if CONFIG_COLLECT_TIMESTAMPS
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timestamp_init(base_time);
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timestamp_add(TS_START_ROMSTAGE, start_romstage_time );
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timestamp_add(TS_BEFORE_INITRAM, before_dram_time );
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timestamp_add(TS_AFTER_INITRAM, after_dram_time );
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timestamp_add_now(TS_END_ROMSTAGE);
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#endif
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/* Call into the real romstage main with this board's attributes. */
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romstage_common(&romstage_params);
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}
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