add support for ICH4. more i955pm stuff.

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1649 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/mainboard/digitallogic/adl855pc/Config.lb

@@ -140,7 +140,7 @@ end
 
 makerule ./failover.inc
 	depends "./failover.E ./romcc"
-	action "./romcc -O -mcpu=c3 -o failover.inc --label-prefix=failover ./failover.E"
+	action "./romcc -O -mcpu=p4 -o failover.inc --label-prefix=failover ./failover.E"
 end
 
 makerule ./auto.E 
@@ -149,7 +149,7 @@ makerule ./auto.E
 end
 makerule ./auto.inc 
 	depends "./auto.E ./romcc"
-	action	"./romcc   -O -mcpu=c3 ./auto.E "
+	action	"./romcc   -O -mcpu=p4 ./auto.E "
 end
 
 ##

src/mainboard/digitallogic/adl855pc/auto.c

@@ -5,7 +5,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <arch/smp/lapic.h>
-#include "option_table.h"
+//#include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"

src/northbridge/intel/i855pm/raminit.c

@@ -5,7 +5,7 @@
 /* converted to C 6/2004 yhlu */
 
 #define DEBUG_RAM_CONFIG 1
-
+#define ASM_CONSOLE_LOGLEVEL 10
 #define dumpnorth() dump_pci_device(PCI_DEV(0, 0, 0)) 
 
 /* DDR DIMM Mode register Definitions */
@@ -1512,7 +1512,7 @@ static unsigned int spd_detect_dimms(const struct mem_controller *ctrl)
                                 dimm_mask |= (1 << i);
                         }
                 }
-#if 1
+#if 0
                 device = ctrl->channel1[i];
                 if (device) {
                         byte = spd_read_byte(ctrl->channel1[i], 2);
@@ -1798,12 +1798,13 @@ static void dram_finish(const struct mem_controller *ctrl)
 #endif
 
 		/* Clear the ECC error bits */
+#if 0
 		pci_write_config8(ctrl->d0f1, 0x80, 0x03); /* dev 0, function 1, offset 80 */
 		pci_write_config8(ctrl->d0f1, 0x82, 0x03); /* dev 0, function 1, offset 82 */
 
 		pci_write_config32(ctrl->d0f1, 0x40, 1<<18); /* clear dev 0, function 1, offset 40; bit 18 by writing a 1 to it */
   	        pci_write_config32(ctrl->d0f1, 0x44, 1<<18); /* clear dev 0, function 1, offset 44; bit 18 by writing a 1 to it */
-
+#endif
 		pci_write_config8(ctrl->d0, 0x52, 0x0d);
 	}