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soc/intel/alderlake: Wait for panel power cycle to complete

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The Alder Lake PEIM graphics driver executed as part of the FSP does
not wait for the panel power cycle to complete before it initializes
communication with the display. It can result in AUX channel
communication time out and PEIM graphics driver failing to bring up
graphics.

If we have performed some graphics operation in romstage, it is
possible that a panel power cycle is still in progress. To prevent any
issue with the PEIM graphics driver it is preferable to ensure that
panel power cycle is complete.

This patch replaces commit ba2cef5b54
("soc/intel/common/block/early_graphics: Introduce a 200 ms delay")
workaround patch.

BUG=b:264526798
BRANCH=firmware-brya-14505.B
TEST=Developer screen is visible in the recovery flow

Change-Id: Iadd6c9552b184f7d6ec8df9d0d392634864ba50b
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72419
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This commit is contained in:
Jeremy Compostella
2023-01-19 19:06:09 -07:00
committed by Nick Vaccaro
parent b628beca34
commit a2a7fecabf
3 changed files with 47 additions and 17 deletions
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2
src/drivers/intel/gma/i915_reg.h
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@@ -3753,6 +3753,8 @@
#define PIPEB_PP_DIVISOR 0x61310
#define PCH_PP_STATUS 0xc7200
#define PANEL_POWER_CYCLE_ACTIVE (1 << 27)
#define PCH_PP_CONTROL 0xc7204
#define PANEL_UNLOCK_REGS (0xabcd << 16)
#define PANEL_UNLOCK_MASK (0xffff << 16)