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soc/intel/skylake: Add FSP 2.0 support in ramstage

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Add FSP 2.0 support in ramstage.
Populate required Fsp Silicon Init params and configure mainboard
specific GPIOs.
Define function fsp_soc_get_igd_bar needed by fsp2.0 driver for
pre OS screens.

Change-Id: Ib38ca7547b5d5ec2b268698b8886d5caa28d6497
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/16592
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Naresh G Solanki
2016-08-30 20:47:13 +05:30
committed by Martin Roth
parent 21130c6508
commit a2d4062d42
11 changed files with 585 additions and 335 deletions
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13
src/soc/intel/skylake/chip.h
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@@ -273,6 +273,19 @@ struct soc_intel_skylake_config {
u16 PchConfigSubSystemVendorId;
/* Subsystem ID of the PCH devices*/
u16 PchConfigSubSystemId;
/*
* Determine if WLAN wake from Sx, corresponds to the
* HOST_WLAN_PP_EN bit in the PWRM_CFG3 register.
*/
u8 PchPmWoWlanEnable;
/*
* Determine if WLAN wake from DeepSx, corresponds to
* the DSX_WLAN_PP_EN bit in the PWRM_CFG3 register.
*/
u8 PchPmWoWlanDeepSxEnable;
/*
* Corresponds to the "WOL Enable Override" bit in the General PM
* Configuration B (GEN_PMCON_B) register