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arch/x86: Introduce ARCH_ALL_STAGES_X86_32

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Nearly every x86 platform uses the same arch for all stages. The only
exception is Picasso. So, factor out redundant symbols from the rest.

Alder Lake is not yet complete, so it has been skipped for now.

Change-Id: I7cff9efbc44546807d9af089292c69fb0acc7bad
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Angel Pons
2020-09-25 10:20:11 +02:00
committed by Nico Huber
parent 2db7790795
commit a32df26ec0
33 changed files with 39 additions and 128 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
src/cpu/amd/agesa/Kconfig
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@@ -6,10 +6,7 @@ config CPU_AMD_AGESA
default y if CPU_AMD_AGESA_FAMILY15_TN
default y if CPU_AMD_AGESA_FAMILY16_KB
default n
select ARCH_BOOTBLOCK_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select ARCH_ALL_STAGES_X86_32
select DRIVERS_AMD_PI
select TSC_SYNC_LFENCE
select UDELAY_LAPIC

5
src/cpu/amd/pi/Kconfig
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@@ -6,10 +6,7 @@ config CPU_AMD_PI
default y if CPU_AMD_PI_00730F01
default y if CPU_AMD_PI_00660F01
default n
select ARCH_BOOTBLOCK_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select ARCH_ALL_STAGES_X86_32
select DRIVERS_AMD_PI
select TSC_SYNC_LFENCE
select UDELAY_LAPIC

5
src/cpu/intel/haswell/Kconfig
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@@ -6,10 +6,7 @@ if CPU_INTEL_HASWELL
config CPU_SPECIFIC_OPTIONS
def_bool y
select ARCH_BOOTBLOCK_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select ARCH_ALL_STAGES_X86_32
select MMX
select SSE2
select UDELAY_TSC

5
src/cpu/intel/model_1067x/Kconfig
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@@ -1,9 +1,6 @@
config CPU_INTEL_MODEL_1067X
bool
select ARCH_BOOTBLOCK_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select ARCH_ALL_STAGES_X86_32
select SSE2
select UDELAY_TSC
select TSC_MONOTONIC_TIMER

5
src/cpu/intel/model_106cx/Kconfig
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@@ -1,9 +1,6 @@
config CPU_INTEL_MODEL_106CX
bool
select ARCH_BOOTBLOCK_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select ARCH_ALL_STAGES_X86_32
select SSE2
select UDELAY_TSC
select TSC_MONOTONIC_TIMER

5
src/cpu/intel/model_2065x/Kconfig
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@@ -5,10 +5,7 @@ if CPU_INTEL_MODEL_2065X
config CPU_SPECIFIC_OPTIONS
def_bool y
select ARCH_BOOTBLOCK_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select ARCH_ALL_STAGES_X86_32
select SSE2
select UDELAY_TSC
select TSC_MONOTONIC_TIMER

5
src/cpu/intel/model_206ax/Kconfig
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@@ -5,10 +5,7 @@ if CPU_INTEL_MODEL_206AX
config CPU_SPECIFIC_OPTIONS
def_bool y
select ARCH_BOOTBLOCK_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select ARCH_ALL_STAGES_X86_32
select MMX
select SSE2
select UDELAY_TSC

5
src/cpu/intel/model_65x/Kconfig
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@@ -1,7 +1,4 @@
config CPU_INTEL_MODEL_65X
bool
select ARCH_BOOTBLOCK_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select ARCH_ALL_STAGES_X86_32
select SUPPORT_CPU_UCODE_IN_CBFS

5
src/cpu/intel/model_67x/Kconfig
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@@ -1,7 +1,4 @@
config CPU_INTEL_MODEL_67X
bool
select ARCH_BOOTBLOCK_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select ARCH_ALL_STAGES_X86_32
select SUPPORT_CPU_UCODE_IN_CBFS

5
src/cpu/intel/model_68x/Kconfig
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@@ -2,8 +2,5 @@
config CPU_INTEL_MODEL_68X
bool
select ARCH_BOOTBLOCK_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select ARCH_ALL_STAGES_X86_32
select SUPPORT_CPU_UCODE_IN_CBFS

5
src/cpu/intel/model_6bx/Kconfig
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@@ -1,7 +1,4 @@
config CPU_INTEL_MODEL_6BX
bool
select ARCH_BOOTBLOCK_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select ARCH_ALL_STAGES_X86_32
select SUPPORT_CPU_UCODE_IN_CBFS

5
src/cpu/intel/model_6ex/Kconfig
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@@ -1,9 +1,6 @@
config CPU_INTEL_MODEL_6EX
bool
select ARCH_BOOTBLOCK_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select ARCH_ALL_STAGES_X86_32
select SSE2
select UDELAY_TSC
select TSC_MONOTONIC_TIMER

5
src/cpu/intel/model_6fx/Kconfig
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@@ -1,9 +1,6 @@
config CPU_INTEL_MODEL_6FX
bool
select ARCH_BOOTBLOCK_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select ARCH_ALL_STAGES_X86_32
select SSE2
select UDELAY_TSC
select TSC_MONOTONIC_TIMER

5
src/cpu/intel/model_6xx/Kconfig
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@@ -1,7 +1,4 @@
config CPU_INTEL_MODEL_6XX
bool
select ARCH_BOOTBLOCK_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select ARCH_ALL_STAGES_X86_32
select SUPPORT_CPU_UCODE_IN_CBFS

5
src/cpu/intel/model_f2x/Kconfig
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@@ -1,9 +1,6 @@
config CPU_INTEL_MODEL_F2X
bool
select ARCH_BOOTBLOCK_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select ARCH_ALL_STAGES_X86_32
select SUPPORT_CPU_UCODE_IN_CBFS
select SMM_ASEG
select CPU_INTEL_COMMON

5
src/cpu/intel/model_f3x/Kconfig
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@@ -1,9 +1,6 @@
config CPU_INTEL_MODEL_F3X
bool
select ARCH_BOOTBLOCK_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select ARCH_ALL_STAGES_X86_32
select SUPPORT_CPU_UCODE_IN_CBFS
select CPU_INTEL_COMMON
select CPU_INTEL_COMMON_HYPERTHREADING

5
src/cpu/intel/model_f4x/Kconfig
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@@ -1,7 +1,4 @@
config CPU_INTEL_MODEL_F4X
bool
select ARCH_BOOTBLOCK_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select ARCH_ALL_STAGES_X86_32
select SUPPORT_CPU_UCODE_IN_CBFS

5
src/cpu/qemu-x86/Kconfig
View File

@@ -19,9 +19,6 @@ config CPU_QEMU_X86_32
bool
default n if CPU_QEMU_X86_64
default y
select ARCH_BOOTBLOCK_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_ALL_STAGES_X86_32
select ARCH_POSTCAR_X86_32
select ARCH_RAMSTAGE_X86_32
endif