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src: Remove unneeded whitespace

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Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Elyes HAOUAS
2018-10-17 10:56:26 +02:00
committed by Patrick Georgi
parent 9856892297
commit a342f3937e
164 changed files with 508 additions and 480 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/northbridge/amd/agesa/family12/dimmSpd.c
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@@ -55,7 +55,7 @@ AmdMemoryReadSPD (
IN UINT32 Func,
IN UINTN Data,
IN OUT AGESA_READ_SPD_PARAMS *SpdData
)
)
{
UINT8 SmBusAddress = 0;
UINTN Index;

4
src/northbridge/amd/agesa/family14/northbridge.c
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@@ -149,7 +149,7 @@ static struct resource *amdfam14_find_iopair(struct device *dev,
/* Ext conf space */
if (!reg) {
/* Because of Extend conf space, we will never run out of reg,
* but we need one index to differ them. So ,same node and same
* but we need one index to differ them. So,same node and same
* link can have multi range
*/
u32 index = get_io_addr_index(nodeid, link);
@@ -185,7 +185,7 @@ static struct resource *amdfam14_find_mempair(struct device *dev, u32 nodeid,
/* Ext conf space */
if (!reg) {
/* Because of Extend conf space, we will never run out of reg,
* but we need one index to differ them. So ,same node and same
* but we need one index to differ them. So,same node and same
* link can have multi range
*/
u32 index = get_mmio_addr_index(nodeid, link);

2
src/northbridge/amd/amdmct/mct/mct_d.c
View File

@@ -1737,7 +1737,7 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat,
* and PCI 0:24N:2x60,64,68,6C config registers (CS Mask 0-3).
*/
u8 ChipSel, Rows, Cols, Ranks ,Banks, DevWidth;
u8 ChipSel, Rows, Cols, Ranks, Banks, DevWidth;
u32 BankAddrReg, csMask;
u32 val;

2
src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
View File

@@ -684,7 +684,7 @@ void prepareDimms(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat,
{tempW = bitTestSet(tempW, 7);}
if (bitTest(tempW1,18))
{tempW = bitTestSet(tempW, 6);}
/* tempW = tempW|(((tempW1 >> 20) & 0x7 )<< 3); */
/* tempW = tempW|(((tempW1 >> 20) & 0x7)<< 3); */
tempW = tempW|((tempW1&0x00700000) >> 17);
/* workaround for DR-B0 */
if ((pDCTData->LogicalCPUID & AMD_DR_Bx) && (pDCTData->Status[DCT_STATUS_REGISTERED]))

3
src/northbridge/intel/e7505/debug.c
View File

@@ -148,7 +148,8 @@ void dump_smbus_registers(void)
printk(BIOS_DEBUG, "\n");
for (device = 1; device < 0x80; device++) {
int j;
if ( spd_read_byte(device, 0) < 0 ) continue;
if (spd_read_byte(device, 0) < 0)
continue;
printk(BIOS_DEBUG, "smbus: %02x", device);
for (j = 0; j < 256; j++) {
int status;

2
src/northbridge/intel/fsp_rangeley/northbridge.c
View File

@@ -131,7 +131,7 @@ static void mc_add_dram_resources(struct device *dev)
mmio_resource(dev, index++, tomlow >> 10, (bmbound - bsmmrrl) >> 10);
if (bmbound_hi > 0x100000000) {
ram_resource(dev, index++, 0x100000000 >> 10, (bmbound_hi - 0x100000000) >> 10 );
ram_resource(dev, index++, 0x100000000 >> 10, (bmbound_hi - 0x100000000) >> 10);
printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", (bmbound_hi - 0x100000000) >> 20);
}

2
src/northbridge/intel/haswell/raminit.c
View File

@@ -180,7 +180,7 @@ void sdram_initialize(struct pei_data *pei_data)
*/
u32 version = MCHBAR32(0x5034);
printk(BIOS_DEBUG, "System Agent Version %d.%d.%d Build %d\n",
version >> 24 , (version >> 16) & 0xff,
version >> 24, (version >> 16) & 0xff,
(version >> 8) & 0xff, version & 0xff);
report_memory_config();

2
src/northbridge/intel/nehalem/early_init.c
View File

@@ -36,7 +36,7 @@ static void nehalem_setup_bars(void)
pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
/* Enable ACPI BAR */
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80);
printk(BIOS_DEBUG, " done.\n");

2
src/northbridge/intel/nehalem/raminit.c
View File

@@ -1420,7 +1420,7 @@ static void program_total_memory_map(struct raminfo *info)
TOM = 4032;
TOUUD = ALIGN_DOWN(TOM - info->memory_reserved_for_heci_mb, 64);
TOLUD = ALIGN_DOWN(min(4096 - mmio_size + ALIGN_UP(uma_size_igd + uma_size_gtt, 64)
, TOUUD), 64);
, TOUUD), 64);
memory_remap = 0;
if (TOUUD - TOLUD > 64) {
memory_remap = 1;

4
src/northbridge/intel/pineview/early_init.c
View File

@@ -181,9 +181,9 @@ static void pineview_setup_bars(void)
printk(BIOS_DEBUG, "Setting up static southbridge registers...");
pci_write_config32(LPC, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
pci_write_config32(LPC, PMBASE, DEFAULT_PMBASE | 1);
pci_write_config8(LPC, 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI */
pci_write_config8(LPC, 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI */
pci_write_config32(LPC, GPIOBASE, DEFAULT_GPIOBASE | 1);
pci_write_config8(LPC, 0x4c /* GC */ , 0x10); /* Enable GPIOs */
pci_write_config8(LPC, 0x4c /* GC */, 0x10); /* Enable GPIOs */
pci_write_config32(LPC, 0x88, 0x007c0291);
pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);

14
src/northbridge/intel/pineview/raminit.c
View File

@@ -57,13 +57,13 @@
#define DIMM_IS_POPULATED(dimms, idx) (dimms[idx].card_type != 0)
#define IF_DIMM_POPULATED(dimms, idx) if (dimms[idx].card_type != 0)
#define ONLY_DIMMA_IS_POPULATED(dimms, ch) ( \
#define ONLY_DIMMA_IS_POPULATED(dimms, ch) (\
(DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2) && \
!DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3)))
#define ONLY_DIMMB_IS_POPULATED(dimms, ch) ( \
#define ONLY_DIMMB_IS_POPULATED(dimms, ch) (\
(DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3) && \
!DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2)))
#define BOTH_DIMMS_ARE_POPULATED(dimms, ch) ( \
#define BOTH_DIMMS_ARE_POPULATED(dimms, ch) (\
(DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2) && \
(DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3))))
#define FOR_EACH_DIMM(idx) \
@@ -905,11 +905,11 @@ static void sdram_p_dqs(struct pllparam *pll, u8 f, u8 clk)
reg32 |= ((u32) pll->dben[f][clk]) << (dqs + 9);
reg32 |= ((u32) pll->dbsel[f][clk]) << dqs;
MCHBAR32(0x5b4+rank*4) = (MCHBAR32(0x5b4+rank*4) &
~( (1 << (dqs+9))|(1 << dqs) )) | reg32;
~((1 << (dqs+9))|(1 << dqs))) | reg32;
reg32 = ((u32) pll->clkdelay[f][clk]) << ((dqs*2) + 16);
MCHBAR32(0x5c8+rank*4) = (MCHBAR32(0x5c8+rank*4) &
~( (1 << (dqs*2 + 17))|(1 << (dqs*2 + 16)) )) | reg32;
~((1 << (dqs*2 + 17))|(1 << (dqs*2 + 16)))) | reg32;
reg8 = pll->pi[f][clk];
MCHBAR8(0x520+j) = (MCHBAR8(0x520+j) & ~0x3f) | reg8;
@@ -930,11 +930,11 @@ static void sdram_p_dq(struct pllparam *pll, u8 f, u8 clk)
reg32 |= ((u32) pll->dben[f][clk]) << (dq + 9);
reg32 |= ((u32) pll->dbsel[f][clk]) << dq;
MCHBAR32(0x5a4+rank*4) = (MCHBAR32(0x5a4+rank*4) &
~( (1 << (dq+9))|(1 << dq) )) | reg32;
~((1 << (dq+9))|(1 << dq))) | reg32;
reg32 = ((u32) pll->clkdelay[f][clk]) << (dq*2);
MCHBAR32(0x5c8+rank*4) = (MCHBAR32(0x5c8+rank*4) &
~( (1 << (dq*2 + 1))|(1 << (dq*2)) )) | reg32;
~((1 << (dq*2 + 1))|(1 << (dq*2)))) | reg32;
reg8 = pll->pi[f][clk];
MCHBAR8(0x500+j) = (MCHBAR8(0x500+j) & ~0x3f) | reg8;

2
src/northbridge/intel/sandybridge/raminit_ivy.c
View File

@@ -225,7 +225,7 @@ static u8 get_XP(u32 tCK, u8 base_freq)
* FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 |
* XP : | 3 | 4 | 4 | 5 | 6 | 7 | 8 | 8 |
*/
static const u8 frq_xp_map[] = { 3, 4, 4, 5, 6, 7 , 8, 8 };
static const u8 frq_xp_map[] = { 3, 4, 4, 5, 6, 7, 8, 8 };
xp = frq_xp_map[get_FRQ(tCK, 133) - 3];
}

2
src/northbridge/intel/sandybridge/raminit_mrc.c
View File

@@ -248,7 +248,7 @@ void sdram_initialize(struct pei_data *pei_data)
*/
u32 version = MCHBAR32(0x5034);
printk(BIOS_DEBUG, "System Agent Version %d.%d.%d Build %d\n",
version >> 24 , (version >> 16) & 0xff,
version >> 24, (version >> 16) & 0xff,
(version >> 8) & 0xff, version & 0xff);
/* Send ME init done for SandyBridge here. This is done

2
src/northbridge/intel/x4x/dq_dqs.c
View File

@@ -463,7 +463,7 @@ int do_read_training(struct sysinfo *s)
struct rt_dqs_setting dqs_setting[TOTAL_BYTELANES];
u16 saved_dqs_center[TOTAL_CHANNELS][TOTAL_BYTELANES];
memset(saved_dqs_center, 0 , sizeof(saved_dqs_center));
memset(saved_dqs_center, 0, sizeof(saved_dqs_center));
printk(BIOS_DEBUG, "Starting DQS read training\n");

18
src/northbridge/via/vx900/chrome9hd.c
View File

@@ -105,15 +105,15 @@ u8 vx900_int15_get_5f18_bl(void)
* 0000: 66MHz
* 0001: 100MHz
* 0010: 133MHz
* 0011: 200MHz ( DDR200 )
* 0100: 266MHz ( DDR266 )
* 0101: 333MHz ( DDR333 )
* 0110: 400MHz ( DDR400 )
* 0111: 533MHz ( DDR I/II 533)
* 1000: 667MHz ( DDR I/II 667)
* 1001: 800MHz ( DDR3 800)
* 1010: 1066MHz ( DDR3 1066)
* 1011: 1333MHz ( DDR3 1333)
* 0011: 200MHz (DDR200)
* 0100: 266MHz (DDR266)
* 0101: 333MHz (DDR333)
* 0110: 400MHz (DDR400)
* 0111: 533MHz (DDR I/II 533)
* 1000: 667MHz (DDR I/II 667)
* 1001: 800MHz (DDR3 800)
* 1010: 1066MHz (DDR3 1066)
* 1011: 1333MHz (DDR3 1333)
* Bit[3:0]
* N: Frame Buffer Size 2^N MB
*/