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src: Remove unneeded whitespace

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Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Elyes HAOUAS 2018-10-17 10:56:26 +02:00 committed by Patrick Georgi
parent 9856892297
commit a342f3937e
164 changed files with 508 additions and 480 deletions
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6
src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c
View File

@ -68,7 +68,8 @@ unsigned long acpi_fill_madt(unsigned long current)
for (i = 1; i < sysconf.hc_possible_num; i++) {
u32 d = 0;
if(!(sysconf.pci1234[i] & 0x1) ) continue;
if (!(sysconf.pci1234[i] & 0x1))
continue;
/* 8131 need to use +4 */
switch (sysconf.hcid[i]) {
case 1:
@ -137,7 +138,8 @@ unsigned long mainboard_write_acpi_tables(struct device *device,
for (i = 1; i < sysconf.hc_possible_num; i++) { /* 0: is hc sblink */
const char *file_name;
if((sysconf.pci1234[i] & 1) != 1 ) continue;
if ((sysconf.pci1234[i] & 1) != 1)
continue;
u8 c;
if (i < 7) {
c = (u8) ('4' + i - 1);

3
src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c
View File

@ -145,7 +145,8 @@ void get_bus_conf(void)
/* HT chain 1 */
j = 0;
for (i = 1; i < sysconf.hc_possible_num; i++) {
if(!(sysconf.pci1234[i] & 0x1) ) continue;
if (!(sysconf.pci1234[i] & 0x1))
continue;
/* check hcid type here */
sysconf.hcid[i] = get_hcid(i);

6
src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
View File

@ -68,7 +68,8 @@ static void *smp_write_config_table(void *v)
j = 0;
for (i = 1; i < sysconf.hc_possible_num; i++) {
if(!(sysconf.pci1234[i] & 0x1) ) continue;
if (!(sysconf.pci1234[i] & 0x1))
continue;
switch(sysconf.hcid[i]) {
case 1:
@ -131,7 +132,8 @@ static void *smp_write_config_table(void *v)
j = 0;
for (i = 1; i < sysconf.hc_possible_num; i++) {
if(!(sysconf.pci1234[i] & 0x1) ) continue;
if (!(sysconf.pci1234[i] & 0x1))
continue;
int ii;
int jj;
struct device *dev;

3
src/northbridge/intel/e7505/debug.c
View File

@ -148,7 +148,8 @@ void dump_smbus_registers(void)
printk(BIOS_DEBUG, "\n");
for (device = 1; device < 0x80; device++) {
int j;
if ( spd_read_byte(device, 0) < 0 ) continue;
if (spd_read_byte(device, 0) < 0)
continue;
printk(BIOS_DEBUG, "smbus: %02x", device);
for (j = 0; j < 256; j++) {
int status;

60
src/soc/broadcom/cygnus/ddr_init.c
View File

@ -71,40 +71,52 @@ void PRE_SRX(void)
// Disable low power receivers: bit 0 of the byte lane STATIC_PAD_CTL register
readvalue = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL);
reg32_write ((volatile uint32_t *)DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL, ( readvalue & ~(1 << DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__RX_MODE_R)));
reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL,
(readvalue & ~(1 << DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__RX_MODE_R)));
// Turn off ZQ_CAL drivers: bits 0,1, and 17 of the ZQ_CAL register (other bits 0 & 1 are set to 1)
readvalue = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_ZQ_CAL);
reg32_write ((volatile uint32_t *)DDR_PHY_CONTROL_REGS_ZQ_CAL, ( readvalue & ~(1 << DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_IDDQ)));
reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_ZQ_CAL,
(readvalue & ~(1 << DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_IDDQ)));
// Byte lane 0 power up
readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL);
reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, ( readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDLE)));
reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL,
(readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDLE)));
readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL);
reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, ( readvalue & 0xffff800f));
reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL,
(readvalue & 0xffff800f));
readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL);
reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, ( readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDDQ)));
reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL,
(readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDDQ)));
// Byte lane 1 power up
readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL);
reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, ( readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDLE)));
reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL,
(readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDLE)));
readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL);
reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, ( readvalue & 0xffff800f));
reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL,
(readvalue & 0xffff800f));
readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL);
reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, ( readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDDQ)));
reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL,
(readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDDQ)));
// Turn on PHY_CONTROL AUTO_OEB C not required
// Enable byte lane AUTO_DQ_RXENB_MODE: bits 18 and 19 of the byte lane IDLE_PAD_CONTROL C already set 180114c8: 000f000a
printk(BIOS_INFO, "\n....PLL power up.\n");
reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG, (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & ~(1<<DDR_PHY_CONTROL_REGS_PLL_CONFIG__PWRDN)));
reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG,
(reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) &
~(1<<DDR_PHY_CONTROL_REGS_PLL_CONFIG__PWRDN)));
// PLL out of reset
reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG, (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & ~(1<<DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESET)));
reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG,
(reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) &
~(1<<DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESET)));
printk(BIOS_INFO, "\n....poll lock..\n");
// Poll lock
readvalue = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_STATUS);
@ -115,25 +127,34 @@ void PRE_SRX(void)
}
printk(BIOS_INFO, "\n....after while..\n");
reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG, (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & ~(1<<DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESET_POST_DIV)));
reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG,
(reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) &
~(1<<DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESET_POST_DIV)));
printk(BIOS_INFO, "\n....remove hold..\n");
// Remove hold
reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG, (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & ~(1<<DDR_PHY_CONTROL_REGS_PLL_CONFIG__HOLD)));
reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG,
(reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) &
~(1<<DDR_PHY_CONTROL_REGS_PLL_CONFIG__HOLD)));
printk(BIOS_INFO, "\n....restore dac..\n");
// Restore DAC
reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL, (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL) & 0xffff0fff));
reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL,
(reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL) & 0xffff0fff));
printk(BIOS_INFO, "\n....set iddq bit..\n");
// Set the iddq bit in the idle control register and select all outputs except cke and rst in the idee select registers.
// Do NOT assert any other bits in the idle control register. (This step can be done during init on power up.)
reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL, (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL) & ~(1 << DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__IDDQ)));
reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL,
(reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL) &
~(1 << DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__IDDQ)));
printk(BIOS_INFO, "\n....idle pad enable 0..\n");
reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0, 0x0);
reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1, 0x0);
printk(BIOS_INFO, "\n....DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL..\n");
reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL, (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL) & ~(1 << DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__IDLE)));
reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL,
(reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL) &
~(1 << DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__IDLE)));
}
#endif
@ -985,8 +1006,7 @@ static int try_restore_shmoo(void)
/* Perform memory test to see if the parameters work */
if (CONFIG_SHMOO_REUSE_MEMTEST_LENGTH > 0) {
printk(BIOS_INFO, "Running simple memory test ..... ");
i = simple_memory_test(
(void *)CONFIG_SHMOO_REUSE_MEMTEST_START,
i = simple_memory_test((void *)CONFIG_SHMOO_REUSE_MEMTEST_START,
CONFIG_SHMOO_REUSE_MEMTEST_LENGTH);
if (i) {
printk(BIOS_ERR, "failed!\n");
@ -1116,9 +1136,11 @@ static int clear_ddr(uint32_t offset, uint32_t size)
unsigned long start;
unsigned int i, val;
reg32_write((uint32_t *)DDR_BistConfig,reg32_read((uint32_t *)DDR_BistConfig) & ~0x1);
reg32_write((uint32_t *)DDR_BistConfig,
reg32_read((uint32_t *)DDR_BistConfig) & ~0x1);
for ( i = 0; i < 1000; i++);
for (i = 0; i < 1000; i++)
;
#if !defined(CONFIG_IPROC_P7)
reg32_write((volatile uint32_t *)DDR_DENALI_CTL_213, 0x00FFFFFF);