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src: Remove unneeded whitespace

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Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Elyes HAOUAS 2018-10-17 10:56:26 +02:00 committed by Patrick Georgi
parent 9856892297
commit a342f3937e
164 changed files with 508 additions and 480 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/arch/x86/acpigen.c
View File

@ -453,7 +453,7 @@ static void acpigen_write_field_name(const char *name, uint32_t size)
* FIELDLIST_OFFSET(0x84),
* FIELDLIST_NAMESTR("PMCS", 2),
* };
* acpigen_write_field("UART", l ,ARRAY_SIZE(l), FIELD_ANYACC | FIELD_NOLOCK |
* acpigen_write_field("UART", l, ARRAY_SIZE(l), FIELD_ANYACC | FIELD_NOLOCK |
* FIELD_PRESERVE);
* Output:
* Field (UART, AnyAcc, NoLock, Preserve)

2
src/commonlib/storage/storage_write.c
View File

@ -130,7 +130,7 @@ uint64_t storage_block_fill_write(struct storage_media *media, uint64_t start,
uint32_t *buffer = malloc(buffer_bytes);
uint32_t *ptr = buffer;
for ( ; buffer_words ; buffer_words--)
for (; buffer_words ; buffer_words--)
*ptr++ = fill_pattern;
uint64_t todo = count;

2
src/cpu/amd/family_10h-family_15h/fidvid.c
View File

@ -682,7 +682,7 @@ static void waitCurrentPstate(u32 target_pstate) {
do { // should we just go on instead ?
pstate_msr = rdmsr(PS_STS_REG);
} while ( pstate_msr.lo != target_pstate );
} while (pstate_msr.lo != target_pstate);
}
}

2
src/cpu/amd/family_10h-family_15h/powernow_acpi.c
View File

@ -226,7 +226,7 @@ void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
fam10h_rev_e = 1;
/*
* Based on the CPU socket type,cmp_cap and pwr_lmt , get the power limit.
* Based on the CPU socket type, cmp_cap and pwr_lmt, get the power limit.
* socket_type : 0x10 SocketF; 0x11 AM2/ASB1; 0x12 S1G1
* cmp_cap : 0x0 SingleCore; 0x1 DualCore; 0x2 TripleCore; 0x3 QuadCore; 0x4 QuintupleCore; 0x5 HexCore
*/

2
src/cpu/amd/microcode/microcode.c
View File

@ -129,7 +129,7 @@ static void apply_microcode_patch(const struct microcode *m)
msr = rdmsr(0x8b);
new_patch_id = msr.lo;
UCODE_DEBUG("updated to patch id = 0x%08x %s\n", new_patch_id ,
UCODE_DEBUG("updated to patch id = 0x%08x %s\n", new_patch_id,
(new_patch_id == m->patch_id) ? "success" : "fail");
}

10
src/cpu/via/nano/nano_init.c
View File

@ -71,7 +71,7 @@ static void nano_set_max_fid_vid(void)
printk(BIOS_INFO, "Voltage ID : %dx (min %dx; max %dx)\n",
cur_vid, min_vid, max_vid);
if ( (cur_fid != max_fid) || (cur_vid != max_vid) ) {
if ((cur_fid != max_fid) || (cur_vid != max_vid)) {
/* Set highest frequency and VID */
msr.lo = msr.hi;
msr.hi = 0;
@ -101,7 +101,7 @@ static void nano_power(void)
* This MSR is not documented by VIA docs, other than setting these
* bits */
msr = rdmsr(NANO_MYSTERIOUS_MSR);
msr.lo |= ( (1 << 7) | (1 << 4) );
msr.lo |= ((1 << 7) | (1 << 4));
/* FIXME: Do we have a 6-bit or 7-bit VRM?
* set bit [5] for 7-bit, or don't set it for 6 bit VRM
* This will probably require a Kconfig option
@ -114,15 +114,15 @@ static void nano_power(void)
/* Enable TM3 */
msr = rdmsr(IA32_MISC_ENABLE);
msr.lo |= ( (1 << 3) | (1 << 13) );
msr.lo |= ((1 << 3) | (1 << 13));
wrmsr(IA32_MISC_ENABLE, msr);
u8 stepping = ( cpuid_eax(0x1) ) &0xf;
u8 stepping = (cpuid_eax(0x1)) & 0xf;
if (stepping >= MODEL_NANO_3000_B0) {
/* Hello Nano 3000. The Terminator needs a CPU upgrade */
/* Enable C1e, C2e, C3e, and C4e states */
msr = rdmsr(IA32_MISC_ENABLE);
msr.lo |= ( (1 << 25) | (1 << 26) | (1 << 31)); /* C1e, C2e, C3e */
msr.lo |= ((1 << 25) | (1 << 26) | (1 << 31)); /* C1e, C2e, C3e */
msr.hi |= (1 << 0); /* C4e */
wrmsr(IA32_MISC_ENABLE, msr);
}

8
src/cpu/via/nano/update_ucode.c
View File

@ -43,9 +43,9 @@ static ucode_update_status nano_apply_ucode(const nano_ucode_header *ucode)
static void nano_print_ucode_info(const nano_ucode_header *ucode)
{
printk(BIOS_SPEW, "Microcode update information:\n");
printk(BIOS_SPEW, "Name: %8s\n", ucode->name );
printk(BIOS_SPEW, "Name: %8s\n", ucode->name);
printk(BIOS_SPEW, "Date: %u/%u/%u\n", ucode->month,
ucode->day, ucode->year );
ucode->day, ucode->year);
}
static ucode_validity nano_ucode_is_valid(const nano_ucode_header *ucode)
@ -54,7 +54,7 @@ static ucode_validity nano_ucode_is_valid(const nano_ucode_header *ucode)
if (ucode->signature != NANO_UCODE_SIGNATURE)
return NANO_UCODE_SIGNATURE_ERROR;
/* The size of the head must be exactly 12 double words */
if ( (ucode->total_size - ucode->payload_size) != NANO_UCODE_HEADER_SIZE)
if ((ucode->total_size - ucode->payload_size) != NANO_UCODE_HEADER_SIZE)
return NANO_UCODE_WRONG_SIZE;
/* How about a checksum ? Checksum must be 0
@ -119,7 +119,7 @@ unsigned int nano_update_ucode(void)
/* We might do a lot of loops searching for the microcode updates, but
* keep in mind, nano_ucode_is_valid searches for the signature before
* doing anything else. */
for ( i = 0; i < (ucode_len >> 2); /* don't increment i here */ )
for (i = 0; i < (ucode_len >> 2); /* don't increment i here */)
{
ucode_update_status stat;
const nano_ucode_header * ucode = (void *)(&ucode_data[i]);

2
src/device/device.c
View File

@ -123,7 +123,7 @@ static struct device *__alloc_dev(struct bus *parent, struct device_path *path)
struct device *dev, *child;
/* Find the last child of our parent. */
for (child = parent->children; child && child->sibling; /* */ )
for (child = parent->children; child && child->sibling; /* */)
child = child->sibling;
dev = malloc(sizeof(*dev));

2
src/device/hypertransport.c
View File

@ -61,7 +61,7 @@ static struct device *ht_scan_get_devs(struct device **old_devices)
/* Now add the device to the list of devices on the bus. */
/* Find the last child of our parent. */
for (child = first->bus->children; child && child->sibling; )
for (child = first->bus->children; child && child->sibling;)
child = child->sibling;
/* Place the chain on the list of children of their parent. */

4
src/device/pciexp_device.c
View File

@ -275,7 +275,7 @@ static void pciexp_L1_substate_commit(struct device *root, struct device *dev,
pci_update_config32(root, root_cap + 0x08, ~0xff00,
(comm_mode_rst_time << 8));
pci_update_config32(root, root_cap + 0x0c , 0xffffff04,
pci_update_config32(root, root_cap + 0x0c, 0xffffff04,
(endp_power_on_value << 3) | (power_on_scale));
/* TODO: 0xa0, 2 are values that work on some chipsets but really
@ -291,7 +291,7 @@ static void pciexp_L1_substate_commit(struct device *root, struct device *dev,
L1SubStateSupport);
for (dev_t = dev; dev_t; dev_t = dev_t->sibling) {
pci_update_config32(dev_t, end_cap + 0x0c , 0xffffff04,
pci_update_config32(dev_t, end_cap + 0x0c, 0xffffff04,
(endp_power_on_value << 3) | (power_on_scale));
pci_update_config32(dev_t, end_cap + 0x08,

2
src/drivers/emulation/qemu/bochs.c
View File

@ -99,7 +99,7 @@ static void bochs_init_linear_fb(struct device *dev)
return;
printk(BIOS_DEBUG, "QEMU VGA: bochs dispi interface found, "
"%d MiB video memory\n", mem / ( 1024 * 1024));
"%d MiB video memory\n", mem / (1024 * 1024));
printk(BIOS_DEBUG, "QEMU VGA: framebuffer @ %x (pci bar %d)\n",
addr, bar);

2
src/drivers/intel/fsp1_0/hob.c
View File

@ -33,7 +33,7 @@ void printguid(EFI_GUID *guid)
guid->Data4[0], guid->Data4[1],
guid->Data4[2], guid->Data4[3],
guid->Data4[4], guid->Data4[5],
guid->Data4[6], guid->Data4[7] );
guid->Data4[6], guid->Data4[7]);
}
void print_hob_mem_attributes(void *Hobptr)

6
src/drivers/intel/fsp2_0/hand_off_block.c
View File

@ -139,7 +139,7 @@ struct hob_resource *find_resource_hob_by_guid(const struct hob_header *hob,
{
const struct hob_resource *res;
for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST;
for (; hob->type != HOB_TYPE_END_OF_HOB_LIST;
hob = fsp_next_hob(hob)) {
if (hob->type != HOB_TYPE_RESOURCE_DESCRIPTOR)
@ -202,7 +202,7 @@ const void *fsp_find_extension_hob_by_guid(const uint8_t *guid, size_t *size)
if (!hob)
return NULL;
for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST;
for (; hob->type != HOB_TYPE_END_OF_HOB_LIST;
hob = fsp_next_hob(hob)) {
if (hob->type != HOB_TYPE_GUID_EXTENSION)
@ -281,7 +281,7 @@ void fsp_display_fvi_version_hob(void)
if (!hob)
return;
for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST;
for (; hob->type != HOB_TYPE_END_OF_HOB_LIST;
hob = fsp_next_hob(hob)) {
if (hob->type != HOB_TYPE_GUID_EXTENSION)
continue;

2
src/drivers/intel/fsp2_0/hob_display.c
View File

@ -116,7 +116,7 @@ void fsp_print_memory_resource_hobs(void)
{
const struct hob_header *hob = fsp_get_hob_list();
for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST;
for (; hob->type != HOB_TYPE_END_OF_HOB_LIST;
hob = fsp_next_hob(hob)) {
if (hob->type == HOB_TYPE_RESOURCE_DESCRIPTOR)
fsp_print_resource_descriptor(hob);

14
src/drivers/intel/gma/edid.c
View File

@ -46,15 +46,15 @@ static void intel_gmbus_stop_bus(u8 *mmio, u8 bus)
wait_rdy(mmio);
write32(GMBUS5_ADDR, 0);
write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_WAIT | GMBUS_CYCLE_INDEX
| GMBUS_CYCLE_STOP | ( 0x4 << GMBUS_BYTE_COUNT_SHIFT )
| GMBUS_SLAVE_READ | (AT24_ADDR << 1) );
| GMBUS_CYCLE_STOP | (0x4 << GMBUS_BYTE_COUNT_SHIFT)
| GMBUS_SLAVE_READ | (AT24_ADDR << 1));
wait_rdy(mmio);
write32(GMBUS5_ADDR, 0);
write32(GMBUS1_ADDR, GMBUS_SW_CLR_INT);
write32(GMBUS1_ADDR, 0);
wait_rdy(mmio);
write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP | GMBUS_SLAVE_WRITE
| (AT24_ADDR << 1) );
| (AT24_ADDR << 1));
wait_rdy(mmio);
write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP);
write32(GMBUS2_ADDR, GMBUS_INUSE);
@ -80,13 +80,13 @@ void intel_gmbus_read_edid(u8 *mmio, u8 bus, u8 slave, u8 *edid, u32 edid_size)
/* Ensure index bits are disabled. */
write32(GMBUS5_ADDR, 0);
write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_WAIT | GMBUS_CYCLE_INDEX
| (slave << 1) );
| (slave << 1));
wait_rdy(mmio);
/* Ensure index bits are disabled. */
write32(GMBUS5_ADDR, 0);
write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_SLAVE_READ | GMBUS_CYCLE_WAIT
| GMBUS_CYCLE_STOP
| (edid_size << GMBUS_BYTE_COUNT_SHIFT) | (slave << 1) );
| (edid_size << GMBUS_BYTE_COUNT_SHIFT) | (slave << 1));
for (i = 0; i < edid_size / 4; i++) {
u32 reg32;
wait_rdy(mmio);
@ -99,9 +99,9 @@ void intel_gmbus_read_edid(u8 *mmio, u8 bus, u8 slave, u8 *edid, u32 edid_size)
wait_rdy(mmio);
write32(GMBUS1_ADDR, GMBUS_SW_RDY
| GMBUS_SLAVE_WRITE | GMBUS_CYCLE_WAIT | GMBUS_CYCLE_STOP
| (128 << GMBUS_BYTE_COUNT_SHIFT) | (slave << 1) );
| (128 << GMBUS_BYTE_COUNT_SHIFT) | (slave << 1));
wait_rdy(mmio);
write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP );
write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP);
write32(GMBUS2_ADDR, GMBUS_INUSE);
printk (BIOS_SPEW, "EDID:\n");

2
src/drivers/intel/wifi/wifi.c
View File

@ -173,7 +173,7 @@ static void emit_sar_acpi_structures(void)
acpigen_write_package(2);
acpigen_write_dword(wgds->version);
/* Emit 'Domain Type' +
* Group specific delta of power ( 6 bytes * NUM_WGDS_SAR_GROUPS )
* Group specific delta of power (6 bytes * NUM_WGDS_SAR_GROUPS)
*/
package_size = sizeof(sar_limits.wgds.group) + 1;
acpigen_write_package(package_size);

2
src/drivers/net/ne2k.c
View File

@ -287,7 +287,7 @@ int ne2k_init(unsigned int eth_nic_base) {
if (dev == PCI_DEV_INVALID)
return 0;
pci_write_config32(dev, 0x10, eth_nic_base | 1 );
pci_write_config32(dev, 0x10, eth_nic_base | 1);
pci_write_config8(dev, 0x4, 0x1);
c = inb(eth_nic_base + NE_ASIC_OFFSET + NE_RESET);

2
src/drivers/pc80/tpm/tis.c
View File

@ -46,7 +46,7 @@
#define TPM_DEBUG(fmt, args...) \
if (IS_ENABLED(CONFIG_DEBUG_TPM)) { \
printk(BIOS_DEBUG, PREFIX); \
printk(BIOS_DEBUG, fmt , ##args); \
printk(BIOS_DEBUG, fmt, ##args); \
}
#define TPM_DEBUG_IO_READ(reg_, val_) \
TPM_DEBUG("Read reg 0x%x returns 0x%x\n", (reg_), (val_))

2
src/drivers/spi/flashconsole.c
View File

@ -55,7 +55,7 @@ void flashconsole_init(void)
* the sector is already erased, so we would need to read
* anyways to check if it's all 0xff).
*/
for (i = 0; i < len && offset < size; ) {
for (i = 0; i < len && offset < size;) {
// Fill the buffer on first iteration
if (i == 0) {
len = min(READ_BUFFER_SIZE, size - offset);

2
src/drivers/xgi/common/vb_setmode.c
View File

@ -2799,7 +2799,7 @@ static void XGI_SetCRT2Offset(unsigned short ModeNo,
static void XGI_SetCRT2FIFO(struct vb_device_info *pVBInfo)
{
/* threshold high ,disable auto threshold */
/* threshold high, disable auto threshold */
xgifb_reg_set(pVBInfo->Part1Port, 0x01, 0x3B);
/* threshold low default 04h */
xgifb_reg_and_or(pVBInfo->Part1Port, 0x02, ~(0x3F), 0x04);

2
src/lib/edid.c
View File

@ -155,7 +155,7 @@ detailed_cvt_descriptor(unsigned char *x, int first)
printk(BIOS_SPEW, " (broken)\n");
} else {
printk(BIOS_SPEW,
" %dx%d @ ( %s%s%s%s%s) Hz (%s%s preferred)\n",
" %dx%d @ (%s%s%s%s%s) Hz (%s%s preferred)\n",
width, height,
fifty ? "50 " : "",
sixty ? "60 " : "",

2
src/lib/stack.c
View File

@ -1,5 +1,5 @@
/*
This software and ancillary information (herein called SOFTWARE )
This software and ancillary information (herein called SOFTWARE)
called LinuxBIOS is made available under the terms described
here. The SOFTWARE has been approved for release with associated
LA-CC Number 00-34 . Unless otherwise indicated, this SOFTWARE has

2
src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c
View File

@ -142,7 +142,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
FchParams->Imc.ImcEnable = TRUE;
FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */
FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */
FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */
LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader);

2
src/mainboard/amd/lamar/BiosCallOuts.c
View File

@ -159,7 +159,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
FchParams->Imc.ImcEnable = TRUE;
FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */
FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */
FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */
LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader);

2
src/mainboard/amd/olivehill/BiosCallOuts.c
View File

@ -111,7 +111,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
FchParams->Imc.ImcEnable = TRUE;
FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */
FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */
FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */
LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader);

2
src/mainboard/amd/olivehillplus/BiosCallOuts.c
View File

@ -125,7 +125,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
FchParams->Imc.ImcEnable = TRUE;
FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */
FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */
FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */
LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader);

2
src/mainboard/amd/parmer/BiosCallOuts.c
View File

@ -111,7 +111,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
FchParams->Imc.ImcEnable = TRUE;
FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */
FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */
FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */
LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader);

22
src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c
View File

@ -49,7 +49,7 @@ unsigned long acpi_fill_madt(unsigned long current)
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_1,
res->base, gsi_base );
res->base, gsi_base);
gsi_base+=7;
}
}
@ -58,7 +58,7 @@ unsigned long acpi_fill_madt(unsigned long current)
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_2,
res->base, gsi_base );
res->base, gsi_base);
gsi_base+=7;
}
}
@ -66,9 +66,10 @@ unsigned long acpi_fill_madt(unsigned long current)
int i;
int j = 0;
for(i = 1; i < sysconf.hc_possible_num; i++) {
for (i = 1; i < sysconf.hc_possible_num; i++) {
u32 d = 0;
if(!(sysconf.pci1234[i] & 0x1) ) continue;
if (!(sysconf.pci1234[i] & 0x1))
continue;
/* 8131 need to use +4 */
switch (sysconf.hcid[i]) {
case 1:
@ -86,7 +87,7 @@ unsigned long acpi_fill_madt(unsigned long current)
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][0],
res->base, gsi_base );
res->base, gsi_base);
gsi_base+=d;
}
}
@ -95,7 +96,7 @@ unsigned long acpi_fill_madt(unsigned long current)
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][1],
res->base, gsi_base );
res->base, gsi_base);
gsi_base+=d;
}
}
@ -105,7 +106,7 @@ unsigned long acpi_fill_madt(unsigned long current)
}
}
current += acpi_create_madt_irqoverride( (acpi_madt_irqoverride_t *) current, 0, 0, 2, 5 );
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 5);
/* 0: mean bus 0--->ISA */
/* 0: PIC 0 */
/* 2: APIC 2 */
@ -135,11 +136,12 @@ unsigned long mainboard_write_acpi_tables(struct device *device,
* change HCIN, and recalculate the checknum and add_table
*/
for(i = 1; i < sysconf.hc_possible_num; i++) { /* 0: is hc sblink */
for (i = 1; i < sysconf.hc_possible_num; i++) { /* 0: is hc sblink */
const char *file_name;
if((sysconf.pci1234[i] & 1) != 1 ) continue;
if ((sysconf.pci1234[i] & 1) != 1)
continue;
u8 c;
if(i < 7) {
if (i < 7) {
c = (u8) ('4' + i - 1);
}
else {

11
src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c
View File

@ -95,7 +95,7 @@ void get_bus_conf(void)
int i, j;
struct mb_sysconf_t *m;
if(get_bus_conf_done == 1)
if (get_bus_conf_done == 1)
return; /* do it only once */
get_bus_conf_done = 1;
@ -105,7 +105,7 @@ void get_bus_conf(void)
m = sysconf.mb;
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
for(i = 0; i < sysconf.hc_possible_num; i++) {
for (i = 0; i < sysconf.hc_possible_num; i++) {
sysconf.pci1234[i] = pci1234x[i];
sysconf.hcdn[i] = hcdnx[i];
}
@ -144,8 +144,9 @@ void get_bus_conf(void)
/* HT chain 1 */
j = 0;
for(i = 1; i< sysconf.hc_possible_num; i++) {
if(!(sysconf.pci1234[i] & 0x1) ) continue;
for (i = 1; i < sysconf.hc_possible_num; i++) {
if (!(sysconf.pci1234[i] & 0x1))
continue;
/* check hcid type here */
sysconf.hcid[i] = get_hcid(i);
@ -201,7 +202,7 @@ void get_bus_conf(void)
m->apicid_8111 = apicid_base + 0;
m->apicid_8132_1 = apicid_base + 1;
m->apicid_8132_2 = apicid_base + 2;
for(i = 0; i < j; i++) {
for (i = 0; i < j; i++) {
m->apicid_8132a[i][0] = apicid_base + 3 + i * 2;
m->apicid_8132a[i][1] = apicid_base + 3 + i * 2 + 1;
}

26
src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
View File

@ -67,8 +67,9 @@ static void *smp_write_config_table(void *v)
j = 0;
for(i = 1; i< sysconf.hc_possible_num; i++) {
if(!(sysconf.pci1234[i] & 0x1) ) continue;
for (i = 1; i < sysconf.hc_possible_num; i++) {
if (!(sysconf.pci1234[i] & 0x1))
continue;
switch(sysconf.hcid[i]) {
case 1:
@ -106,32 +107,33 @@ static void *smp_write_config_table(void *v)
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0 << 2)|3, m->apicid_8111, 0x13);
/* Slot 3 PCI 32 */
for(i = 0; i < 4; i++) {
for (i = 0; i < 4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5 << 2)|i, m->apicid_8111, 0x10 + (1+i)%4); /* 16 */
}
/* Slot 4 PCI 32 */
for(i = 0; i < 4; i++) {
for (i = 0; i < 4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4 << 2)|i, m->apicid_8111, 0x10 + (0+i)%4); /* 16 */
}
/* Slot 1 PCI-X 133/100/66 */
for(i = 0; i < 4; i++) {
for (i = 0; i < 4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1 << 2)|i, m->apicid_8132_2, (0+i)%4);
}
/* Slot 2 PCI-X 133/100/66 */
for(i = 0; i < 4; i++) {
for (i = 0; i < 4; i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1 << 2)|i, m->apicid_8132_1, (1+i)%4); /* 25 */
}
j = 0;
for(i = 1; i< sysconf.hc_possible_num; i++) {
if(!(sysconf.pci1234[i] & 0x1) ) continue;
for (i = 1; i < sysconf.hc_possible_num; i++) {
if (!(sysconf.pci1234[i] & 0x1))
continue;
int ii;
int jj;
struct device *dev;
@ -143,9 +145,9 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
for(jj = 0; jj < 4; jj++) {
for (jj = 0; jj < 4; jj++) {
/* Slot 1 PCI-X 133/100/66 */
for(ii = 0; ii < 4; ii++) {
for (ii = 0; ii < 4; ii++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (jj << 2)|ii, m->apicid_8132a[j][0], (jj+ii)%4);
}
}
@ -156,9 +158,9 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
for(jj = 0; jj < 4; jj++) {
for (jj = 0; jj < 4; jj++) {
/* Slot 2 PCI-X 133/100/66 */
for(ii = 0; ii < 4; ii++) {
for (ii = 0; ii < 4; ii++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (jj << 2)|ii, m->apicid_8132a[j][1], (jj+ii)%4); /* 25 */
}
}

2
src/mainboard/amd/thatcher/BiosCallOuts.c
View File

@ -111,7 +111,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
FchParams->Imc.ImcEnable = TRUE;
FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */
FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */
FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */
LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader);

6
src/mainboard/amd/tilapia_fam10/mainboard.c
View File

@ -149,7 +149,7 @@ static void set_gpio40_gfx(void)
dword &= ~(1 << 10);
/* When the gpio40 is configured as GPIO, this will represent the output value*/
/* 1 :enable two x8 , 0 : master slot enable only */
/* 1: enable two x8, 0: master slot enable only */
dword |= (1 << 26);
pci_write_config32(sm_dev, 0xfc, dword);
@ -161,7 +161,7 @@ static void set_gpio40_gfx(void)
dword &= ~(1 << 10);
/* When the gpio40 is configured as GPIO, this will represent the output value*/
/* 1 :enable two x8 , 0 : master slot enable only */
/* 1: enable two x8, 0: master slot enable only */
dword &= ~(1 << 26);
pci_write_config32(sm_dev, 0xfc, dword);
}
@ -187,7 +187,7 @@ static void set_thermal_config(void)
byte = ADT7461_read_byte(0x02); /* read status register to clear it */
ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */
printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte);
printk(BIOS_INFO, "Init adt7461 end, status 0x02 %02x\n", byte);
/* sb700 settings for thermal config */
/* set SB700 GPIO 64 to GPIO with pull-up */

2
src/mainboard/amd/torpedo/gpio.c
View File

@ -91,7 +91,7 @@ void gpioEarlyInit(void) {
Mmio8_And_Or (GpioMmioAddr, Index, 0xA3, gpio_table[Index].value);
}
if (Index == GPIO_65) {
if ( BoardType == 0 ) {
if (BoardType == 0) {
Mmio8_And_Or (IoMuxMmioAddr, GPIO_65, 0x00, 3); // function 3
}
}

2
src/mainboard/asus/am1i-a/BiosCallOuts.c
View File

@ -125,7 +125,7 @@ void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env)
/* Read SATA controller mode from CMOS */
enum cb_err ret;
ret = get_option(&FchParams_env->Sata.SataClass, "sata_mode");
if ( ret != CB_SUCCESS) {
if (ret != CB_SUCCESS) {
FchParams_env->Sata.SataClass = 0;
printk(BIOS_DEBUG, "ERROR: cannot read CMOS setting, falling back to default. Error code: %x\n", (int)ret);
}

4
src/mainboard/asus/m4a785-m/mainboard.c
View File

@ -133,7 +133,7 @@ static void set_thermal_config(void)
byte = ADT7461_read_byte(0x02); /* read status register to clear it */
ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */
printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte);
printk(BIOS_INFO, "Init adt7461 end, status 0x02 %02x\n", byte);
/* sb700 settings for thermal config */
/* set SB700 GPIO 64 to GPIO with pull-up */
@ -172,7 +172,7 @@ static void set_thermal_config(void)
* pm_iowrite(0x55, byte);
*
* byte = pm_ioread(0x67);
* byte &= ~( 1 << 6);
* byte &= ~(1 << 6);
* pm_iowrite(0x67, byte);
*/
}

2
src/mainboard/bap/ode_e20XX/BiosCallOuts.c
View File

@ -114,7 +114,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
FchParams->Imc.ImcEnable = TRUE;
FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */
FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */
FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */
LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader);

2
src/mainboard/bap/ode_e21XX/BiosCallOuts.c
View File

@ -127,7 +127,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
FchParams->Imc.ImcEnable = TRUE;
FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */
FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */
FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */
LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader);

2
src/mainboard/biostar/a68n_5200/BiosCallOuts.c
View File

@ -111,7 +111,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
FchParams->Imc.ImcEnable = TRUE;
FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */
FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */
FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */
LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader);

50
src/mainboard/biostar/am1ml/romstage.c
View File

@ -59,37 +59,37 @@ static void ite_exit_conf(pnp_devfn_t dev)
static void ite_evc_conf(pnp_devfn_t dev)
{
ite_enter_conf(dev);
it_sio_write(dev, 0xf1 , 0x40 );
it_sio_write(dev, 0xf4 , 0x80 );
it_sio_write(dev, 0xf5 , 0x00 );
it_sio_write(dev, 0xf6 , 0xf0 );
it_sio_write(dev, 0xf9 , 0x48 );
it_sio_write(dev, 0xfa , 0x00 );
it_sio_write(dev, 0xfb , 0x00 );
it_sio_write(dev, 0xf1, 0x40);
it_sio_write(dev, 0xf4, 0x80);
it_sio_write(dev, 0xf5, 0x00);
it_sio_write(dev, 0xf6, 0xf0);
it_sio_write(dev, 0xf9, 0x48);
it_sio_write(dev, 0xfa, 0x00);
it_sio_write(dev, 0xfb, 0x00);
ite_exit_conf(dev);
}
static void ite_gpio_conf(pnp_devfn_t dev)
{
ite_enter_conf (dev);
it_sio_write (dev, 0x25 , 0x80 );
it_sio_write (dev, 0x26 , 0x07 );
it_sio_write (dev, 0x28 , 0x81 );
it_sio_write (dev, 0x2c , 0x06 );
it_sio_write (dev, 0x72 , 0x00 );
it_sio_write (dev, 0x73 , 0x00 );
it_sio_write (dev, 0xb3 , 0x01 );
it_sio_write (dev, 0xb8 , 0x00 );
it_sio_write (dev, 0xc0 , 0x00 );
it_sio_write (dev, 0xc3 , 0x00 );
it_sio_write (dev, 0xc8 , 0x00 );
it_sio_write (dev, 0xc9 , 0x07 );
it_sio_write (dev, 0xcb , 0x01 );
it_sio_write (dev, 0xf0 , 0x10 );
it_sio_write (dev, 0xf4 , 0x27 );
it_sio_write (dev, 0xf8 , 0x20 );
it_sio_write (dev, 0xf9 , 0x01 );
ite_exit_conf (dev);
it_sio_write(dev, 0x25, 0x80);
it_sio_write(dev, 0x26, 0x07);
it_sio_write(dev, 0x28, 0x81);
it_sio_write(dev, 0x2c, 0x06);
it_sio_write(dev, 0x72, 0x00);
it_sio_write(dev, 0x73, 0x00);
it_sio_write(dev, 0xb3, 0x01);
it_sio_write(dev, 0xb8, 0x00);
it_sio_write(dev, 0xc0, 0x00);
it_sio_write(dev, 0xc3, 0x00);
it_sio_write(dev, 0xc8, 0x00);
it_sio_write(dev, 0xc9, 0x07);
it_sio_write(dev, 0xcb, 0x01);
it_sio_write(dev, 0xf0, 0x10);
it_sio_write(dev, 0xf4, 0x27);
it_sio_write(dev, 0xf8, 0x20);
it_sio_write(dev, 0xf9, 0x01);
ite_exit_conf(dev);
}
void board_BeforeAgesa(struct sysinfo *cb)

2
src/mainboard/esd/atom15/romstage.c
View File

@ -57,7 +57,7 @@ void late_mainboard_romstage_entry()
read_ssus_gpio(27),
read_ssus_gpio(28),
read_ssus_gpio(29),
read_ssus_gpio(30) );
read_ssus_gpio(30));
}

2
src/mainboard/gigabyte/ma785gmt/mainboard.c
View File

@ -226,7 +226,7 @@ static void set_thermal_config(void)
* pm_iowrite(0x55, byte);
*
* byte = pm_ioread(0x67);
* byte &= ~( 1 << 6);
* byte &= ~(1 << 6);
* pm_iowrite(0x67, byte);
*/
}

2
src/mainboard/gizmosphere/gizmo/OemCustomize.c
View File

@ -123,7 +123,7 @@ static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
#define WLSEED 0x08
#define RXSEED 0x40
WRITE_LEVELING_SEED(ANY_SOCKET, ANY_CHANNEL, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED),
HW_RXEN_SEED( ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED),
HW_RXEN_SEED(ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED),
PSO_END
};

2
src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c
View File

@ -111,7 +111,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
FchParams->Imc.ImcEnable = TRUE;
FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */
FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */
FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */
LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader);

8
src/mainboard/google/cyan/variants/banon/gpio.c
View File

@ -66,7 +66,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = {
GPIO_NC, /* 69 MMC1_RCLK */
Native_M1, /* 75 GPO USB_OC1_B */
Native_M1, /* 76 PMU_RESETBUTTON_B */
GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA),
GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA),
/* GPIO_ALERT 77 */
GPIO_NC, /* 78 SDMMC3_PWR_EN_B */
GPIO_NC, /* 79 GPI ILB_SERIRQ */
@ -127,9 +127,9 @@ static const struct soc_gpio_map gpsw_gpio_map[] = {
/* 76 GPI SATA_GP1 */
GPIO_INPUT_PU_20K, /* 77 SATA_LEDN */
GPIO_NC, /* 80 SATA_GP3 */
Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */
GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */
Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */
Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */
/* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */
Native_M1, /* 90 PCIE_CLKREQ0B */
@ -156,7 +156,7 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
GPIO_NC, /* 06 GPIO_DFX8 */
GPIO_NC, /* 07 GPIO_DFX2 */
GPIO_NC, /* 08 GPIO_DFX6 */
GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data ,
GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data,
UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */
GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),

8
src/mainboard/google/cyan/variants/celes/gpio.c
View File

@ -66,13 +66,13 @@ static const struct soc_gpio_map gpse_gpio_map[] = {
GPIO_NC, /* 69 MMC1_RCLK */
Native_M1, /* 75 GPO USB_OC1_B */
Native_M1, /* 76 PMU_RESETBUTTON_B */
GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA),
GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA),
/* GPIO_ALERT 77 */
Native_M1, /* 78 SDMMC3_PWR_EN_B */
GPIO_NC, /* 79 GPI ILB_SERIRQ */
Native_M1, /* 80 USB_OC0_B */
GPI(trig_edge_both, L1, P_20K_H, non_maskable,
en_edge_detect, NA , NA),
en_edge_detect, NA, NA),
/* 81 SDMMC3_CD_B */
GPIO_NC, /* 82 spkr assumed gpio number */
Native_M1, /* 83 SUSPWRDNACK */
@ -132,7 +132,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = {
GPIO_NC, /* 78 SATA_GP2 */
GPIO_NC, /* 79 MF_SMB_ALERTB */
GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */
GPIO_NC, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
GPIO_NC, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */
GPIO_NC, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */
/* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */
Native_M1, /* 90 PCIE_CLKREQ0B */
@ -159,7 +159,7 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
GPIO_NC, /* 06 GPIO_DFX8 */
GPIO_NC, /* 07 GPIO_DFX2 */
GPIO_NC, /* 08 GPIO_DFX6 */
GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data ,
GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data,
UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */
GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),

6
src/mainboard/google/cyan/variants/cyan/gpio.c
View File

@ -66,7 +66,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = {
GPIO_NC, /* 69 MMC1_RCLK */
Native_M1, /* 75 GPO USB_OC1_B */
Native_M1, /* 76 PMU_RESETBUTTON_B */
GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA),
GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA),
/* GPIO_ALERT 77 */
Native_M1, /* 78 SDMMC3_PWR_EN_B */
GPIO_NC, /* 79 GPI ILB_SERIRQ */
@ -130,7 +130,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = {
GPIO_NC, /* 78 HSIC AUX1 / SV Mode/ SATA_GP2 */
Native_M1, /* 79 MF_SMB_ALERTB */
GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */
Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */
Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */
/* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */
Native_M1, /* 90 PCIE_CLKREQ0B */
@ -159,7 +159,7 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
GPIO_NC, /* 06 GPIO_DFX8 */
GPIO_NC, /* 07 GPIO_DFX2 */
GPIO_NC, /* 08 GPIO_DFX6 */
GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data ,
GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data,
UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */
GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),

6
src/mainboard/google/cyan/variants/edgar/gpio.c
View File

@ -66,7 +66,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = {
GPIO_NC, /* 69 MMC1_RCLK */
Native_M1, /* 75 GPO USB_OC1_B */
Native_M1, /* 76 PMU_RESETBUTTON_B */
GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA),
GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA),
/* GPIO_ALERT 77 */
Native_M1, /* 78 SDMMC3_PWR_EN_B */
GPIO_NC, /* 79 GPI ILB_SERIRQ */
@ -129,7 +129,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = {
GPIO_NC, /* 78 SATA_GP2 */
Native_M1, /* 79 MF_SMB_ALERTB */
GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */
Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */
Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */
/* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */
GPIO_INPUT_PU_20K, /* 90 PCIE_CLKREQ0B */
@ -156,7 +156,7 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
GPIO_NC, /* 06 GPIO_DFX8 */
GPIO_NC, /* 07 GPIO_DFX2 */
GPIO_NC, /* 08 GPIO_DFX6 */
GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data ,
GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data,
UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */
GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),

6
src/mainboard/google/cyan/variants/kefka/gpio.c
View File

@ -67,7 +67,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = {
GPIO_NC, /* 69 MMC1_RCLK */
Native_M1, /* 75 GPO USB_OC1_B */
Native_M1, /* 76 PMU_RESETBUTTON_B */
GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA),
GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA),
/* GPIO_ALERT 77 */
Native_M1, /* 78 SDMMC3_PWR_EN_B */
GPIO_NC, /* 79 GPI ILB_SERIRQ */
@ -129,7 +129,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = {
GPIO_NC, /* 78 SATA_GP2 */
Native_M1, /* 79 MF_SMB_ALERTB */
GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */
Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */
Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */
/* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */
GPIO_NC, /* 90 PCIE_CLKREQ0B */
@ -156,7 +156,7 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
GPIO_NC, /* 06 GPIO_DFX8 */
GPIO_NC, /* 07 GPIO_DFX2 */
GPIO_NC, /* 08 GPIO_DFX6 */
GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data ,
GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data,
UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */
GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),

8
src/mainboard/google/cyan/variants/reks/gpio.c
View File

@ -66,7 +66,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = {
GPIO_NC, /* 69 MMC1_RCLK */
Native_M1, /* 75 GPO USB_OC1_B */
Native_M1, /* 76 PMU_RESETBUTTON_B */
GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA),
GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA),
/* GPIO_ALERT 77 */
Native_M1, /* 78 SDMMC3_PWR_EN_B */
GPIO_NC, /* 79 GPI ILB_SERIRQ */
@ -129,9 +129,9 @@ static const struct soc_gpio_map gpsw_gpio_map[] = {
/* 76 GPI SATA_GP1 */
GPIO_INPUT_PU_20K, /* 77 SATA_LEDN-> EC_IN_RW */
GPIO_NC, /* 80 SATA_GP3 */
Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */
GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */
Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */
Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */
/* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */
Native_M1, /* 90 PCIE_CLKREQ0B */
@ -158,7 +158,7 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
GPIO_NC, /* 06 GPIO_DFX8 */
GPIO_NC, /* 07 GPIO_DFX2 */
GPIO_NC, /* 08 GPIO_DFX6 */
GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data ,
GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data,
UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */
GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),

8
src/mainboard/google/cyan/variants/relm/gpio.c
View File

@ -67,7 +67,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = {
GPIO_NC, /* 69 MMC1_RCLK */
Native_M1, /* 75 GPO USB_OC1_B */
Native_M1, /* 76 PMU_RESETBUTTON_B */
GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA),
GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA),
/* GPIO_ALERT 77 */
Native_M1, /* 78 SDMMC3_PWR_EN_B */
GPIO_NC, /* 79 GPI ILB_SERIRQ */
@ -130,9 +130,9 @@ static const struct soc_gpio_map gpsw_gpio_map[] = {
/* 76 GPI SATA_GP1 */
GPIO_INPUT_PU_20K, /* 77 SATA_LEDN */
GPIO_NC, /* 80 SATA_GP3 */
Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */
GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */
Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */
Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */
/* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */
Native_M1, /* 90 PCIE_CLKREQ0B */
@ -159,7 +159,7 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
GPIO_NC, /* 06 GPIO_DFX8 */
GPIO_NC, /* 07 GPIO_DFX2 */
GPIO_NC, /* 08 GPIO_DFX6 */
GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data ,
GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data,
UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */
GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),

8
src/mainboard/google/cyan/variants/setzer/gpio.c
View File

@ -67,7 +67,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = {
GPIO_NC, /* 69 MMC1_RCLK */
Native_M1, /* 75 GPO USB_OC1_B */
Native_M1, /* 76 PMU_RESETBUTTON_B */
GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA),
GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA),
/* GPIO_ALERT 77 */
Native_M1, /* 78 SDMMC3_PWR_EN_B */
GPIO_NC, /* 79 GPI ILB_SERIRQ */
@ -128,9 +128,9 @@ static const struct soc_gpio_map gpsw_gpio_map[] = {
/* 76 GPI SATA_GP1 */
GPIO_INPUT_PU_20K, /* 77 SATA_LEDN */
GPIO_NC, /* 78 SATA_GP2 */
Native_M1, /* 79 NFC_DEV_WAKE , MF_SMB_CLK */
Native_M1, /* 79 NFC_DEV_WAKE, MF_SMB_CLK */
GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID3 */
Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */
Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */
/* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */
GPIO_NC, /* 90 PCIE_CLKREQ0B */
@ -157,7 +157,7 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
GPIO_NC, /* 06 GPIO_DFX8 */
GPIO_NC, /* 07 GPIO_DFX2 */
GPIO_NC, /* 08 GPIO_DFX6 */
GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data ,
GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data,
UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */
GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),

6
src/mainboard/google/cyan/variants/terra/gpio.c
View File

@ -66,7 +66,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = {
GPIO_NC, /* 69 MMC1_RCLK */
Native_M1, /* 75 GPO USB_OC1_B */
Native_M1, /* 76 PMU_RESETBUTTON_B */
GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA),
GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA),
/* GPIO_ALERT 77 */
Native_M1, /* 78 SDMMC3_PWR_EN_B */
GPIO_NC, /* 79 GPI ILB_SERIRQ */
@ -128,7 +128,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = {
GPIO_NC, /* 78 SATA_GP2 */
GPIO_NC, /* 79 MF_SMB_ALERTB */
GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */
Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */
Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */
/* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */
Native_M1, /* 90 PCIE_CLKREQ0B */
@ -155,7 +155,7 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
GPIO_NC, /* 06 GPIO_DFX8 */
GPIO_NC, /* 07 GPIO_DFX2 */
GPIO_NC, /* 08 GPIO_DFX6 */
GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data ,
GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data,
UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */
GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),

8
src/mainboard/google/cyan/variants/ultima/gpio.c
View File

@ -66,7 +66,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = {
GPIO_NC, /* 69 MMC1_RCLK */
Native_M1, /* 75 GPO USB_OC1_B */
Native_M1, /* 76 PMU_RESETBUTTON_B */
GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA),
GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA),
/* GPIO_ALERT 77 */
Native_M1, /* 78 SDMMC3_PWR_EN_B */
GPIO_NC, /* 79 GPI ILB_SERIRQ */
@ -129,9 +129,9 @@ static const struct soc_gpio_map gpsw_gpio_map[] = {
/* 76 GPI SATA_GP1 */
GPIO_INPUT_PU_20K, /* 77 SATA_LEDN-> EC_IN_RW */
GPIO_NC, /* 80 SATA_GP3 */
Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */
GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */
Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */
Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */
/* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */
Native_M1, /* 90 PCIE_CLKREQ0B */
@ -158,7 +158,7 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
GPIO_NC, /* 06 GPIO_DFX8 */
GPIO_NC, /* 07 GPIO_DFX2 */
GPIO_NC, /* 08 GPIO_DFX6 */
GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data ,
GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data,
UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */
GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),

8
src/mainboard/google/cyan/variants/wizpig/gpio.c
View File

@ -66,7 +66,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = {
GPIO_NC, /* 69 MMC1_RCLK */
Native_M1, /* 75 GPO USB_OC1_B */
Native_M1, /* 76 PMU_RESETBUTTON_B */
GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA),
GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA),
/* GPIO_ALERT 77 */
Native_M1, /* 78 SDMMC3_PWR_EN_B */
GPIO_NC, /* 79 GPI ILB_SERIRQ */
@ -128,9 +128,9 @@ static const struct soc_gpio_map gpsw_gpio_map[] = {
GPIO_NC, /* 76 GPI SATA_GP1 */
GPIO_INPUT_PU_20K, /* 77 SATA_LEDN */
GPIO_NC, /* 78 SATA_GP2 */
Native_M1, /* 79 NFC_DEV_WAKE , MF_SMB_CLK */
Native_M1, /* 79 NFC_DEV_WAKE, MF_SMB_CLK */
GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */
Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */
Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */
/* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */
GPIO_NC, /* 90 PCIE_CLKREQ0B */
@ -157,7 +157,7 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
GPIO_NC, /* 06 GPIO_DFX8 */
GPIO_NC, /* 07 GPIO_DFX2 */
GPIO_NC, /* 08 GPIO_DFX6 */
GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data ,
GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data,
UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */
GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),

2
src/mainboard/google/eve/romstage.c
View File

@ -27,7 +27,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
/* DQ byte map */
const u8 dq_map[2][12] = {
{ 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0 ,
{ 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },
{ 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC,
0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };

4
src/mainboard/google/glados/variants/lars/variant.c
View File

@ -33,9 +33,9 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
{
/* DQ byte map */
const u8 dq_map[2][12] = {
{ 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0 ,
{ 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },
{ 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0 ,
{ 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };
/* DQS CPU<>DRAM map */
const u8 dqs_map[2][8] = {

2
src/mainboard/google/gru/boardid.c
View File

@ -65,7 +65,7 @@ static uint32_t get_index(uint32_t channel, int *cached_id)
}
}
die("Read impossible value ( > 1023) from 10-bit ADC!");
die("Read impossible value (> 1023) from 10-bit ADC!");
}
uint32_t board_id(void)

2
src/mainboard/google/link/i915.c
View File

@ -295,7 +295,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
index = run(index);
auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_LINK_BW_SET << 8|0x8;
auxout[1] = 0x0a840000;
/*( DP_LINK_BW_2_7 &0xa)|0x0000840a*/
/*(DP_LINK_BW_2_7 &0xa)|0x0000840a*/
auxout[2] = 0x00000000;
auxout[3] = 0x01000000;
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 13, auxin, 0);

2
src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c
View File

@ -112,7 +112,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
FchParams->Imc.ImcEnable = TRUE;
FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */
FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */
FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */
LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader);

6
src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
View File

@ -365,9 +365,9 @@ GPIO_CONTROL pavilion_m6_1035dx_gpio[] = {
#define SCI_MAP_PWRBTN 0x73
SCI_MAP_CONTROL m6_1035dx_sci_map[] = {
{GEVENT_PIN( EC_SCI_GEVENT ), EC_SCI_GPE},
{GEVENT_PIN( EC_LID_GEVENT ), EC_LID_GPE},
{GEVENT_PIN( PCIE_GEVENT ), PCIE_GPE},
{GEVENT_PIN(EC_SCI_GEVENT), EC_SCI_GPE},
{GEVENT_PIN(EC_LID_GEVENT), EC_LID_GPE},
{GEVENT_PIN(PCIE_GEVENT), PCIE_GPE},
{SCI_MAP_OHCI_12_0, PME_GPE},
{SCI_MAP_OHCI_13_0, PME_GPE},
{SCI_MAP_XHCI_10_0, PME_GPE},

26
src/mainboard/intel/bayleybay_fsp/romstage.c
View File

@ -65,67 +65,67 @@ const uint32_t mAzaliaVerbTableData13[] = {
/*
*ALC262 Verb Table - 10EC0262
*/
/* Pin Complex (NID 0x11 ) */
/* Pin Complex (NID 0x11) */
0x01171CF0,
0x01171D11,
0x01171E11,
0x01171F41,
/* Pin Complex (NID 0x12 ) */
/* Pin Complex (NID 0x12) */
0x01271CF0,
0x01271D11,
0x01271E11,
0x01271F41,
/* Pin Complex (NID 0x14 ) */
/* Pin Complex (NID 0x14) */
0x01471C10,
0x01471D40,
0x01471E01,
0x01471F01,
/* Pin Complex (NID 0x15 ) */
/* Pin Complex (NID 0x15) */
0x01571CF0,
0x01571D11,
0x01571E11,
0x01571F41,
/* Pin Complex (NID 0x16 ) */
/* Pin Complex (NID 0x16) */
0x01671CF0,
0x01671D11,
0x01671E11,
0x01671F41,
/* Pin Complex (NID 0x18 ) */
/* Pin Complex (NID 0x18) */
0x01871C20,
0x01871D98,
0x01871EA1,
0x01871F01,
/* Pin Complex (NID 0x19 ) */
/* Pin Complex (NID 0x19) */
0x01971C21,
0x01971D98,
0x01971EA1,
0x01971F02,
/* Pin Complex (NID 0x1A ) */
/* Pin Complex (NID 0x1A) */
0x01A71C2F,
0x01A71D30,
0x01A71E81,
0x01A71F01,
/* Pin Complex (NID 0x1B ) */
/* Pin Complex (NID 0x1B) */
0x01B71C1F,
0x01B71D40,
0x01B71E21,
0x01B71F02,
/* Pin Complex (NID 0x1C ) */
/* Pin Complex (NID 0x1C) */
0x01C71CF0,
0x01C71D11,
0x01C71E11,
0x01C71F41,
/* Pin Complex (NID 0x1D ) */
/* Pin Complex (NID 0x1D) */
0x01D71C01,
0x01D71DC6,
0x01D71E14,
0x01D71F40,
/* Pin Complex (NID 0x1E ) */
/* Pin Complex (NID 0x1E) */
0x01E71CF0,
0x01E71D11,
0x01E71E11,
0x01E71F41,
/* Pin Complex (NID 0x1F ) */
/* Pin Complex (NID 0x1F) */
0x01F71CF0,
0x01F71D11,
0x01F71E11,

2
src/mainboard/intel/cannonlake_rvp/spd/spd_util.c
View File

@ -23,7 +23,7 @@ void mainboard_fill_dq_map_ch0(void *dq_map_ptr)
{
/* DQ byte map Ch0 */
const u8 dq_map[12] = {
0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00 ,
0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
memcpy(dq_map_ptr, dq_map, sizeof(dq_map));

2
src/mainboard/intel/cougar_canyon2/romstage.c
View File

@ -261,7 +261,7 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) {
/* For reference print FSP version */
u32 version = MCHBAR32(0x5034);
printk(BIOS_DEBUG, "FSP Version %d.%d.%d Build %d\n",
version >> 24 , (version >> 16) & 0xff,
version >> 24, (version >> 16) & 0xff,
(version >> 8) & 0xff, version & 0xff);
printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status);

4
src/mainboard/intel/kunimitsu/spd/spd_util.c
View File

@ -26,9 +26,9 @@ void mainboard_fill_dq_map_data(void *dq_map_ptr)
{
/* DQ byte map */
const u8 dq_map[2][12] = {
{ 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0 ,
{ 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },
{ 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0 ,
{ 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };
memcpy(dq_map_ptr, dq_map, sizeof(dq_map));
}

10
src/mainboard/intel/strago/gpio.c
View File

@ -69,7 +69,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = {
GPIO_NC, /* 69 MMC1_RCLK */
Native_M1, /* 75 GPO USB_OC1_B */
Native_M1, /* 76 PMU_RESETBUTTON_B */
GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA),
GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA),
/* GPIO_ALERT 77 */
Native_M1, /* 78 SDMMC3_PWR_EN_B */
GPIO_NC, /* 79 GPI ILB_SERIRQ */
@ -131,11 +131,11 @@ static const struct soc_gpio_map gpsw_gpio_map[] = {
GPIO_OUT_HIGH, /* 75 SATA_GP0 */
GPIO_NC,
/* 76 GPI SATA_GP1 */
GPIO_INPUT_PU_20K, /* 77 SATA_LEDN , EC_IN_RW */
GPIO_INPUT_PU_20K, /* 77 SATA_LEDN, EC_IN_RW */
GPIO_NC, /* 80 SATA_GP3 */
Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */
GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */
Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */
Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */
/* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */
Native_M1, /* 90 PCIE_CLKREQ0B */
@ -162,7 +162,7 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
GPIO_NC, /* 06 GPIO_DFX8 */
GPIO_NC, /* 07 GPIO_DFX2 */
GPIO_NC, /* 08 GPIO_DFX6 */
GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data ,
GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data,
UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */
GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),

2
src/mainboard/lenovo/g505s/BiosCallOuts.c
View File

@ -112,7 +112,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
FchParams->Imc.ImcEnable = TRUE;
FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */
FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */
FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */
LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader);

6
src/mainboard/lenovo/g505s/buildOpts.c
View File

@ -365,9 +365,9 @@ GPIO_CONTROL lenovo_g505s_gpio[] = {
#define SCI_MAP_PWRBTN 0x73
SCI_MAP_CONTROL lenovo_g505s_sci_map[] = {
{GEVENT_PIN( EC_SCI_GEVENT ), EC_SCI_GPE},
{GEVENT_PIN( EC_LID_GEVENT ), EC_LID_GPE},
{GEVENT_PIN( PCIE_GEVENT ), PCIE_GPE},
{GEVENT_PIN(EC_SCI_GEVENT), EC_SCI_GPE},
{GEVENT_PIN(EC_LID_GEVENT), EC_LID_GPE},
{GEVENT_PIN(PCIE_GEVENT), PCIE_GPE},
{SCI_MAP_OHCI_12_0, PME_GPE},
{SCI_MAP_OHCI_13_0, PME_GPE},
{SCI_MAP_XHCI_10_0, PME_GPE},

2
src/mainboard/lenovo/t430s/romstage.c
View File

@ -43,7 +43,7 @@ void mainboard_rcba_config(void)
}
const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 0, 0 }, /* P0: , OC 0 */
{ 1, 0, 0 }, /* P0:, OC 0 */
{ 1, 1, 1 }, /* P1: (EHCI debug), OC 1 */
{ 1, 1, 3 }, /* P2: OC 3 */
{ 1, 0, -1 }, /* P3: no OC */

2
src/mainboard/lenovo/t60/romstage.c
View File

@ -183,7 +183,7 @@ void mainboard_romstage_entry(unsigned long bist)
/* We want early GPIO setup, to be able to detect legacy I/O module */
pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1);
/* Enable GPIOs */
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */ , 0x10);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */, 0x10);
setup_pch_gpios(&mainboard_gpio_map);
dock_err = dlpc_init();

2
src/mainboard/lenovo/t60/smihandler.c
View File

@ -49,7 +49,7 @@ static void mainboard_smi_brightness_up(void)
{
u8 *bar;
if ((bar = (u8 *)pci_read_config32(PCI_DEV(1, 0, 0), 0x18))) {
printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int )bar, *(bar+LVTMA_BL_MOD_LEVEL));
printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, *(bar+LVTMA_BL_MOD_LEVEL));
*(bar+LVTMA_BL_MOD_LEVEL) |= 0x0f;
if (*(bar+LVTMA_BL_MOD_LEVEL) < 0xf0)
*(bar+LVTMA_BL_MOD_LEVEL) += 0x10;

2
src/mainboard/lenovo/x60/dock.c
View File

@ -190,7 +190,7 @@ int dock_connect(void)
dock_gpio_set_mode(0x14, PC87392_GPIO_PIN_PULLUP, 0x00);
dock_gpio_set_mode(0x15, PC87392_GPIO_PIN_PULLUP, 0x00);
dock_gpio_set_mode(0x16, PC87392_GPIO_PIN_PULLUP |
PC87392_GPIO_PIN_OE , 0x00);
PC87392_GPIO_PIN_OE, 0x00);
dock_gpio_set_mode(0x17, PC87392_GPIO_PIN_PULLUP, 0x00);

2
src/mainboard/lenovo/z61t/romstage.c
View File

@ -183,7 +183,7 @@ void mainboard_romstage_entry(unsigned long bist)
/* We want early GPIO setup, to be able to detect legacy I/O module */
pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1);
/* Enable GPIOs */
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */ , 0x10);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */, 0x10);
setup_pch_gpios(&mainboard_gpio_map);
dock_err = dlpc_init();

2
src/mainboard/lenovo/z61t/smihandler.c
View File

@ -50,7 +50,7 @@ static void mainboard_smi_brightness_up(void)
{
u8 *bar;
if ((bar = (u8 *)pci_read_config32(PCI_DEV(1, 0, 0), 0x18))) {
printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int )bar,
printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar,
*(bar+LVTMA_BL_MOD_LEVEL));
*(bar+LVTMA_BL_MOD_LEVEL) |= 0x0f;
if (*(bar+LVTMA_BL_MOD_LEVEL) < 0xf0)

24
src/mainboard/lippert/frontrunner-af/mainboard.c
View File

@ -65,19 +65,19 @@ static void init(struct device *dev)
/* Init Hudson GPIOs. */
printk(BIOS_DEBUG, "Init FCH GPIOs @ 0x%08x\n", ACPI_MMIO_BASE+GPIO_BASE);
FCH_IOMUX( 50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices
FCH_GPIO ( 50) = 0xC0; // = output set to 1 as it's never needed
FCH_IOMUX(50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices
FCH_GPIO (50) = 0xC0; // = output set to 1 as it's never needed
FCH_IOMUX(197) = 2; // GPIO197: BIOS_DEFAULTS# = input (int. PU)
FCH_IOMUX( 56) = 1; // GPIO58-56: REV_ID2-0
FCH_GPIO ( 56) = 0x28; // = inputs, disable int. pull-ups
FCH_IOMUX( 57) = 1;
FCH_GPIO ( 57) = 0x28;
FCH_IOMUX( 58) = 1;
FCH_GPIO ( 58) = 0x28;
FCH_IOMUX( 96) = 1; // "Gpio96": GEVENT0# signal on X2 connector (int. PU)
FCH_IOMUX( 52) = 1; // GPIO52,61,62,187-192 free to use on X2 connector
FCH_IOMUX( 61) = 2; // default to inputs with int. PU
FCH_IOMUX( 62) = 2;
FCH_IOMUX(56) = 1; // GPIO58-56: REV_ID2-0
FCH_GPIO (56) = 0x28; // = inputs, disable int. pull-ups
FCH_IOMUX(57) = 1;
FCH_GPIO (57) = 0x28;
FCH_IOMUX(58) = 1;
FCH_GPIO (58) = 0x28;
FCH_IOMUX(96) = 1; // "Gpio96": GEVENT0# signal on X2 connector (int. PU)
FCH_IOMUX(52) = 1; // GPIO52,61,62,187-192 free to use on X2 connector
FCH_IOMUX(61) = 2; // default to inputs with int. PU
FCH_IOMUX(62) = 2;
FCH_IOMUX(187) = 2;
FCH_IOMUX(188) = 2;
FCH_IOMUX(189) = 1;

16
src/mainboard/lippert/toucan-af/mainboard.c
View File

@ -33,16 +33,16 @@ static void init(struct device *dev)
/* Init Hudson GPIOs. */
printk(BIOS_DEBUG, "Init FCH GPIOs @ 0x%08x\n", ACPI_MMIO_BASE+GPIO_BASE);
FCH_IOMUX( 50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices
FCH_GPIO ( 50) = 0xC0; // = output set to 1 as it's never needed
FCH_IOMUX(50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices
FCH_GPIO (50) = 0xC0; // = output set to 1 as it's never needed
FCH_IOMUX(197) = 2; // GPIO197: BIOS_DEFAULTS#
FCH_GPIO (197) = 0x28; // = input, disable int. pull-up
FCH_IOMUX( 56) = 1; // GPIO58-56: REV_ID2-0
FCH_GPIO ( 56) = 0x28; // = inputs, disable int. pull-ups
FCH_IOMUX( 57) = 1;
FCH_GPIO ( 57) = 0x28;
FCH_IOMUX( 58) = 1;
FCH_GPIO ( 58) = 0x28;
FCH_IOMUX(56) = 1; // GPIO58-56: REV_ID2-0
FCH_GPIO (56) = 0x28; // = inputs, disable int. pull-ups
FCH_IOMUX(57) = 1;
FCH_GPIO (57) = 0x28;
FCH_IOMUX(58) = 1;
FCH_GPIO (58) = 0x28;
FCH_IOMUX(187) = 2; // GPIO187,188,166,GPO160: GPO0-3 on COM Express connector
FCH_GPIO (187) = 0x08; // = outputs, disable PUs, default to 0
FCH_IOMUX(188) = 2;

4
src/mainboard/msi/ms9652_fam10/get_bus_conf.c
View File

@ -101,12 +101,12 @@ void get_bus_conf(void)
}
for (i = 2; i < 8; i++) {
dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0));
dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0));
if (dev) {
m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 );
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2);
}
}

8
src/mainboard/msi/ms9652_fam10/romstage.c
View File

@ -87,13 +87,13 @@ static void sio_setup(void)
u32 dword;
u8 byte;
byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0x7b);
byte |= 0x20;
pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0x7b, byte);
dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa0);
dword |= (1 << 0);
pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa0, dword);
}
static const u8 spd_addr[] = {

2
src/mainboard/pcengines/alix1c/romstage.c
View File

@ -44,7 +44,7 @@
* 4banks (2)
* SSTL_2 (2)
* 4th GEN die (C)
* Normal Power Consumption (<blank> )
* Normal Power Consumption (<blank>)
* TSOP (T)
* Single Die (<blank>)
* Lead Free (P)

2
src/mainboard/pcengines/alix2d/romstage.c
View File

@ -42,7 +42,7 @@
* 4banks (2)
* SSTL_2 (2)
* 4th GEN die (C)
* Normal Power Consumption (<blank> )
* Normal Power Consumption (<blank>)
* TSOP (T)
* Single Die (<blank>)
* Lead Free (P)

2
src/mainboard/pcengines/apu1/OemCustomize.c
View File

@ -108,7 +108,7 @@ static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
#define WLSEED 0x08
#define RXSEED 0x40
WRITE_LEVELING_SEED(ANY_SOCKET, ANY_CHANNEL, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED),
HW_RXEN_SEED( ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED),
HW_RXEN_SEED(ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED),
PSO_END
};

6
src/mainboard/pcengines/apu1/gpio_ftns.c
View File

@ -25,9 +25,9 @@ uintptr_t find_gpio_base(void)
uintptr_t base_addr = 0;
/* Find the ACPImmioAddr base address */
for ( pm_index = 0x27; pm_index > 0x23; pm_index-- ) {
outb( pm_index, PM_INDEX );
pm_data = inb( PM_DATA );
for (pm_index = 0x27; pm_index > 0x23; pm_index--) {
outb(pm_index, PM_INDEX);
pm_data = inb(PM_DATA);
base_addr <<= 8;
base_addr |= (u32)pm_data;
}

2
src/mainboard/pcengines/apu2/BiosCallOuts.c
View File

@ -99,7 +99,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
FchParams->Usb.Ehci1Enable = TRUE;
}
// Enable EHCI 1 ( port 4 to 7)
// Enable EHCI 1 (port 4 to 7)
// port 4 and 5 to EHCI header port 6 and 7 to PCIe slot.
FchParams->Usb.Ehci2Enable = TRUE;

4
src/mainboard/pcengines/apu2/mainboard.c
View File

@ -167,12 +167,12 @@ static void mainboard_enable(struct device *dev)
//
// Enable the RTC output
//
pm_write16 ( PM_RTC_CONTROL, pm_read16( PM_RTC_CONTROL ) | (1 << 11));
pm_write16(PM_RTC_CONTROL, pm_read16(PM_RTC_CONTROL) | (1 << 11));
//
// Enable power on from WAKE#
//
pm_write16 ( PM_S_STATE_CONTROL, pm_read16( PM_S_STATE_CONTROL ) | (1 << 14));
pm_write16(PM_S_STATE_CONTROL, pm_read16(PM_S_STATE_CONTROL) | (1 << 14));
/* Initialize the PIRQ data structures for consumption */
pirq_setup();

2
src/mainboard/siemens/mc_tcu3/ptn3460.c
View File

@ -53,7 +53,7 @@ int ptn3460_init(char *hwi_block)
hwi_block);
return 1;
}
if (hwilib_get_field(PF_Color_Depth ,&color_depth, 1) != 1) {
if (hwilib_get_field(PF_Color_Depth, &color_depth, 1) != 1) {
printk(BIOS_ERR, "LCD: Missing panel features from %s\n",
hwi_block);
return 1;

26
src/mainboard/siemens/mc_tcu3/romstage.c
View File

@ -66,67 +66,67 @@ const uint32_t mAzaliaVerbTableData13[] = {
/*
*ALC262 Verb Table - 10EC0262
*/
/* Pin Complex (NID 0x11 ) */
/* Pin Complex (NID 0x11) */
0x01171CF0,
0x01171D11,
0x01171E11,
0x01171F41,
/* Pin Complex (NID 0x12 ) */
/* Pin Complex (NID 0x12) */
0x01271CF0,
0x01271D11,
0x01271E11,
0x01271F41,
/* Pin Complex (NID 0x14 ) */
/* Pin Complex (NID 0x14) */
0x01471C10,
0x01471D40,
0x01471E01,
0x01471F01,
/* Pin Complex (NID 0x15 ) */
/* Pin Complex (NID 0x15) */
0x01571CF0,
0x01571D11,
0x01571E11,
0x01571F41,
/* Pin Complex (NID 0x16 ) */
/* Pin Complex (NID 0x16) */
0x01671CF0,
0x01671D11,
0x01671E11,
0x01671F41,
/* Pin Complex (NID 0x18 ) */
/* Pin Complex (NID 0x18) */
0x01871C20,
0x01871D98,
0x01871EA1,
0x01871F01,
/* Pin Complex (NID 0x19 ) */
/* Pin Complex (NID 0x19) */
0x01971C21,
0x01971D98,
0x01971EA1,
0x01971F02,
/* Pin Complex (NID 0x1A ) */
/* Pin Complex (NID 0x1A) */
0x01A71C2F,
0x01A71D30,
0x01A71E81,
0x01A71F01,
/* Pin Complex (NID 0x1B ) */
/* Pin Complex (NID 0x1B) */
0x01B71C1F,
0x01B71D40,
0x01B71E21,
0x01B71F02,
/* Pin Complex (NID 0x1C ) */
/* Pin Complex (NID 0x1C) */
0x01C71CF0,
0x01C71D11,
0x01C71E11,
0x01C71F41,
/* Pin Complex (NID 0x1D ) */
/* Pin Complex (NID 0x1D) */
0x01D71C01,
0x01D71DC6,
0x01D71E14,
0x01D71F40,
/* Pin Complex (NID 0x1E ) */
/* Pin Complex (NID 0x1E) */
0x01E71CF0,
0x01E71D11,
0x01E71E11,
0x01E71F41,
/* Pin Complex (NID 0x1F ) */
/* Pin Complex (NID 0x1F) */
0x01F71CF0,
0x01F71D11,
0x01F71E11,

4
src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c
View File

@ -99,12 +99,12 @@ void get_bus_conf(void)
}
for(i = 2; i < 8; i++) {
dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0));
dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0));
if (dev) {
m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 );
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2);
}
}

4
src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c
View File

@ -105,12 +105,12 @@ void get_bus_conf(void)
}
for(i = 2; i < 8; i++) {
dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0));
dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0));
if (dev) {
m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 );
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2);
}
}

14
src/mainboard/supermicro/h8qme_fam10/romstage.c
View File

@ -89,17 +89,17 @@ static void sio_setup(void)
// smbusx_write_byte(1, (0x58 >> 1), 0, 0x80); /* select bank0 */
smbusx_write_byte(1, (0x58 >> 1), 0xb1, 0xff); /* set FAN ctrl to DC mode */
byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0x7b);
byte |= 0x20;
pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0x7b, byte);
dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa0);
dword |= (1 << 0);
pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa0, dword);
dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa4);
dword |= (1 << 16);
pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa4, dword);
}
static const u8 spd_addr[] = {
@ -113,7 +113,7 @@ static const u8 spd_addr[] = {
/* third node */
RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
/* fourth node */
RC03, DIMM4, DIMM6,0 , 0, DIMM5, DIMM7, 0, 0,
RC03, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0,
#endif
};

4
src/mainboard/tyan/s2912_fam10/get_bus_conf.c
View File

@ -98,12 +98,12 @@ void get_bus_conf(void)
}
for(i = 2; i < 8; i++) {
dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0));
dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0));
if (dev) {
m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 );
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2);
}
}

12
src/mainboard/tyan/s2912_fam10/romstage.c
View File

@ -87,18 +87,18 @@ static void sio_setup(void)
uint32_t dword;
uint8_t byte;
byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0x7b);
byte |= 0x20;
pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0x7b, byte);
dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa0);
/*serial 0 */
dword |= (1 << 0);
pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa0, dword);
dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa4);
dword |= (1 << 16);
pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa4, dword);
}
static const u8 spd_addr[] = {

4
src/northbridge/amd/agesa/family14/northbridge.c
View File

@ -149,7 +149,7 @@ static struct resource *amdfam14_find_iopair(struct device *dev,
/* Ext conf space */
if (!reg) {
/* Because of Extend conf space, we will never run out of reg,
* but we need one index to differ them. So ,same node and same
* but we need one index to differ them. So,same node and same
* link can have multi range
*/
u32 index = get_io_addr_index(nodeid, link);
@ -185,7 +185,7 @@ static struct resource *amdfam14_find_mempair(struct device *dev, u32 nodeid,
/* Ext conf space */
if (!reg) {
/* Because of Extend conf space, we will never run out of reg,
* but we need one index to differ them. So ,same node and same
* but we need one index to differ them. So,same node and same
* link can have multi range
*/
u32 index = get_mmio_addr_index(nodeid, link);

2
src/northbridge/amd/amdmct/mct/mct_d.c
View File

@ -1737,7 +1737,7 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat,
* and PCI 0:24N:2x60,64,68,6C config registers (CS Mask 0-3).
*/
u8 ChipSel, Rows, Cols, Ranks ,Banks, DevWidth;
u8 ChipSel, Rows, Cols, Ranks, Banks, DevWidth;
u32 BankAddrReg, csMask;
u32 val;

2
src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
View File

@ -684,7 +684,7 @@ void prepareDimms(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat,
{tempW = bitTestSet(tempW, 7);}
if (bitTest(tempW1,18))
{tempW = bitTestSet(tempW, 6);}
/* tempW = tempW|(((tempW1 >> 20) & 0x7 )<< 3); */
/* tempW = tempW|(((tempW1 >> 20) & 0x7)<< 3); */
tempW = tempW|((tempW1&0x00700000) >> 17);
/* workaround for DR-B0 */
if ((pDCTData->LogicalCPUID & AMD_DR_Bx) && (pDCTData->Status[DCT_STATUS_REGISTERED]))

3
src/northbridge/intel/e7505/debug.c
View File

@ -148,7 +148,8 @@ void dump_smbus_registers(void)
printk(BIOS_DEBUG, "\n");
for (device = 1; device < 0x80; device++) {
int j;
if ( spd_read_byte(device, 0) < 0 ) continue;
if (spd_read_byte(device, 0) < 0)
continue;
printk(BIOS_DEBUG, "smbus: %02x", device);
for (j = 0; j < 256; j++) {
int status;

2
src/northbridge/intel/fsp_rangeley/northbridge.c
View File

@ -131,7 +131,7 @@ static void mc_add_dram_resources(struct device *dev)
mmio_resource(dev, index++, tomlow >> 10, (bmbound - bsmmrrl) >> 10);
if (bmbound_hi > 0x100000000) {
ram_resource(dev, index++, 0x100000000 >> 10, (bmbound_hi - 0x100000000) >> 10 );
ram_resource(dev, index++, 0x100000000 >> 10, (bmbound_hi - 0x100000000) >> 10);
printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", (bmbound_hi - 0x100000000) >> 20);
}

2
src/northbridge/intel/haswell/raminit.c
View File

@ -180,7 +180,7 @@ void sdram_initialize(struct pei_data *pei_data)
*/
u32 version = MCHBAR32(0x5034);
printk(BIOS_DEBUG, "System Agent Version %d.%d.%d Build %d\n",
version >> 24 , (version >> 16) & 0xff,
version >> 24, (version >> 16) & 0xff,
(version >> 8) & 0xff, version & 0xff);
report_memory_config();

2
src/northbridge/intel/nehalem/early_init.c
View File

@ -36,7 +36,7 @@ static void nehalem_setup_bars(void)
pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
/* Enable ACPI BAR */
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80);
printk(BIOS_DEBUG, " done.\n");

4
src/northbridge/intel/pineview/early_init.c
View File

@ -181,9 +181,9 @@ static void pineview_setup_bars(void)
printk(BIOS_DEBUG, "Setting up static southbridge registers...");
pci_write_config32(LPC, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
pci_write_config32(LPC, PMBASE, DEFAULT_PMBASE | 1);
pci_write_config8(LPC, 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI */
pci_write_config8(LPC, 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI */
pci_write_config32(LPC, GPIOBASE, DEFAULT_GPIOBASE | 1);
pci_write_config8(LPC, 0x4c /* GC */ , 0x10); /* Enable GPIOs */
pci_write_config8(LPC, 0x4c /* GC */, 0x10); /* Enable GPIOs */
pci_write_config32(LPC, 0x88, 0x007c0291);
pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);

14
src/northbridge/intel/pineview/raminit.c
View File

@ -57,13 +57,13 @@
#define DIMM_IS_POPULATED(dimms, idx) (dimms[idx].card_type != 0)
#define IF_DIMM_POPULATED(dimms, idx) if (dimms[idx].card_type != 0)
#define ONLY_DIMMA_IS_POPULATED(dimms, ch) ( \
#define ONLY_DIMMA_IS_POPULATED(dimms, ch) (\
(DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2) && \
!DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3)))
#define ONLY_DIMMB_IS_POPULATED(dimms, ch) ( \
#define ONLY_DIMMB_IS_POPULATED(dimms, ch) (\
(DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3) && \
!DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2)))
#define BOTH_DIMMS_ARE_POPULATED(dimms, ch) ( \
#define BOTH_DIMMS_ARE_POPULATED(dimms, ch) (\
(DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2) && \
(DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3))))
#define FOR_EACH_DIMM(idx) \
@ -905,11 +905,11 @@ static void sdram_p_dqs(struct pllparam *pll, u8 f, u8 clk)
reg32 |= ((u32) pll->dben[f][clk]) << (dqs + 9);
reg32 |= ((u32) pll->dbsel[f][clk]) << dqs;
MCHBAR32(0x5b4+rank*4) = (MCHBAR32(0x5b4+rank*4) &
~( (1 << (dqs+9))|(1 << dqs) )) | reg32;
~((1 << (dqs+9))|(1 << dqs))) | reg32;
reg32 = ((u32) pll->clkdelay[f][clk]) << ((dqs*2) + 16);
MCHBAR32(0x5c8+rank*4) = (MCHBAR32(0x5c8+rank*4) &
~( (1 << (dqs*2 + 17))|(1 << (dqs*2 + 16)) )) | reg32;
~((1 << (dqs*2 + 17))|(1 << (dqs*2 + 16)))) | reg32;
reg8 = pll->pi[f][clk];
MCHBAR8(0x520+j) = (MCHBAR8(0x520+j) & ~0x3f) | reg8;
@ -930,11 +930,11 @@ static void sdram_p_dq(struct pllparam *pll, u8 f, u8 clk)
reg32 |= ((u32) pll->dben[f][clk]) << (dq + 9);
reg32 |= ((u32) pll->dbsel[f][clk]) << dq;
MCHBAR32(0x5a4+rank*4) = (MCHBAR32(0x5a4+rank*4) &
~( (1 << (dq+9))|(1 << dq) )) | reg32;
~((1 << (dq+9))|(1 << dq))) | reg32;
reg32 = ((u32) pll->clkdelay[f][clk]) << (dq*2);
MCHBAR32(0x5c8+rank*4) = (MCHBAR32(0x5c8+rank*4) &
~( (1 << (dq*2 + 1))|(1 << (dq*2)) )) | reg32;
~((1 << (dq*2 + 1))|(1 << (dq*2)))) | reg32;
reg8 = pll->pi[f][clk];
MCHBAR8(0x500+j) = (MCHBAR8(0x500+j) & ~0x3f) | reg8;

2
src/northbridge/intel/sandybridge/raminit_ivy.c
View File

@ -225,7 +225,7 @@ static u8 get_XP(u32 tCK, u8 base_freq)
* FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 |
* XP : | 3 | 4 | 4 | 5 | 6 | 7 | 8 | 8 |
*/
static const u8 frq_xp_map[] = { 3, 4, 4, 5, 6, 7 , 8, 8 };
static const u8 frq_xp_map[] = { 3, 4, 4, 5, 6, 7, 8, 8 };
xp = frq_xp_map[get_FRQ(tCK, 133) - 3];
}

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