From a3b01374310f635dd4716d71c64e677bc797fc30 Mon Sep 17 00:00:00 2001 From: Tim Crawford Date: Wed, 26 Oct 2022 09:53:54 -0600 Subject: [PATCH] mb/system76/adl-p: Remove CPU PCIe RP RTD3 config This has caused nothing but issues trying to get different drives to behave correctly. Just remove it. Change-Id: I5ed36c519fa7757034172f146fb5e03a15f40ede Signed-off-by: Tim Crawford --- .../system76/adl-p/variants/darp8/overridetree.cb | 6 ------ .../system76/adl-p/variants/galp6/overridetree.cb | 6 ------ .../system76/adl-p/variants/lemp11/overridetree.cb | 6 ------ .../system76/adl-p/variants/oryp10/overridetree.cb | 14 -------------- .../system76/adl-p/variants/oryp9/overridetree.cb | 14 -------------- 5 files changed, 46 deletions(-) diff --git a/src/mainboard/system76/adl-p/variants/darp8/overridetree.cb b/src/mainboard/system76/adl-p/variants/darp8/overridetree.cb index 4caed3a173..4a554adfcc 100644 --- a/src/mainboard/system76/adl-p/variants/darp8/overridetree.cb +++ b/src/mainboard/system76/adl-p/variants/darp8/overridetree.cb @@ -22,12 +22,6 @@ chip soc/intel/alderlake .clk_req = 0, .flags = PCIE_RP_LTR, }" - chip soc/intel/common/block/pcie/rtd3 - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD2_PWR_EN - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)" # M2_CPU_SSD2_RST# - register "srcclk_pin" = "0" # SSD2_CLKREQ# - device generic 0 on end - end end device ref tcss_xhci on register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" diff --git a/src/mainboard/system76/adl-p/variants/galp6/overridetree.cb b/src/mainboard/system76/adl-p/variants/galp6/overridetree.cb index 84b0116742..555b1fd70b 100644 --- a/src/mainboard/system76/adl-p/variants/galp6/overridetree.cb +++ b/src/mainboard/system76/adl-p/variants/galp6/overridetree.cb @@ -20,12 +20,6 @@ chip soc/intel/alderlake .clk_req = 0, .flags = PCIE_RP_LTR, }" - chip soc/intel/common/block/pcie/rtd3 - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD1_PWR_EN - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)" # M2_SSD1_RST# - register "srcclk_pin" = "0" # SSD1_CLKREQ# - device generic 0 on end - end end device ref tcss_xhci on register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" diff --git a/src/mainboard/system76/adl-p/variants/lemp11/overridetree.cb b/src/mainboard/system76/adl-p/variants/lemp11/overridetree.cb index ac27ab989b..5bdfafe57d 100644 --- a/src/mainboard/system76/adl-p/variants/lemp11/overridetree.cb +++ b/src/mainboard/system76/adl-p/variants/lemp11/overridetree.cb @@ -20,12 +20,6 @@ chip soc/intel/alderlake .clk_req = 0, .flags = PCIE_RP_LTR, }" - chip soc/intel/common/block/pcie/rtd3 - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD2_PWR_EN - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)" # M2_CPU_SSD2_RST# - register "srcclk_pin" = "0" # SSD0_CLKREQ# - device generic 0 on end - end end device ref tcss_xhci on register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" diff --git a/src/mainboard/system76/adl-p/variants/oryp10/overridetree.cb b/src/mainboard/system76/adl-p/variants/oryp10/overridetree.cb index 81e26ed326..3fd36bc251 100644 --- a/src/mainboard/system76/adl-p/variants/oryp10/overridetree.cb +++ b/src/mainboard/system76/adl-p/variants/oryp10/overridetree.cb @@ -41,13 +41,6 @@ chip soc/intel/alderlake .clk_req = 0, .flags = PCIE_RP_LTR, }" - # FIXME: WD drives fail to suspend - #chip soc/intel/common/block/pcie/rtd3 - # register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # M2_PWR_EN1 - # register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST# - # register "srcclk_pin" = "0" # SSD0_CLKREQ# - # device generic 0 on end - #end end device ref pcie4_1 on # CPU PCIe RP#3 x4, Clock 4 (SSD2) @@ -56,13 +49,6 @@ chip soc/intel/alderlake .clk_req = 4, .flags = PCIE_RP_LTR, }" - # FIXME: WD drives fail to suspend - #chip soc/intel/common/block/pcie/rtd3 - # register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C2)" # M2_PWR_EN2 - # register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST# - # register "srcclk_pin" = "4" # SSD1_CLKREQ# - # device generic 0 on end - #end end device ref tcss_xhci on register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" diff --git a/src/mainboard/system76/adl-p/variants/oryp9/overridetree.cb b/src/mainboard/system76/adl-p/variants/oryp9/overridetree.cb index 0a91b5190a..05257d8971 100644 --- a/src/mainboard/system76/adl-p/variants/oryp9/overridetree.cb +++ b/src/mainboard/system76/adl-p/variants/oryp9/overridetree.cb @@ -41,13 +41,6 @@ chip soc/intel/alderlake .clk_req = 0, .flags = PCIE_RP_LTR, }" - # FIXME: WD drives fail to suspend - #chip soc/intel/common/block/pcie/rtd3 - # register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # M2_PWR_EN1 - # register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST# - # register "srcclk_pin" = "0" # SSD0_CLKREQ# - # device generic 0 on end - #end end device ref pcie4_1 on # CPU PCIe RP#3 x4, Clock 4 (SSD2) @@ -56,13 +49,6 @@ chip soc/intel/alderlake .clk_req = 4, .flags = PCIE_RP_LTR, }" - # FIXME: WD drives fail to suspend - #chip soc/intel/common/block/pcie/rtd3 - # register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C2)" # M2_PWR_EN2 - # register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST# - # register "srcclk_pin" = "4" # SSD1_CLKREQ# - # device generic 0 on end - #end end device ref tcss_xhci on register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"