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haswell boards: Correct USB config indentation

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Change-Id: I72b717a41c5611cf578ce178722029b8646cbb35
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50539
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons
2021-02-11 13:59:12 +01:00
parent 33b59c9170
commit a3c6ed0dff
12 changed files with 314 additions and 314 deletions
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8
src/mainboard/asrock/b85m_pro4/romstage.c
View File

@@ -25,7 +25,7 @@ void mb_get_spd_map(uint8_t spd_map[4])
spd_map[3] = 0xa6;
}
const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
{ 0x0040, 1, 0, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 0, USB_PORT_BACK_PANEL },
@@ -41,13 +41,13 @@ void mb_get_spd_map(uint8_t spd_map[4])
{ 0x0040, 1, 5, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 6, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 6, USB_PORT_BACK_PANEL },
};
};
const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
{ 1, 0 },
{ 1, 0 },
{ 1, 1 },
{ 1, 1 },
{ 1, 2 },
{ 1, 2 },
};
};

8
src/mainboard/asrock/h81m-hds/romstage.c
View File

@@ -23,7 +23,7 @@ void mb_get_spd_map(uint8_t spd_map[4])
spd_map[2] = 0xa4;
}
const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
{ 0x0040, 1, 0, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 0, USB_PORT_BACK_PANEL },
@@ -39,9 +39,9 @@ void mb_get_spd_map(uint8_t spd_map[4])
{ 0x0040, 1, 5, USB_PORT_BACK_PANEL },
{ 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },
{ 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },
};
};
const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
/* Enable, OCn# */
{ 1, 0 },
{ 1, 0 },
@@ -49,4 +49,4 @@ void mb_get_spd_map(uint8_t spd_map[4])
{ 0, USB_OC_PIN_SKIP },
{ 0, USB_OC_PIN_SKIP },
{ 0, USB_OC_PIN_SKIP },
};
};

8
src/mainboard/google/beltino/romstage.c
View File

@@ -46,7 +46,7 @@ void mb_get_spd_map(uint8_t spd_map[4])
spd_map[2] = 0xa4;
}
const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
{ 0x0064, 1, 0, /* P0: VP8 */
USB_PORT_MINI_PCIE },
@@ -64,12 +64,12 @@ void mb_get_spd_map(uint8_t spd_map[4])
USB_PORT_INTERNAL },
{ 0x0000, 0, 0, /* P7: N/C */
USB_PORT_SKIP },
};
};
const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
/* Enable, OCn# */
{ 1, 0 }, /* P1; CN22 */
{ 1, 1 }, /* P2; CN23 */
{ 1, 2 }, /* P3; CN25 */
{ 1, 2 }, /* P4; CN25 */
};
};

8
src/mainboard/google/slippy/variants/falco/romstage.c
View File

@@ -48,7 +48,7 @@ void copy_spd(struct pei_data *peid)
}
}
const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
{ 0x0064, 1, 0, /* P0: Port A, CN8 */
USB_PORT_BACK_PANEL },
@@ -66,12 +66,12 @@ void copy_spd(struct pei_data *peid)
USB_PORT_INTERNAL },
{ 0x0123, 1, 3, /* P7: USB2 Port */
USB_PORT_INTERNAL },
};
};
const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
/* Enable, OCn# */
{ 1, 0 }, /* P1; Port A, CN8 */
{ 1, 0 }, /* P2; Port B, CN9 */
{ 0, USB_OC_PIN_SKIP }, /* P3; */
{ 0, USB_OC_PIN_SKIP }, /* P4; */
};
};

8
src/mainboard/google/slippy/variants/leon/romstage.c
View File

@@ -44,7 +44,7 @@ void copy_spd(struct pei_data *peid)
spd_file + (spd_index * spd_len), spd_len);
}
const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
{ 0x0040, 1, 0, /* P0: Port A, CN10 */
USB_PORT_BACK_PANEL },
@@ -62,12 +62,12 @@ void copy_spd(struct pei_data *peid)
USB_PORT_FLEX },
{ 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */
USB_PORT_SKIP },
};
};
const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
/* Enable, OCn# */
{ 1, 0 }, /* P1; Port A, CN10 */
{ 1, 2 }, /* P2; Port B, CN11 */
{ 0, USB_OC_PIN_SKIP }, /* P3; */
{ 0, USB_OC_PIN_SKIP }, /* P4; */
};
};

8
src/mainboard/google/slippy/variants/peppy/romstage.c
View File

@@ -62,7 +62,7 @@ void copy_spd(struct pei_data *peid)
}
}
const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
{ 0x0150, 1, USB_OC_PIN_SKIP, /* P0: LTE */
USB_PORT_MINI_PCIE },
@@ -80,12 +80,12 @@ void copy_spd(struct pei_data *peid)
USB_PORT_FLEX },
{ 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */
USB_PORT_SKIP },
};
};
const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
/* Enable, OCn# */
{ 1, 0 }, /* P1; Port A, CN6 */
{ 0, USB_OC_PIN_SKIP }, /* P2; */
{ 0, USB_OC_PIN_SKIP }, /* P3; */
{ 0, USB_OC_PIN_SKIP }, /* P4; */
};
};

8
src/mainboard/google/slippy/variants/wolf/romstage.c
View File

@@ -48,7 +48,7 @@ void copy_spd(struct pei_data *peid)
}
}
const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
{ 0x0040, 1, 0, /* P0: Port A, CN10 */
USB_PORT_BACK_PANEL },
@@ -66,12 +66,12 @@ void copy_spd(struct pei_data *peid)
USB_PORT_INTERNAL },
{ 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */
USB_PORT_SKIP },
};
};
const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
/* Enable, OCn# */
{ 1, 0 }, /* P1; Port A, CN10 */
{ 1, 2 }, /* P2; Port B, CN11 */
{ 0, USB_OC_PIN_SKIP }, /* P3; */
{ 0, USB_OC_PIN_SKIP }, /* P4; */
};
};

8
src/mainboard/hp/folio_9480m/romstage.c
View File

@@ -23,7 +23,7 @@ void mb_get_spd_map(uint8_t spd_map[4])
spd_map[2] = 0xa4;
}
const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
{ 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* dock */
{ 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* left, EHCI debug */
@@ -33,11 +33,11 @@ void mb_get_spd_map(uint8_t spd_map[4])
{ 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE }, /* WWAN */
{ 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* Webcam */
{ 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL },
};
};
const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
{ 1, USB_OC_PIN_SKIP }, /* dock */
{ 1, USB_OC_PIN_SKIP }, /* left */
{ 1, USB_OC_PIN_SKIP }, /* right */
{ 0, USB_OC_PIN_SKIP },
};
};

8
src/mainboard/intel/baskingridge/romstage.c
View File

@@ -49,7 +49,7 @@ void mb_get_spd_map(uint8_t spd_map[4])
spd_map[3] = 0xa6;
}
const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
{ 0x0040, 1, 0, /* P0: Back USB3 port (OC0) */
USB_PORT_BACK_PANEL },
@@ -79,9 +79,9 @@ void mb_get_spd_map(uint8_t spd_map[4])
USB_PORT_FRONT_PANEL },
{ 0x0040, 1, 6, /* P13: USB/DP Jack (OC6) */
USB_PORT_FRONT_PANEL },
};
};
const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
/* Enable, OCn# */
{ 1, 0 }, /* P1; */
{ 1, 0 }, /* P2; */
@@ -89,4 +89,4 @@ void mb_get_spd_map(uint8_t spd_map[4])
{ 1, 0 }, /* P4; */
{ 1, 0 }, /* P6; */
{ 1, 0 }, /* P6; */
};
};

8
src/mainboard/lenovo/t440p/romstage.c
View File

@@ -46,7 +46,7 @@ void mb_get_spd_map(uint8_t spd_map[4])
spd_map[2] = 0xa2;
}
const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
{ 0x0040, 1, 0, USB_PORT_BACK_PANEL }, /* USB3 */
{ 0x0040, 1, 0, USB_PORT_BACK_PANEL }, /* USB3 */
@@ -62,13 +62,13 @@ void mb_get_spd_map(uint8_t spd_map[4])
{ 0x0040, 1, 5, USB_PORT_BACK_PANEL }, /* webcam */
{ 0x0080, 1, 6, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 6, USB_PORT_BACK_PANEL },
};
};
const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
{ 1, 0 },
{ 1, 0 },
{ 1, USB_OC_PIN_SKIP },
{ 1, USB_OC_PIN_SKIP },
{ 1, 1 },
{ 1, 1 }, /* WWAN */
};
};

8
src/mainboard/msi/h81m-p33/romstage.c
View File

@@ -23,7 +23,7 @@ void mb_get_spd_map(uint8_t spd_map[4])
spd_map[2] = 0xa4;
}
const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
{ 0x0040, 1, 0, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 0, USB_PORT_BACK_PANEL },
@@ -39,13 +39,13 @@ void mb_get_spd_map(uint8_t spd_map[4])
{ 0x0040, 1, 5, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 6, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 6, USB_PORT_BACK_PANEL },
};
};
const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
{ 1, 0 },
{ 1, 0 },
{ 1, 1 },
{ 1, 1 },
{ 1, 2 },
{ 1, 2 },
};
};

8
src/mainboard/supermicro/x10slm-f/romstage.c
View File

@@ -25,7 +25,7 @@ void mb_get_spd_map(uint8_t spd_map[4])
spd_map[3] = 0xa6;
}
const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
{ 0x0040, 1, 0, USB_PORT_INTERNAL },
{ 0x0040, 1, 0, USB_PORT_BACK_PANEL },
@@ -41,9 +41,9 @@ void mb_get_spd_map(uint8_t spd_map[4])
{ 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },
{ 0x0040, 1, 6, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 6, USB_PORT_BACK_PANEL },
};
};
const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
/* Enable, OCn# */
{ 1, 1 },
{ 1, 1 },
@@ -51,4 +51,4 @@ void mb_get_spd_map(uint8_t spd_map[4])
{ 0, USB_OC_PIN_SKIP },
{ 1, 3 },
{ 1, 3 },
};
};