static configuration. Needs new keyword per greg to enable inclusion of a

part-specific struct into the tree.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@941 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich
2003-07-11 14:51:29 +00:00
parent 2fceb77c47
commit a3c708b5d2
4 changed files with 67 additions and 16 deletions

View File

@@ -1,7 +1,8 @@
/* chips are arbitrary chips (superio, southbridge, etc.)
* They have private structures that define chip resources and default
* settings. They have four externally visible functions for control.
* new settings are provided as ascii strings.
* They have a generic component which applies to all chips for
* path, etc.
*/
/* some of the types of resources chips can control */
@@ -30,6 +31,7 @@ struct lpt_ports {
struct chip;
/* there is one of these for each TYPE of chip */
struct chip_control {
void (*alloc)(struct chip *s);
void (*pre_pci_init)(struct chip *s);
@@ -46,5 +48,9 @@ struct chip {
struct chip_control *control; /* for this device */
char *path; /* can be 0, in which case the default is taken */
char *configuration; /* can be 0. */
int irq;
struct chip *next, *children;
/* there is one of these for each INSTANCE of a chip */
void *chip_info; /* the dreaded "void *" */
};

View File

@@ -20,7 +20,7 @@ if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
#
arch i386 end
cpu k8 end
#cpu k8 end
#
###
### Build our 16 bit and 32 bit linuxBIOS entry code
@@ -34,7 +34,6 @@ ldscript /cpu/i386/entry32.lds
### Build our reset vector (This is where linuxBIOS is entered)
###
if USE_FALLBACK_IMAGE
print "Use fallback!"
mainboardinit cpu/i386/reset16.inc
ldscript /cpu/i386/reset16.lds
else
@@ -128,7 +127,7 @@ southbridge amd/amd8111
end
#mainboardinit archi386/smp/secondary.inc
superio NSC/pc87360
register "com1={1} com2={0} floppy=1 lpt=1 keyboard=1"
register ".com1={1}, .com2={0}, .floppy=1, .lpt=1, .keyboard=1"
end
dir /pc80
##dir /src/superio/winbond/w83627hf