static configuration. Needs new keyword per greg to enable inclusion of a
part-specific struct into the tree. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@941 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@@ -1,7 +1,8 @@
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/* chips are arbitrary chips (superio, southbridge, etc.)
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* They have private structures that define chip resources and default
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* settings. They have four externally visible functions for control.
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* new settings are provided as ascii strings.
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* They have a generic component which applies to all chips for
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* path, etc.
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*/
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/* some of the types of resources chips can control */
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@@ -30,6 +31,7 @@ struct lpt_ports {
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struct chip;
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/* there is one of these for each TYPE of chip */
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struct chip_control {
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void (*alloc)(struct chip *s);
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void (*pre_pci_init)(struct chip *s);
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@@ -46,5 +48,9 @@ struct chip {
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struct chip_control *control; /* for this device */
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char *path; /* can be 0, in which case the default is taken */
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char *configuration; /* can be 0. */
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int irq;
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struct chip *next, *children;
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/* there is one of these for each INSTANCE of a chip */
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void *chip_info; /* the dreaded "void *" */
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};
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@@ -20,7 +20,7 @@ if HAVE_MP_TABLE object mptable.o end
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if HAVE_PIRQ_TABLE object irq_tables.o end
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#
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arch i386 end
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cpu k8 end
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#cpu k8 end
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#
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###
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### Build our 16 bit and 32 bit linuxBIOS entry code
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@@ -34,7 +34,6 @@ ldscript /cpu/i386/entry32.lds
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### Build our reset vector (This is where linuxBIOS is entered)
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###
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if USE_FALLBACK_IMAGE
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print "Use fallback!"
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mainboardinit cpu/i386/reset16.inc
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ldscript /cpu/i386/reset16.lds
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else
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@@ -128,7 +127,7 @@ southbridge amd/amd8111
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end
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#mainboardinit archi386/smp/secondary.inc
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superio NSC/pc87360
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register "com1={1} com2={0} floppy=1 lpt=1 keyboard=1"
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register ".com1={1}, .com2={0}, .floppy=1, .lpt=1, .keyboard=1"
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end
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dir /pc80
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##dir /src/superio/winbond/w83627hf
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