soc/intel/jasperlake: Add Acoustic noise mitigation configuration
This patch exposes acoustic noise mitigation related UPDs/configuration to be filled from devicetree. For each variant, we might have different values for various parameters. Filling it from devicetree will allow us to fill separate values for each board/variant. Note that since JasperLake only has one VR, we're only filling index 0 for slew rate and FastPkgCRampDisable. BUG=b:162192346 BRANCH=dedede TEST=code compilation is successful and values from devicetree are getting reflected in UPDs Change-Id: Id022f32acc3fd3fe62f78e3053bacdeb33727c02 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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committed by
Patrick Georgi
parent
c987e65eb4
commit
a4bef79522
@@ -236,6 +236,14 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
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config->PchPmSlpS3MinAssert, config->PchPmSlpAMinAssert,
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config->PchPmPwrCycDur);
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/* Fill Acoustic noise mitigation related configuration */
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params->FastPkgCRampDisable[0] = config->FastPkgCRampDisable;
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params->SlowSlewRate[0] = config->SlowSlewRate;
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params->AcousticNoiseMitigation = config->AcousticNoiseMitigation;
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params->PreWake = config->PreWake;
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params->RampUp = config->RampUp;
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params->RampDown = config->RampDown;
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/* Override/Fill FSP Silicon Param for mainboard */
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mainboard_silicon_init_params(params);
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}
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