mb/**/cmos.layout: Drop unreferenced iommu
option
No code in coreboot uses this option, so it might as well be dropped. Change-Id: Ie58bab7e87831db08b9f398a777ba350920b707b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52639 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
@@ -11,7 +11,6 @@ entries
|
|||||||
400 1 e 1 power_on_after_fail
|
400 1 e 1 power_on_after_fail
|
||||||
412 4 e 6 debug_level
|
412 4 e 6 debug_level
|
||||||
444 1 e 1 nmi
|
444 1 e 1 nmi
|
||||||
445 1 e 1 iommu
|
|
||||||
728 256 h 0 user_data
|
728 256 h 0 user_data
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
# Reserve the extended AMD configuration registers
|
# Reserve the extended AMD configuration registers
|
||||||
|
@@ -11,7 +11,6 @@ entries
|
|||||||
400 1 e 1 power_on_after_fail
|
400 1 e 1 power_on_after_fail
|
||||||
412 4 e 6 debug_level
|
412 4 e 6 debug_level
|
||||||
444 1 e 1 nmi
|
444 1 e 1 nmi
|
||||||
445 1 e 1 iommu
|
|
||||||
728 256 h 0 user_data
|
728 256 h 0 user_data
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
# Reserve the extended AMD configuration registers
|
# Reserve the extended AMD configuration registers
|
||||||
|
@@ -11,7 +11,6 @@ entries
|
|||||||
400 1 e 1 power_on_after_fail
|
400 1 e 1 power_on_after_fail
|
||||||
412 4 e 6 debug_level
|
412 4 e 6 debug_level
|
||||||
444 1 e 1 nmi
|
444 1 e 1 nmi
|
||||||
445 1 e 1 iommu
|
|
||||||
728 256 h 0 user_data
|
728 256 h 0 user_data
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
# Reserve the extended AMD configuration registers
|
# Reserve the extended AMD configuration registers
|
||||||
|
@@ -11,7 +11,6 @@ entries
|
|||||||
400 1 e 1 power_on_after_fail
|
400 1 e 1 power_on_after_fail
|
||||||
412 4 e 6 debug_level
|
412 4 e 6 debug_level
|
||||||
444 1 e 1 nmi
|
444 1 e 1 nmi
|
||||||
445 1 e 1 iommu
|
|
||||||
728 256 h 0 user_data
|
728 256 h 0 user_data
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
# Reserve the extended AMD configuration registers
|
# Reserve the extended AMD configuration registers
|
||||||
|
@@ -11,7 +11,6 @@ entries
|
|||||||
400 1 e 1 power_on_after_fail
|
400 1 e 1 power_on_after_fail
|
||||||
412 4 e 6 debug_level
|
412 4 e 6 debug_level
|
||||||
444 1 e 1 nmi
|
444 1 e 1 nmi
|
||||||
445 1 e 1 iommu
|
|
||||||
728 256 h 0 user_data
|
728 256 h 0 user_data
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
# Reserve the extended AMD configuration registers
|
# Reserve the extended AMD configuration registers
|
||||||
|
@@ -11,7 +11,6 @@ entries
|
|||||||
400 1 e 1 power_on_after_fail
|
400 1 e 1 power_on_after_fail
|
||||||
412 4 e 6 debug_level
|
412 4 e 6 debug_level
|
||||||
444 1 e 1 nmi
|
444 1 e 1 nmi
|
||||||
445 1 e 1 iommu
|
|
||||||
728 256 h 0 user_data
|
728 256 h 0 user_data
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
# Reserve the extended AMD configuration registers
|
# Reserve the extended AMD configuration registers
|
||||||
|
@@ -11,7 +11,6 @@ entries
|
|||||||
400 1 e 1 power_on_after_fail
|
400 1 e 1 power_on_after_fail
|
||||||
412 4 e 6 debug_level
|
412 4 e 6 debug_level
|
||||||
444 1 e 1 nmi
|
444 1 e 1 nmi
|
||||||
445 1 e 1 iommu
|
|
||||||
728 256 h 0 user_data
|
728 256 h 0 user_data
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
# Reserve the extended AMD configuration registers
|
# Reserve the extended AMD configuration registers
|
||||||
|
@@ -11,7 +11,6 @@ entries
|
|||||||
400 2 e 3 power_on_after_fail
|
400 2 e 3 power_on_after_fail
|
||||||
412 4 e 6 debug_level
|
412 4 e 6 debug_level
|
||||||
444 1 e 1 nmi
|
444 1 e 1 nmi
|
||||||
445 1 e 1 iommu
|
|
||||||
728 256 h 0 user_data
|
728 256 h 0 user_data
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
# Reserve the extended AMD configuration registers
|
# Reserve the extended AMD configuration registers
|
||||||
|
@@ -11,7 +11,6 @@ entries
|
|||||||
400 1 e 1 power_on_after_fail
|
400 1 e 1 power_on_after_fail
|
||||||
412 4 e 6 debug_level
|
412 4 e 6 debug_level
|
||||||
444 1 e 1 nmi
|
444 1 e 1 nmi
|
||||||
445 1 e 1 iommu
|
|
||||||
728 256 h 0 user_data
|
728 256 h 0 user_data
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
# Reserve the extended AMD configuration registers
|
# Reserve the extended AMD configuration registers
|
||||||
|
@@ -8,7 +8,6 @@ entries
|
|||||||
400 1 e 1 power_on_after_fail
|
400 1 e 1 power_on_after_fail
|
||||||
412 4 e 6 debug_level
|
412 4 e 6 debug_level
|
||||||
444 1 e 1 nmi
|
444 1 e 1 nmi
|
||||||
445 1 e 1 iommu
|
|
||||||
728 256 h 0 user_data
|
728 256 h 0 user_data
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
# Reserve the extended AMD configuration registers
|
# Reserve the extended AMD configuration registers
|
||||||
|
@@ -11,7 +11,6 @@ entries
|
|||||||
400 1 e 1 power_on_after_fail
|
400 1 e 1 power_on_after_fail
|
||||||
412 4 e 6 debug_level
|
412 4 e 6 debug_level
|
||||||
444 1 e 1 nmi
|
444 1 e 1 nmi
|
||||||
445 1 e 1 iommu
|
|
||||||
728 256 h 0 user_data
|
728 256 h 0 user_data
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
# Reserve the extended AMD configuration registers
|
# Reserve the extended AMD configuration registers
|
||||||
|
@@ -11,7 +11,6 @@ entries
|
|||||||
400 1 e 1 power_on_after_fail
|
400 1 e 1 power_on_after_fail
|
||||||
412 4 e 6 debug_level
|
412 4 e 6 debug_level
|
||||||
444 1 e 1 nmi
|
444 1 e 1 nmi
|
||||||
445 1 e 1 iommu
|
|
||||||
728 256 h 0 user_data
|
728 256 h 0 user_data
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
# Reserve the extended AMD configuration registers
|
# Reserve the extended AMD configuration registers
|
||||||
|
@@ -11,7 +11,6 @@ entries
|
|||||||
400 1 e 1 power_on_after_fail
|
400 1 e 1 power_on_after_fail
|
||||||
412 4 e 6 debug_level
|
412 4 e 6 debug_level
|
||||||
444 1 e 1 nmi
|
444 1 e 1 nmi
|
||||||
445 1 e 1 iommu
|
|
||||||
728 256 h 0 user_data
|
728 256 h 0 user_data
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
# Reserve the extended AMD configuration registers
|
# Reserve the extended AMD configuration registers
|
||||||
|
@@ -39,7 +39,6 @@ entries
|
|||||||
428 4 h 0 boot_index
|
428 4 h 0 boot_index
|
||||||
432 8 h 0 boot_countdown
|
432 8 h 0 boot_countdown
|
||||||
444 1 e 1 nmi
|
444 1 e 1 nmi
|
||||||
445 1 e 1 iommu
|
|
||||||
728 256 h 0 user_data
|
728 256 h 0 user_data
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
# Reserve the extended AMD configuration registers
|
# Reserve the extended AMD configuration registers
|
||||||
|
@@ -11,7 +11,6 @@ entries
|
|||||||
400 1 e 1 power_on_after_fail
|
400 1 e 1 power_on_after_fail
|
||||||
412 4 e 6 debug_level
|
412 4 e 6 debug_level
|
||||||
444 1 e 1 nmi
|
444 1 e 1 nmi
|
||||||
445 1 e 1 iommu
|
|
||||||
728 256 h 0 user_data
|
728 256 h 0 user_data
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
# Reserve the extended AMD configuration registers
|
# Reserve the extended AMD configuration registers
|
||||||
|
@@ -11,7 +11,6 @@ entries
|
|||||||
400 1 e 1 power_on_after_fail
|
400 1 e 1 power_on_after_fail
|
||||||
412 4 e 6 debug_level
|
412 4 e 6 debug_level
|
||||||
444 1 e 1 nmi
|
444 1 e 1 nmi
|
||||||
445 1 e 1 iommu
|
|
||||||
728 256 h 0 user_data
|
728 256 h 0 user_data
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
# Reserve the extended AMD configuration registers
|
# Reserve the extended AMD configuration registers
|
||||||
|
@@ -11,7 +11,6 @@ entries
|
|||||||
400 1 e 1 power_on_after_fail
|
400 1 e 1 power_on_after_fail
|
||||||
412 4 e 6 debug_level
|
412 4 e 6 debug_level
|
||||||
444 1 e 1 nmi
|
444 1 e 1 nmi
|
||||||
445 1 e 1 iommu
|
|
||||||
728 256 h 0 user_data
|
728 256 h 0 user_data
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
# Reserve the extended AMD configuration registers
|
# Reserve the extended AMD configuration registers
|
||||||
|
@@ -11,7 +11,6 @@ entries
|
|||||||
400 1 e 1 power_on_after_fail
|
400 1 e 1 power_on_after_fail
|
||||||
412 4 e 6 debug_level
|
412 4 e 6 debug_level
|
||||||
444 1 e 1 nmi
|
444 1 e 1 nmi
|
||||||
445 1 e 1 iommu
|
|
||||||
728 256 h 0 user_data
|
728 256 h 0 user_data
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
# Reserve the extended AMD configuration registers
|
# Reserve the extended AMD configuration registers
|
||||||
|
@@ -11,7 +11,6 @@ entries
|
|||||||
400 1 e 1 power_on_after_fail
|
400 1 e 1 power_on_after_fail
|
||||||
412 4 e 6 debug_level
|
412 4 e 6 debug_level
|
||||||
444 1 e 1 nmi
|
444 1 e 1 nmi
|
||||||
445 1 e 1 iommu
|
|
||||||
728 256 h 0 user_data
|
728 256 h 0 user_data
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
# Reserve the extended AMD configuration registers
|
# Reserve the extended AMD configuration registers
|
||||||
|
@@ -12,7 +12,6 @@ entries
|
|||||||
408 1 e 1 power_on_after_fail
|
408 1 e 1 power_on_after_fail
|
||||||
412 4 e 6 debug_level
|
412 4 e 6 debug_level
|
||||||
444 1 e 1 nmi
|
444 1 e 1 nmi
|
||||||
445 1 e 1 iommu
|
|
||||||
728 256 h 0 user_data
|
728 256 h 0 user_data
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
# Reserve the extended AMD configuration registers
|
# Reserve the extended AMD configuration registers
|
||||||
|
@@ -11,7 +11,6 @@ entries
|
|||||||
400 1 e 1 power_on_after_fail
|
400 1 e 1 power_on_after_fail
|
||||||
412 4 e 6 debug_level
|
412 4 e 6 debug_level
|
||||||
444 1 e 1 nmi
|
444 1 e 1 nmi
|
||||||
445 1 e 1 iommu
|
|
||||||
728 256 h 0 user_data
|
728 256 h 0 user_data
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
# Reserve the extended AMD configuration registers
|
# Reserve the extended AMD configuration registers
|
||||||
|
@@ -11,7 +11,6 @@ entries
|
|||||||
400 1 e 1 power_on_after_fail
|
400 1 e 1 power_on_after_fail
|
||||||
412 4 e 6 debug_level
|
412 4 e 6 debug_level
|
||||||
444 1 e 1 nmi
|
444 1 e 1 nmi
|
||||||
445 1 e 1 iommu
|
|
||||||
728 256 h 0 user_data
|
728 256 h 0 user_data
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
# Reserve the extended AMD configuration registers
|
# Reserve the extended AMD configuration registers
|
||||||
|
@@ -11,7 +11,6 @@ entries
|
|||||||
400 1 e 1 power_on_after_fail
|
400 1 e 1 power_on_after_fail
|
||||||
412 4 e 6 debug_level
|
412 4 e 6 debug_level
|
||||||
444 1 e 1 nmi
|
444 1 e 1 nmi
|
||||||
445 1 e 1 iommu
|
|
||||||
728 256 h 0 user_data
|
728 256 h 0 user_data
|
||||||
984 16 h 0 check_sum
|
984 16 h 0 check_sum
|
||||||
# Reserve the extended AMD configuration registers
|
# Reserve the extended AMD configuration registers
|
||||||
|
Reference in New Issue
Block a user