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soc/mediatek/mt8192: Add PLL and clock init support

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Add PLL and clock init code.

TEST=Boots correctly on MT8192EVB.

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Change-Id: Ia49342c058577e8e107b7e56c867bf21532e40d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This commit is contained in:
Weiyi Lu
2020-05-13 10:01:14 +08:00
committed by Hung-Te Lin
parent 8fcc246a56
commit a4cad368a2
6 changed files with 2201 additions and 3 deletions
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2
src/soc/mediatek/common/include/soc/pll_common.h
View File

@@ -20,6 +20,8 @@
struct mux {
void *reg;
void *set_reg;
void *clr_reg;
void *upd_reg;
u8 mux_shift;
u8 mux_width;

12
src/soc/mediatek/common/pll.c
View File

@@ -12,9 +12,15 @@ void mux_set_sel(const struct mux *mux, u32 sel)
u32 mask = GENMASK(mux->mux_width - 1, 0);
u32 val = read32(mux->reg);
val &= ~(mask << mux->mux_shift);
val |= (sel & mask) << mux->mux_shift;
write32(mux->reg, val);
if (mux->set_reg && mux->clr_reg) {
write32(mux->clr_reg, mask << mux->mux_shift);
write32(mux->set_reg, sel << mux->mux_shift);
} else {
val &= ~(mask << mux->mux_shift);
val |= (sel & mask) << mux->mux_shift;
write32(mux->reg, val);
}
if (mux->upd_reg)
write32(mux->upd_reg, 1 << mux->upd_shift);
}