mainboard/system76/gaze16: Add System76 Gazelle (gaze16)
Change-Id: Ifb90f9b73a10abf53a21738e2c466d539df9a37c Co-authored-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
Jeremy Soller
Tim Crawford
parent
909f958c9e
commit
a4f9ee038e
92
src/mainboard/system76/gaze16/Kconfig
Normal file
92
src/mainboard/system76/gaze16/Kconfig
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@ -0,0 +1,92 @@
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if BOARD_SYSTEM76_GAZE16_3050 || BOARD_SYSTEM76_GAZE16_3060
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_16384
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select DRIVERS_I2C_HID
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select DRIVERS_SYSTEM76_DGPU
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select EC_SYSTEM76_EC
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select EC_SYSTEM76_EC_BAT_THRESHOLDS
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select EC_SYSTEM76_EC_COLOR_KEYBOARD
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select EC_SYSTEM76_EC_DGPU
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select HAVE_CMOS_DEFAULT
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select HAVE_OPTION_TABLE
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select INTEL_GMA_HAVE_VBT
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select INTEL_LPSS_UART_FOR_CONSOLE
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select MAINBOARD_HAS_LPC_TPM
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select MAINBOARD_HAS_TPM2
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select NO_UART_ON_SUPERIO
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select SOC_INTEL_TIGERLAKE
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select SOC_INTEL_TIGERLAKE_PCH_H
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select SOC_INTEL_COMMON_BLOCK_HDA_VERB
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select SPD_READ_BY_WORD
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select SYSTEM_TYPE_LAPTOP
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select TPM_RDRESP_NEED_DELAY
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select USE_OPTION_TABLE
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config MAINBOARD_DIR
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string
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default "system76/gaze16"
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config MAINBOARD_PART_NUMBER
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string
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default "gaze16-3050" if BOARD_SYSTEM76_GAZE16_3050
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default "gaze16-3060" if BOARD_SYSTEM76_GAZE16_3060
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config MAINBOARD_SMBIOS_PRODUCT_NAME
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string
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default "Gazelle"
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config MAINBOARD_VERSION
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string
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default "gaze16-3050" if BOARD_SYSTEM76_GAZE16_3050
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default "gaze16-3060" if BOARD_SYSTEM76_GAZE16_3060
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config VARIANT_DIR
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string
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default "3050" if BOARD_SYSTEM76_GAZE16_3050
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default "3060" if BOARD_SYSTEM76_GAZE16_3060
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config OVERRIDE_DEVICETREE
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string
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default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
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config CBFS_SIZE
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hex
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default 0xA00000
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config CONSOLE_POST
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bool
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default y
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config DIMM_MAX
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int
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default 4 # Hack to make soc code work
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config DIMM_SPD_SIZE
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int
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default 512
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config DRIVERS_SYSTEM76_DGPU_DEVICE
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hex
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default 0x01
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config MAX_CPUS
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int
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default 16
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config ONBOARD_VGA_IS_PRIMARY
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bool
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default y
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config POST_DEVICE
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bool
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default n
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config UART_FOR_CONSOLE
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int
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default 2
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endif
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5
src/mainboard/system76/gaze16/Kconfig.name
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5
src/mainboard/system76/gaze16/Kconfig.name
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@ -0,0 +1,5 @@
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config BOARD_SYSTEM76_GAZE16_3050
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bool "gaze16 3050"
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config BOARD_SYSTEM76_GAZE16_3060
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bool "gaze16 3060"
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11
src/mainboard/system76/gaze16/Makefile.inc
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11
src/mainboard/system76/gaze16/Makefile.inc
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@ -0,0 +1,11 @@
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## SPDX-License-Identifier: GPL-2.0-only
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
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bootblock-y += bootblock.c
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romstage-y += variants/$(VARIANT_DIR)/romstage.c
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ramstage-y += ramstage.c
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ramstage-y += variants/$(VARIANT_DIR)/ramstage.c
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ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
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30
src/mainboard/system76/gaze16/acpi/backlight.asl
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30
src/mainboard/system76/gaze16/acpi/backlight.asl
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@ -0,0 +1,30 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <drivers/intel/gma/acpi/gma.asl>
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Scope (GFX0) {
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Name (BRIG, Package (22) {
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40, /* default AC */
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40, /* default Battery */
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5,
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10,
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15,
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20,
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25,
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30,
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35,
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40,
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45,
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50,
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55,
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60,
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65,
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70,
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75,
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80,
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85,
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90,
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95,
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100
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})
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}
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30
src/mainboard/system76/gaze16/acpi/dgpu.asl
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30
src/mainboard/system76/gaze16/acpi/dgpu.asl
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@ -0,0 +1,30 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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Scope (\_SB.PCI0.RP01) {
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Device (DEV0) {
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Name(_ADR, 0x00000000)
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OperationRegion (PCIC, PCI_Config, 0x00, 0x50)
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Field (PCIC, DwordAcc, NoLock, Preserve) {
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Offset (0x40),
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SSID, 32
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}
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Name (_PR0, Package () { PWRR })
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Name (_PR3, Package () { PWRR })
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PowerResource (PWRR, 0, 0) {
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Name (_STA, 1)
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Method (_ON) {
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^^SSID = 0x50171558
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Printf("GPU _ON %o", ToHexString(^^SSID))
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_STA = 1
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}
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Method (_OFF) {
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Printf("GPU _OFF %o", ToHexString(^^SSID))
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_STA = 0
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}
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}
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}
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}
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15
src/mainboard/system76/gaze16/acpi/mainboard.asl
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15
src/mainboard/system76/gaze16/acpi/mainboard.asl
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@ -0,0 +1,15 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <variant/gpio.h>
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#include "dgpu.asl"
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#define EC_GPE_SCI 0x6E
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#define EC_GPE_SWI 0x6E
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#include <ec/system76/ec/acpi/ec.asl>
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Scope (\_SB) {
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#include "sleep.asl"
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Scope (PCI0) {
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#include "backlight.asl"
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}
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}
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46
src/mainboard/system76/gaze16/acpi/sleep.asl
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46
src/mainboard/system76/gaze16/acpi/sleep.asl
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@ -0,0 +1,46 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <intelblocks/gpio.h>
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Method (PGPM, 1, Serialized)
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{
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For (Local0 = 0, Local0 < 6, Local0++)
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{
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\_SB.PCI0.CGPM (Local0, Arg0)
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}
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}
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/*
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* Method called from _PTS prior to system sleep state entry
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* Enables dynamic clock gating for all 5 GPIO communities
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*/
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Method (MPTS, 1, Serialized)
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{
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\_SB.PCI0.LPCB.EC0.PTS (Arg0)
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PGPM (MISCCFG_ENABLE_GPIO_PM_CONFIG)
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}
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/*
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* Method called from _WAK prior to system sleep state wakeup
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* Disables dynamic clock gating for all 5 GPIO communities
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*/
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Method (MWAK, 1, Serialized)
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{
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PGPM (0)
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\_SB.PCI0.LPCB.EC0.WAK (Arg0)
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}
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/*
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* S0ix Entry/Exit Notifications
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* Called from \_SB.PEPD._DSM
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*/
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Method (MS0X, 1, Serialized)
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{
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If (Arg0 == 1) {
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/* S0ix Entry */
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PGPM (MISCCFG_ENABLE_GPIO_PM_CONFIG)
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} Else {
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/* S0ix Exit */
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PGPM (0)
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}
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}
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8
src/mainboard/system76/gaze16/board_info.txt
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8
src/mainboard/system76/gaze16/board_info.txt
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@ -0,0 +1,8 @@
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Vendor name: System76
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Board name: gaze16
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Category: laptop
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Release year: 2021
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ROM package: SOIC-8
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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11
src/mainboard/system76/gaze16/bootblock.c
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11
src/mainboard/system76/gaze16/bootblock.c
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@ -0,0 +1,11 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootblock_common.h>
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#include <gpio.h>
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#include <variant/gpio.h>
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#include <drivers/system76/dgpu/bootblock.c>
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void bootblock_mainboard_init(void) {
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gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
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dgpu_power_enable(1);
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}
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2
src/mainboard/system76/gaze16/cmos.default
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2
src/mainboard/system76/gaze16/cmos.default
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boot_option=Fallback
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preserve_smmstore=0
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35
src/mainboard/system76/gaze16/cmos.layout
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35
src/mainboard/system76/gaze16/cmos.layout
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@ -0,0 +1,35 @@
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# SPDX-License-Identifier: GPL-2.0-only
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entries
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0 384 r 0 reserved_memory
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# RTC_BOOT_BYTE (coreboot hardcoded)
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384 1 e 2 boot_option
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388 4 h 0 reboot_counter
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#395 4 e 3 debug_level
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408 1 h 1 preserve_smmstore
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984 16 h 0 check_sum
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enumerations
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1 0 Disable
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1 1 Enable
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2 0 Fallback
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2 1 Normal
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3 0 Emergency
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3 1 Alert
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3 2 Critical
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3 3 Error
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3 4 Warning
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3 5 Notice
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3 6 Info
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3 7 Debug
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3 8 Spew
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checksums
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checksum 392 983 984
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176
src/mainboard/system76/gaze16/devicetree.cb
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176
src/mainboard/system76/gaze16/devicetree.cb
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@ -0,0 +1,176 @@
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chip soc/intel/tigerlake
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register "common_soc_config" = "{
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.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
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// Touchpad I2C bus
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.i2c[0] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 80,
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.fall_time_ns = 110,
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},
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}"
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# ACPI (soc/intel/tigerlake/acpi.c)
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# Enable Enhanced Intel SpeedStep
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register "eist_enable" = "1"
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# CPU (soc/intel/tigerlake/cpu.c)
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# Power limits
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register "power_limits_config[POWER_LIMITS_H_8_CORE]" = "{
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// /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw
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.tdp_pl1_override = 45,
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// /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw
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.tdp_pl2_override = 109,
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}"
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register "power_limits_config[POWER_LIMITS_H_6_CORE]" = "{
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// /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw
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.tdp_pl1_override = 45,
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// /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw
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.tdp_pl2_override = 109,
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}"
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# Finalize (soc/intel/tigerlake/finalize.c)
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# PM Timer Disabled, saves power
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register "PmTimerDisabled" = "1"
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# FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c)
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# Enable C6 DRAM
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register "enable_c6dram" = "1"
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# FSP Silicon (soc/intel/tigerlake/fsp_params.c)
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# Acoustic settings
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register "AcousticNoiseMitigation" = "1"
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register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
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register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
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register "SlowSlewRate[VR_DOMAIN_SA]" = "SLEW_FAST_8"
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register "SlowSlewRate[VR_DOMAIN_VLCC]" = "SLEW_FAST_8"
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register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1"
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register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1"
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register "FastPkgCRampDisable[VR_DOMAIN_SA]" = "1"
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register "FastPkgCRampDisable[VR_DOMAIN_VLCC]" = "1"
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# FIVR configuration
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# Read EXT_RAIL_CONFIG to determine bitmaps
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# sudo devmem2 0xfe0011b8
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# 0x0
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# Read EXT_V1P05_VR_CONFIG
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# sudo devmem2 0xfe0011c0
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# 0x1a42000
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# Read EXT_VNN_VR_CONFIG0
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# sudo devmem2 0xfe0011c4
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# 0x1a42000
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# TODO: v1p05 voltage and vnn icc max?
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register "ext_fivr_settings" = "{
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.configure_ext_fivr = 1,
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.v1p05_enable_bitmap = 0,
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.vnn_enable_bitmap = 0,
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.v1p05_supported_voltage_bitmap = 0,
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.vnn_supported_voltage_bitmap = 0,
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.v1p05_icc_max_ma = 500,
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.vnn_sx_voltage_mv = 1050,
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}"
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# Read LPM_EN, make sure to invert the bits
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# sudo devmem2 0xfe001c78
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# 0x9
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register "LpmStateDisableMask" = "
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LPM_S0i2_1 |
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LPM_S0i2_2 |
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LPM_S0i3_1 |
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LPM_S0i3_2 |
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LPM_S0i3_3 |
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LPM_S0i3_4
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"
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# Thermal
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# rdmsr --bitfield 31:24 --decimal 0x1A2
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register "tcc_offset" = "8"
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# PM Util (soc/intel/tigerlake/pmutil.c)
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# GPE configuration
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# sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
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# 0x432
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register "pmc_gpe0_dw0" = "PMC_GPP_R"
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register "pmc_gpe0_dw1" = "PMC_GPP_B"
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register "pmc_gpe0_dw2" = "PMC_GPP_D"
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# Actual device tree
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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#From CPU EDS(575683)
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device ref system_agent on end
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device ref igpu on
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# DDIA is eDP
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register "DdiPortAConfig" = "1"
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register "DdiPortAHpd" = "1"
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register "DdiPortADdc" = "0"
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# DDIB is HDMI
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register "DdiPortBConfig" = "0"
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register "DdiPortBHpd" = "1"
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register "DdiPortBDdc" = "1"
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register "gfx" = "GMA_STATIC_DISPLAYS(0)"
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end
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device ref dptf on
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register "Device4Enable" = "1"
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end
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device ref gna on end
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# From PCH EDS(615985)
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device ref cnvi_bt on end
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device ref shared_ram on end
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device ref cnvi_wifi on
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chip drivers/wifi/generic
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register "wake" = "GPE0_PME_B0"
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device generic 0 on end
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end
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end
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device ref i2c0 on
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# Touchpad I2C bus
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register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
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chip drivers/i2c/hid
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register "generic.hid" = ""ELAN0412""
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register "generic.desc" = ""ELAN Touchpad""
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register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_R12)"
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register "generic.probed" = "1"
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register "hid_desc_reg_offset" = "0x01"
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device i2c 15 on end
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||||
end
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end
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device ref heci1 on
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||||
#TODO Disable ME and HECI
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register "HeciEnabled" = "1"
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end
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device ref uart2 on
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# Debug console
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register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit"
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||||
end
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||||
device ref pch_espi on
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||||
# LPC configuration from lspci -s 1f.0 -xxx
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||||
# Address 0x84: Decode 0x80 - 0x8F (Port 80)
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||||
register "gen1_dec" = "0x000c0081"
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||||
# Address 0x88: Decode 0x68 - 0x6F (PMC)
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||||
register "gen2_dec" = "0x00040069"
|
||||
# Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command)
|
||||
register "gen3_dec" = "0x00fc0E01"
|
||||
# Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug)
|
||||
register "gen4_dec" = "0x00fc0F01"
|
||||
# LPC TPM
|
||||
chip drivers/pc80/tpm
|
||||
device pnp 0c31.0 on end
|
||||
end
|
||||
end
|
||||
device ref p2sb on end
|
||||
device ref pmc hidden end
|
||||
device ref hda on
|
||||
register "PchHdaAudioLinkHdaEnable" = "1"
|
||||
end
|
||||
device ref smbus on
|
||||
register "SmbusEnable" = "1"
|
||||
end
|
||||
device ref fast_spi on end
|
||||
end
|
||||
end
|
||||
31
src/mainboard/system76/gaze16/dsdt.asl
Normal file
31
src/mainboard/system76/gaze16/dsdt.asl
Normal file
@ -0,0 +1,31 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <acpi/acpi.h>
|
||||
DefinitionBlock(
|
||||
"dsdt.aml",
|
||||
"DSDT",
|
||||
ACPI_DSDT_REV_2,
|
||||
OEM_ID,
|
||||
ACPI_TABLE_CREATOR,
|
||||
0x20110725 // OEM revision
|
||||
)
|
||||
{
|
||||
#include <soc/intel/common/block/acpi/acpi/platform.asl>
|
||||
#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
|
||||
#include <cpu/intel/common/acpi/cpu.asl>
|
||||
|
||||
Device (\_SB.PCI0)
|
||||
{
|
||||
#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
|
||||
#include <soc/intel/tigerlake/acpi/southbridge.asl>
|
||||
}
|
||||
|
||||
#include <southbridge/intel/common/acpi/sleepstates.asl>
|
||||
|
||||
Scope (\_SB.PCI0.LPCB)
|
||||
{
|
||||
#include <drivers/pc80/pc/ps2_controller.asl>
|
||||
}
|
||||
|
||||
#include "acpi/mainboard.asl"
|
||||
}
|
||||
15
src/mainboard/system76/gaze16/ramstage.c
Normal file
15
src/mainboard/system76/gaze16/ramstage.c
Normal file
@ -0,0 +1,15 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <soc/ramstage.h>
|
||||
#include <variant/gpio.h>
|
||||
#include "variant.h"
|
||||
|
||||
void mainboard_silicon_init_params(FSP_S_CONFIG *params)
|
||||
{
|
||||
variant_silicon_init_params(params);
|
||||
|
||||
// Low latency legacy I/O
|
||||
params->PchLegacyIoLowLatency = 1;
|
||||
|
||||
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
|
||||
}
|
||||
34
src/mainboard/system76/gaze16/romstage.c
Normal file
34
src/mainboard/system76/gaze16/romstage.c
Normal file
@ -0,0 +1,34 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <fsp/util.h>
|
||||
#include <soc/meminit.h>
|
||||
#include <soc/romstage.h>
|
||||
#include "variant.h"
|
||||
|
||||
static const struct mb_ddr4_cfg board_cfg = {
|
||||
// dq_map unused on DDR4
|
||||
// dqs_map unused on DDR4
|
||||
|
||||
.dq_pins_interleaved = 1,
|
||||
.ect = 0,
|
||||
};
|
||||
|
||||
static const struct spd_info spd = {
|
||||
.topology = SODIMM,
|
||||
.smbus_info[0] = {
|
||||
.addr_dimm0 = 0x50,
|
||||
},
|
||||
.smbus_info[1] = {
|
||||
.addr_dimm0 = 0x52,
|
||||
},
|
||||
};
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *mupd) {
|
||||
variant_memory_init_params(mupd);
|
||||
|
||||
// Set primary display to internal graphics
|
||||
mupd->FspmConfig.PrimaryDisplay = 0;
|
||||
|
||||
const bool half_populated = false;
|
||||
meminit_ddr4(&mupd->FspmConfig, &board_cfg, &spd, half_populated);
|
||||
}
|
||||
11
src/mainboard/system76/gaze16/variant.h
Normal file
11
src/mainboard/system76/gaze16/variant.h
Normal file
@ -0,0 +1,11 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef VARIANT_H
|
||||
#define VARIANT_H
|
||||
|
||||
#include <fsp/soc_binding.h>
|
||||
|
||||
void variant_memory_init_params(FSPM_UPD *);
|
||||
void variant_silicon_init_params(FSP_S_CONFIG *);
|
||||
|
||||
#endif
|
||||
29
src/mainboard/system76/gaze16/variants/3050/hda_verb.c
Normal file
29
src/mainboard/system76/gaze16/variants/3050/hda_verb.c
Normal file
@ -0,0 +1,29 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC256 */
|
||||
0x10ec0256, /* Vendor ID */
|
||||
0x15585017, /* Subsystem ID */
|
||||
11, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x15585017),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||
AZALIA_PIN_CFG(0, 0x13, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x02a11040),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x41700001),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x21, 0x02211020),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {
|
||||
// Adjust coeff for mic
|
||||
0x02050007,
|
||||
0x02040202,
|
||||
};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
@ -0,0 +1,518 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#define DGPU_RST_N GPP_F8
|
||||
#define DGPU_PWR_EN GPP_F9
|
||||
#define DGPU_GC6 GPP_K11
|
||||
|
||||
#ifndef __ACPI__
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
/* Pad configuration in romstage. */
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
PAD_CFG_GPI(GPP_C20, NONE, DEEP), // UART2_RXD
|
||||
PAD_CFG_GPI(GPP_C21, NONE, DEEP), // UART2_TXD
|
||||
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
|
||||
PAD_CFG_TERM_GPO(DGPU_RST_N, 0, NONE, DEEP), // DGPU_RST#_PCH
|
||||
PAD_CFG_TERM_GPO(DGPU_PWR_EN, 0, NONE, DEEP), // DGPU_PWR_EN
|
||||
};
|
||||
|
||||
/* Pad configuration in ramstage. */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
// BATLOW#
|
||||
PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),
|
||||
// AC_PRESENT
|
||||
PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
|
||||
// LAN_WAKE#
|
||||
PAD_CFG_GPI(GPD2, NATIVE, PWROK),
|
||||
// PWR_BTN#
|
||||
PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
|
||||
// SUSB#_PCH
|
||||
PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
|
||||
// SUSC#_PCH
|
||||
PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
|
||||
// SLP_A#
|
||||
PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
|
||||
// GPD7
|
||||
PAD_CFG_GPI(GPD7, NONE, PWROK),
|
||||
// SUS_CLK
|
||||
PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
|
||||
// PCH_SLP_WLAN#
|
||||
PAD_CFG_GPO(GPD9, 0, PWROK),
|
||||
// SLP_S5#
|
||||
PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
|
||||
// LAN_DISABLE#
|
||||
PAD_CFG_GPI(GPD11, NONE, PWROK),
|
||||
// Test point
|
||||
_PAD_CFG_STRUCT(GPD12, 0x04000300, 0x0000),
|
||||
// ESPI_AD0
|
||||
PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1),
|
||||
// ESPI_AD1
|
||||
PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
|
||||
// ESPI_AD2
|
||||
PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
|
||||
// ESPI_AD3
|
||||
PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
|
||||
// ESPI_FRAME#
|
||||
PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
|
||||
// ESPI_KBC
|
||||
PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1),
|
||||
// ESPI_RESET_N
|
||||
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
|
||||
// GPP_A7
|
||||
PAD_CFG_GPI(GPP_A7, UP_20K, DEEP),
|
||||
// GPP_A8
|
||||
PAD_CFG_GPI(GPP_A8, UP_20K, DEEP),
|
||||
// GPP_A9
|
||||
PAD_CFG_GPI(GPP_A9, UP_20K, DEEP),
|
||||
// SERIRQ
|
||||
PAD_CFG_GPI(GPP_A10, UP_20K, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_A11, UP_20K, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_A12, UP_20K, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_A13, UP_20K, DEEP),
|
||||
// PM_CLKRUN#
|
||||
PAD_CFG_GPI(GPP_A14, NONE, DEEP),
|
||||
// TPM_PIRQ#
|
||||
_PAD_CFG_STRUCT(GPP_B0, 0x40100100, 0x3000),
|
||||
// GPP_B1
|
||||
PAD_CFG_GPI(GPP_B1, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_B2, NONE, DEEP),
|
||||
// BT_EN_PCH
|
||||
PAD_CFG_GPO(GPP_B3, 1, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_B4, NONE, DEEP),
|
||||
// GFX_CLKREQ0#
|
||||
PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_B6, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_B7, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_B8, NONE, DEEP),
|
||||
// SSD2_CLKREQ4#
|
||||
PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
|
||||
// LAN_CLKREQ5#
|
||||
PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_B11, NONE, DEEP),
|
||||
// SLP_S0#
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
// PLT_RST#
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
// PCH_SPKR
|
||||
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
|
||||
// SSD_PWR_EN#
|
||||
PAD_CFG_GPO(GPP_B15, 1, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_B16, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_B17, NONE, DEEP),
|
||||
// GSPI0_MOSI
|
||||
PAD_CFG_GPI(GPP_B18, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_B19, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_B20, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_B21, NONE, DEEP),
|
||||
// GSPI1_MOSI
|
||||
PAD_CFG_GPI(GPP_B22, NONE, DEEP),
|
||||
// SML1_ALERT#
|
||||
PAD_CFG_GPI(GPP_B23, NONE, DEEP),
|
||||
// SMB_CLK
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
// SMB_DAT
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
// CNVI_WAKE#
|
||||
PAD_CFG_GPI(GPP_C2, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_C3, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_C4, NONE, DEEP),
|
||||
// SML0_ALERT#
|
||||
PAD_CFG_GPI(GPP_C5, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_C6, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_C7, NONE, DEEP),
|
||||
// TPM_DET
|
||||
PAD_CFG_GPI(GPP_C8, NONE, DEEP),
|
||||
// BOARD_ID1
|
||||
PAD_CFG_GPI(GPP_C9, NONE, DEEP),
|
||||
// BOARD_ID2
|
||||
PAD_CFG_GPI(GPP_C10, NONE, DEEP),
|
||||
// BOARD_ID3
|
||||
PAD_CFG_GPI(GPP_C11, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_C12, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_C13, NONE, DEEP),
|
||||
// GPC14_RTD3
|
||||
PAD_CFG_GPI(GPP_C14, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_C15, NONE, DEEP),
|
||||
// I2C_SDA_TP
|
||||
PAD_CFG_NF(GPP_C16, NONE, PWROK, NF1),
|
||||
// I2C_SCL_TP
|
||||
PAD_CFG_NF(GPP_C17, NONE, PWROK, NF1),
|
||||
// SCI#
|
||||
PAD_CFG_GPI(GPP_C18, NONE, DEEP),
|
||||
// SWI#
|
||||
PAD_CFG_GPI(GPP_C19, NONE, DEEP),
|
||||
/* Configured in early_gpio_table
|
||||
* // UART2_RXD
|
||||
* PAD_CFG_GPI(GPP_C20, NONE, DEEP),
|
||||
* // UART2_TXD
|
||||
* PAD_CFG_GPI(GPP_C21, NONE, DEEP),
|
||||
*/
|
||||
// UART2_RTS#
|
||||
PAD_CFG_GPO(GPP_C22, 1, DEEP),
|
||||
// SMI#
|
||||
PAD_CFG_GPI(GPP_C23, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_D0, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_D1, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_D2, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_D3, NONE, DEEP),
|
||||
// SML1_CLK
|
||||
PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1),
|
||||
// CNVI_RF_RST#
|
||||
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF2),
|
||||
// XTAL_CLKREQ
|
||||
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_D7, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_D8, NONE, DEEP),
|
||||
// SML0_CLK
|
||||
PAD_CFG_NF(GPP_D9, NONE, DEEP, NF1),
|
||||
// SML0_DATA
|
||||
PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_D11, NATIVE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_D12, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_D13, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_D14, NONE, DEEP),
|
||||
// SML1_DATA
|
||||
PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_D16, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_D17, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_D18, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_D19, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_D20, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_D21, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_D22, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_D23, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_E0, NONE, DEEP),
|
||||
// SATAGP1
|
||||
PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_E2, NONE, DEEP),
|
||||
// SMI#
|
||||
PAD_CFG_GPI(GPP_E3, NONE, DEEP),
|
||||
// DEVSLP0
|
||||
PAD_CFG_GPI(GPP_E4, NONE, DEEP),
|
||||
// DEVSLP1
|
||||
PAD_CFG_NF(GPP_E5, NONE, PWROK, NF1),
|
||||
// PCH_MUTE#
|
||||
PAD_CFG_GPI(GPP_E6, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_E7, NONE, DEEP),
|
||||
// SATA_LED#
|
||||
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
|
||||
// USB_OC0#
|
||||
PAD_CFG_GPI(GPP_E9, NONE, DEEP),
|
||||
// USB_OC1#
|
||||
PAD_CFG_GPI(GPP_E10, NONE, DEEP),
|
||||
// USB_OC2#
|
||||
PAD_CFG_GPI(GPP_E11, NONE, DEEP),
|
||||
// USB_OC3#
|
||||
PAD_CFG_GPI(GPP_E12, NONE, DEEP),
|
||||
// SATAGP3
|
||||
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF2),
|
||||
// SATAGP4
|
||||
PAD_CFG_GPI(GPP_F1, NONE, DEEP),
|
||||
// LAN_RTD3#
|
||||
PAD_CFG_GPO(GPP_F2, 1, PLTRST),
|
||||
// GPP_LAN_RST#
|
||||
PAD_CFG_GPO(GPP_F3, 1, DEEP),
|
||||
// SATA_PWR_EN
|
||||
PAD_CFG_GPO(GPP_F4, 1, DEEP),
|
||||
// 1P05_CTRL
|
||||
PAD_CFG_GPO(GPP_F5, 1, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_F6, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_F7, NONE, DEEP),
|
||||
/* GPU enabled or not in bootblock.c
|
||||
* // DGPU_RST#_PCH
|
||||
* PAD_CFG_GPO(GPP_F8, 1, DEEP),
|
||||
* // DGPU_PWR_EN
|
||||
* PAD_CFG_GPO(GPP_F9, 1, DEEP),
|
||||
*/
|
||||
// BIOS_REC
|
||||
PAD_CFG_GPI(GPP_F10, NONE, DEEP),
|
||||
// PCH_RSVD
|
||||
PAD_CFG_GPI(GPP_F11, NONE, DEEP),
|
||||
// PCH_WLAN_EN
|
||||
PAD_CFG_GPO(GPP_F12, 1, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_F13, NONE, DEEP),
|
||||
// PS_ON#
|
||||
PAD_CFG_GPI(GPP_F14, NONE, DEEP),
|
||||
// SKTOCC#
|
||||
PAD_CFG_GPI(GPP_F15, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_F16, NONE, DEEP),
|
||||
// SB_BLON
|
||||
PAD_CFG_GPO(GPP_F17, 1, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_F18, NONE, DEEP),
|
||||
// NB_ENAVDD
|
||||
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
|
||||
// BLON
|
||||
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
|
||||
// EDP_BRIGHTNESS
|
||||
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
|
||||
// VNN_CTRL
|
||||
PAD_NC(GPP_F22, NONE),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_F23, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_G0, NONE, DEEP),
|
||||
// CNVI_DET#
|
||||
PAD_CFG_GPI(GPP_G1, NONE, DEEP),
|
||||
// Test Point
|
||||
PAD_CFG_GPI(GPP_G2, DN_20K, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_G3, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_G4, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_G5, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_G6, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_G7, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_G8, NATIVE, DEEP),
|
||||
// GPP_G9
|
||||
PAD_CFG_GPI(GPP_G9, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_G10, NATIVE, DEEP),
|
||||
// GPP_G11
|
||||
PAD_CFG_GPI(GPP_G11, NONE, DEEP),
|
||||
// NC
|
||||
_PAD_CFG_STRUCT(GPP_G12, 0x44001300, 0x3c00),
|
||||
// GPP_G13
|
||||
_PAD_CFG_STRUCT(GPP_G13, 0x44001300, 0x3c00),
|
||||
// PCH_MDP_CLK
|
||||
PAD_CFG_GPI(GPP_G14, NATIVE, DEEP),
|
||||
// PCH_MDP_DATA
|
||||
PAD_CFG_GPI(GPP_G15, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_H0, NONE, DEEP),
|
||||
// CARD_CLKREQ7#
|
||||
PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1),
|
||||
// WLAN_CLKREQ8#
|
||||
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),
|
||||
// SSD1_CLKREQ9#
|
||||
PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_H4, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_H5, NONE, DEEP),
|
||||
// SB_KBCRST#
|
||||
PAD_CFG_GPI(GPP_H6, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_H7, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_H8, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_H9, NONE, DEEP),
|
||||
// SML_2CLK
|
||||
PAD_CFG_GPI(GPP_H10, NONE, DEEP),
|
||||
// SML_2DATA
|
||||
PAD_CFG_GPI(GPP_H11, NONE, DEEP),
|
||||
// SML_2ALERT#
|
||||
PAD_CFG_GPI(GPP_H12, NONE, DEEP),
|
||||
// SML_3CLK
|
||||
PAD_CFG_GPI(GPP_H13, NONE, DEEP),
|
||||
// SML_3DATA
|
||||
PAD_CFG_GPI(GPP_H14, NONE, DEEP),
|
||||
// SML_3ALERT#
|
||||
PAD_CFG_GPI(GPP_H15, NONE, PLTRST),
|
||||
// SML_4CLK
|
||||
PAD_CFG_GPI(GPP_H16, NONE, DEEP),
|
||||
// SSD2_PWR_EN#
|
||||
PAD_CFG_GPO(GPP_H17, 1, DEEP),
|
||||
// SML_4ALERT#
|
||||
PAD_CFG_GPI(GPP_H18, NONE, DEEP),
|
||||
// PCH_FLASH_I2C_SDA
|
||||
PAD_CFG_GPI(GPP_H19, NONE, DEEP),
|
||||
// PCH_FLASH_I2C_SCL
|
||||
PAD_CFG_GPI(GPP_H20, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_H21, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_H22, NONE, DEEP),
|
||||
// M2_SSD_RST#
|
||||
PAD_CFG_GPO(GPP_H23, 1, DEEP),
|
||||
// PMC_ALERT#
|
||||
PAD_CFG_NF(GPP_I0, NONE, PWROK, NF1),
|
||||
// GPU_EVENT#
|
||||
PAD_CFG_GPI(GPP_I1, NONE, DEEP),
|
||||
// GPP_I3 (sic)
|
||||
PAD_CFG_GPI(GPP_I2, NONE, DEEP),
|
||||
// GPP_I4 (sic)
|
||||
PAD_CFG_GPI(GPP_I3, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_I4, NONE, DEEP),
|
||||
// HDMI_CTRLCLK
|
||||
PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1),
|
||||
// HDMI_CTRLDATA
|
||||
PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_I7, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_I8, NONE, DEEP),
|
||||
// M2_SSD2_RST#
|
||||
PAD_CFG_GPO(GPP_I9, 1, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_I10, DN_20K, DEEP),
|
||||
// USB_OC4#
|
||||
PAD_CFG_GPI(GPP_I11, NONE, PLTRST),
|
||||
// USB_OC5#
|
||||
PAD_CFG_GPI(GPP_I12, NONE, PLTRST),
|
||||
// USB_OC6#
|
||||
PAD_CFG_GPI(GPP_I13, NONE, PLTRST),
|
||||
// USB_OC7#
|
||||
PAD_CFG_GPI(GPP_I14, NONE, PLTRST),
|
||||
// CNVI_GNSS_PA_BLANKING
|
||||
PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1),
|
||||
// CPU_C10_GATE#
|
||||
PAD_CFG_NF(GPP_J1, NONE, DEEP, NF1),
|
||||
// CNVI_BRI_DT
|
||||
PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1),
|
||||
// CNVI_BRI_RSP
|
||||
PAD_CFG_NF(GPP_J3, UP_20K, DEEP, NF1),
|
||||
// CNVI_RGI_DT
|
||||
PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1),
|
||||
// CNVI_RGI_RSP
|
||||
PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1),
|
||||
// CNVI_MFUART2_RXD
|
||||
PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1),
|
||||
// CNVI_MFUART2_TXD
|
||||
PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1),
|
||||
// GPIO4_GC6_NVDD_EN_R
|
||||
PAD_CFG_GPI(GPP_J8, NONE, PLTRST),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_J9, NONE, DEEP),
|
||||
// DGPU_OVRM
|
||||
PAD_CFG_GPO(GPP_K0, 0, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_K1, NONE, DEEP),
|
||||
// DGPU_PWRGD_R
|
||||
PAD_CFG_GPI(GPP_K2, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_K3, NONE, DEEP),
|
||||
// Test Point
|
||||
PAD_CFG_GPI(GPP_K4, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_K5, NONE, DEEP),
|
||||
// EDP_HPD
|
||||
PAD_CFG_NF(GPP_K6, NONE, DEEP, NF1),
|
||||
// HDMI_HPD
|
||||
PAD_CFG_NF(GPP_K7, NONE, DEEP, NF1),
|
||||
// VCCIN_AUX_VID0
|
||||
PAD_CFG_NF(GPP_K8, NONE, DEEP, NF1),
|
||||
// VCCIN_AUX_VID1
|
||||
PAD_CFG_NF(GPP_K9, NONE, DEEP, NF1),
|
||||
// DGPU_MDP_HPD
|
||||
_PAD_CFG_STRUCT(GPP_K10, 0x46880100, 0x0000),
|
||||
// GC6_FB_EN_PCH
|
||||
PAD_CFG_GPI(GPP_K11, DN_20K, DEEP),
|
||||
// HDA_BITCLK
|
||||
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
|
||||
// HDA_SYNC
|
||||
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
|
||||
// HDA_SDOUT
|
||||
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
|
||||
// HDA_SDIN0
|
||||
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
|
||||
// AZ_RST#_R / ME_WE
|
||||
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),
|
||||
// Test Point
|
||||
PAD_CFG_GPI(GPP_R5, NONE, DEEP),
|
||||
// Test Point
|
||||
PAD_CFG_GPI(GPP_R6, NONE, DEEP),
|
||||
// 100k pull-down
|
||||
PAD_CFG_GPI(GPP_R7, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_R8, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_R9, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_R10, NONE, DEEP),
|
||||
// ISH_GP_6_R
|
||||
PAD_CFG_GPI(GPP_R11, NONE, DEEP),
|
||||
// TP_ATTN#
|
||||
PAD_CFG_GPI_INT(GPP_R12, NONE, PLTRST, LEVEL),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_R13, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_R14, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_R15, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_R16, NONE, DEEP),
|
||||
// 3G_CONFIG2
|
||||
PAD_CFG_GPI(GPP_R17, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_R18, NONE, DEEP),
|
||||
// DGPU_PWM_SELECT#
|
||||
PAD_CFG_GPI(GPP_R19, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_S0, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_S1, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_S2, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_S3, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_S4, NONE, DEEP),
|
||||
// NC
|
||||
PAD_CFG_GPI(GPP_S5, NONE, DEEP),
|
||||
// DMIC_CLK_PCH
|
||||
PAD_CFG_GPI(GPP_S6, NONE, DEEP),
|
||||
// DMIC_DAT_PCH
|
||||
PAD_CFG_GPI(GPP_S7, NONE, DEEP),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
75
src/mainboard/system76/gaze16/variants/3050/overridetree.cb
Normal file
75
src/mainboard/system76/gaze16/variants/3050/overridetree.cb
Normal file
@ -0,0 +1,75 @@
|
||||
chip soc/intel/tigerlake
|
||||
device domain 0 on
|
||||
device ref peg1 on
|
||||
# PCIe PEG2 (remapped to PEG1 by FSP) x8, Clock 0 (DGPU)
|
||||
register "PcieClkSrcUsage[0]" = "0x42"
|
||||
register "PcieClkSrcClkReq[0]" = "0"
|
||||
chip soc/intel/common/block/pcie/rtd3
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # DGPU_PWR_EN
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F8)" # DGPU_RST#_PCH
|
||||
register "enable_delay_ms" = "16"
|
||||
register "enable_off_delay_ms" = "4"
|
||||
register "reset_delay_ms" = "10"
|
||||
register "reset_off_delay_ms" = "4"
|
||||
#TODO: Support disable/enable CPU RP clock
|
||||
register "srcclk_pin" = "-1" # GFX_CLKREQ0#
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref peg0 on
|
||||
# PCIe PEG0 x4, Clock 4 (SSD2)
|
||||
register "PcieClkSrcUsage[4]" = "0x40"
|
||||
register "PcieClkSrcClkReq[4]" = "4"
|
||||
|
||||
#TODO: Hybrid storage mode?
|
||||
register "HybridStorageMode" = "0"
|
||||
end
|
||||
device ref south_xhci on
|
||||
# USB2
|
||||
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 1 (Right)
|
||||
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.2 Gen 2 Type C (Right)
|
||||
register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 1 (Left)
|
||||
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB 2.0 (Left)
|
||||
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
|
||||
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
|
||||
register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
|
||||
# USB3
|
||||
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 2 (Right)
|
||||
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 2 Type C (Right)
|
||||
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 2 Type C (Right)
|
||||
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 1 (Left)
|
||||
end
|
||||
device ref sata on
|
||||
register "SataPortsEnable[0]" = "1" # HDD (SATA0B)
|
||||
register "SataPortsEnable[1]" = "1" # SSD1 (SATA1A)
|
||||
end
|
||||
device ref pcie_rp5 on
|
||||
# PCIe root port #5 x1, Clock 5 (GLAN)
|
||||
register "PcieRpEnable[4]" = "1"
|
||||
register "PcieRpLtrEnable[4]" = "1"
|
||||
register "PcieClkSrcUsage[5]" = "4"
|
||||
register "PcieClkSrcClkReq[5]" = "5"
|
||||
end
|
||||
device ref pcie_rp7 on
|
||||
# PCIe root port #7 x1, Clock 7 (CARD)
|
||||
register "PcieRpEnable[6]" = "1"
|
||||
register "PcieRpLtrEnable[6]" = "1"
|
||||
register "PcieClkSrcUsage[7]" = "6"
|
||||
register "PcieClkSrcClkReq[7]" = "7"
|
||||
end
|
||||
device ref pcie_rp8 on
|
||||
# PCIe root port #8 x1, Clock 8 (WLAN)
|
||||
register "PcieRpEnable[7]" = "1"
|
||||
register "PcieRpLtrEnable[7]" = "1"
|
||||
register "PcieClkSrcUsage[8]" = "7"
|
||||
register "PcieClkSrcClkReq[8]" = "8"
|
||||
end
|
||||
device ref pcie_rp9 on
|
||||
# PCIe root port #9 x4, Clock 9 (SSD1)
|
||||
register "PcieRpEnable[8]" = "1"
|
||||
register "PcieRpLtrEnable[8]" = "1"
|
||||
register "PcieClkSrcUsage[9]" = "8"
|
||||
register "PcieClkSrcClkReq[9]" = "9"
|
||||
end
|
||||
end
|
||||
end
|
||||
19
src/mainboard/system76/gaze16/variants/3050/ramstage.c
Normal file
19
src/mainboard/system76/gaze16/variants/3050/ramstage.c
Normal file
@ -0,0 +1,19 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include "../../variant.h"
|
||||
|
||||
void variant_silicon_init_params(FSP_S_CONFIG *params)
|
||||
{
|
||||
// PEG0 Config
|
||||
params->CpuPcieRpAdvancedErrorReporting[0] = 0;
|
||||
params->CpuPcieRpLtrEnable[0] = 1;
|
||||
params->CpuPcieRpPtmEnabled[0] = 0;
|
||||
|
||||
// PEG2 Config
|
||||
params->CpuPcieRpAdvancedErrorReporting[2] = 0;
|
||||
params->CpuPcieRpLtrEnable[2] = 1;
|
||||
params->CpuPcieRpPtmEnabled[2] = 0;
|
||||
|
||||
// Remap PEG2 as PEG1
|
||||
params->CpuPcieRpFunctionSwap = 1;
|
||||
}
|
||||
9
src/mainboard/system76/gaze16/variants/3050/romstage.c
Normal file
9
src/mainboard/system76/gaze16/variants/3050/romstage.c
Normal file
@ -0,0 +1,9 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include "../../variant.h"
|
||||
|
||||
void variant_memory_init_params(FSPM_UPD *mupd)
|
||||
{
|
||||
// Enable M.2 PCIE 4.0 and PEG2
|
||||
mupd->FspmConfig.CpuPcieRpEnableMask = 0b101;
|
||||
}
|
||||
25
src/mainboard/system76/gaze16/variants/3060/hda_verb.c
Normal file
25
src/mainboard/system76/gaze16/variants/3060/hda_verb.c
Normal file
@ -0,0 +1,25 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC256 */
|
||||
0x10ec0256, /* Vendor ID */
|
||||
0x155850e2, /* Subsystem ID */
|
||||
11, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x155850e2),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||
AZALIA_PIN_CFG(0, 0x13, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x02a11040),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x41789c6d),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x21, 0x02211020),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
@ -0,0 +1,297 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#define DGPU_RST_N GPP_F8
|
||||
#define DGPU_PWR_EN GPP_F9
|
||||
#define DGPU_GC6 GPP_K11
|
||||
|
||||
#ifndef __ACPI__
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
|
||||
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
|
||||
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
|
||||
PAD_CFG_GPO(DGPU_RST_N, 0, DEEP), // DGPU_RST#_PCH
|
||||
PAD_CFG_GPO(DGPU_PWR_EN, 0, DEEP), // DGPU_PWR_EN
|
||||
};
|
||||
|
||||
static const struct pad_config gpio_table[] = {
|
||||
/* ------- GPIO Group GPD ------- */
|
||||
PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW#
|
||||
PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT
|
||||
PAD_CFG_GPI(GPD2, NATIVE, PWROK), // LAN_WAKEUP#
|
||||
PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN#
|
||||
PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH
|
||||
PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH
|
||||
PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A#
|
||||
PAD_CFG_GPI(GPD7, NONE, PWROK), // GPD_7
|
||||
PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK
|
||||
PAD_NC(GPD9, NONE), // SLP_WLAN#
|
||||
PAD_NC(GPD10, NONE), // SLP_S5#
|
||||
PAD_CFG_GPI(GPD11, NONE, PWROK), // LAN_DISABLE#
|
||||
PAD_NC(GPD12, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_A ------- */
|
||||
PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0
|
||||
PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1
|
||||
PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2
|
||||
PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3
|
||||
PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS#
|
||||
PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1), // ESPI_CLK
|
||||
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // ESPI_RESET_N
|
||||
PAD_NC(GPP_A7, UP_20K),
|
||||
PAD_NC(GPP_A8, UP_20K),
|
||||
PAD_NC(GPP_A9, UP_20K),
|
||||
PAD_CFG_GPI(GPP_A10, UP_20K, DEEP), // ESPI_ALRT#
|
||||
_PAD_CFG_STRUCT(GPP_A11, 0x80100100, 0x0000), // INTP_OUT
|
||||
PAD_NC(GPP_A12, UP_20K),
|
||||
PAD_NC(GPP_A13, UP_20K),
|
||||
PAD_NC(GPP_A14, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_B ------- */
|
||||
_PAD_CFG_STRUCT(GPP_B0, 0x40100100, 0x0000), // TPM_PIRQ#
|
||||
PAD_NC(GPP_B1, NONE),
|
||||
PAD_CFG_GPI(GPP_B2, NONE, DEEP), // VRALERT#_PD
|
||||
PAD_CFG_GPO(GPP_B3, 1, DEEP), // BT_EN
|
||||
PAD_NC(GPP_B4, NONE), // 10k pull-up
|
||||
PAD_NC(GPP_B5, NONE),
|
||||
PAD_NC(GPP_B6, NONE),
|
||||
PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), // WLAN_CLKREQ#
|
||||
PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), // CARD_CLKREQ#
|
||||
PAD_NC(GPP_B9, NONE),
|
||||
PAD_NC(GPP_B10, NONE),
|
||||
PAD_NC(GPP_B11, NONE),
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
|
||||
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR
|
||||
PAD_CFG_GPO(GPP_B15, 1, DEEP), // SATA_M2_PWR_EN1
|
||||
PAD_NC(GPP_B16, NONE),
|
||||
PAD_NC(GPP_B17, NONE),
|
||||
PAD_CFG_GPI(GPP_B18, NONE, DEEP), // NO REBOOT strap
|
||||
PAD_NC(GPP_B19, NONE),
|
||||
PAD_NC(GPP_B20, NONE),
|
||||
PAD_NC(GPP_B21, NONE),
|
||||
PAD_CFG_GPI(GPP_B22, NONE, DEEP), // BOOT strap
|
||||
PAD_CFG_GPI(GPP_B23, NONE, DEEP), // CPUNSSC clock
|
||||
|
||||
/* ------- GPIO Group GPP_C ------- */
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DAT
|
||||
PAD_CFG_GPI(GPP_C2, NONE, DEEP), // SKIN_THRM_SNSR_ALERT_N
|
||||
PAD_NC(GPP_C3, NONE),
|
||||
PAD_NC(GPP_C4, NONE),
|
||||
PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1), // eSPI/LPC select strap
|
||||
PAD_NC(GPP_C6, NONE),
|
||||
PAD_NC(GPP_C7, NONE),
|
||||
PAD_CFG_GPI(GPP_C8, NONE, DEEP), // TPM_DET
|
||||
PAD_CFG_GPI(GPP_C9, NONE, DEEP), // BOARD_ID1
|
||||
PAD_CFG_GPI(GPP_C10, NONE, DEEP), // BOARD_ID2
|
||||
PAD_CFG_GPI(GPP_C11, NONE, DEEP), // BOARD_ID3
|
||||
PAD_CFG_GPI(GPP_C12, NONE, DEEP), // PERKB_ID2#_R
|
||||
PAD_CFG_GPI(GPP_C13, NONE, DEEP), // PERKB_ID1#_R
|
||||
PAD_NC(GPP_C14, NONE),
|
||||
PAD_NC(GPP_C15, NONE),
|
||||
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // I2C_SDA_TP
|
||||
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // I2C_SCL_TP
|
||||
PAD_CFG_GPI(GPP_C18, NONE, DEEP), // SCI#
|
||||
PAD_CFG_GPI(GPP_C19, NONE, DEEP), // SWI#
|
||||
//PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
|
||||
//PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
|
||||
PAD_CFG_GPO(GPP_C22, 1, DEEP), // UART2_RTS#
|
||||
PAD_CFG_GPI(GPP_C23, NONE, DEEP), // SMI#
|
||||
|
||||
/* ------- GPIO Group GPP_D ------- */
|
||||
PAD_NC(GPP_D0, NONE),
|
||||
PAD_NC(GPP_D1, NONE),
|
||||
PAD_NC(GPP_D2, NONE),
|
||||
PAD_NC(GPP_D3, NONE),
|
||||
PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), // SML1CLK
|
||||
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF2), // CNVI_RF_RST#
|
||||
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), // CNVI_CLKREQ
|
||||
PAD_NC(GPP_D7, NONE),
|
||||
PAD_NC(GPP_D8, NONE),
|
||||
PAD_CFG_NF(GPP_D9, NONE, DEEP, NF1), // SML0_DATA
|
||||
PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1), // SML0_CLK
|
||||
PAD_NC(GPP_D11, NONE),
|
||||
PAD_NC(GPP_D12, NONE),
|
||||
PAD_NC(GPP_D13, NONE),
|
||||
PAD_NC(GPP_D14, NONE),
|
||||
PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1), // SML1DATA
|
||||
PAD_NC(GPP_D16, NONE),
|
||||
PAD_NC(GPP_D17, NONE),
|
||||
PAD_NC(GPP_D18, NONE),
|
||||
PAD_NC(GPP_D19, NONE),
|
||||
PAD_NC(GPP_D20, NONE),
|
||||
PAD_NC(GPP_D21, NONE),
|
||||
PAD_NC(GPP_D22, NONE),
|
||||
PAD_CFG_GPO(GPP_D23, 1, DEEP), // GPU_EVENT#
|
||||
|
||||
/* ------- GPIO Group GPP_E ------- */
|
||||
PAD_NC(GPP_E0, NONE),
|
||||
PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1), // SATAGP1
|
||||
PAD_NC(GPP_E2, NONE),
|
||||
PAD_CFG_GPI(GPP_E3, NONE, DEEP), // SMI#
|
||||
PAD_CFG_NF(GPP_E4, NONE, PWROK, NF1), // DEVSLP0
|
||||
PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), // DEVSLP1
|
||||
PAD_NC(GPP_E6, NONE),
|
||||
PAD_NC(GPP_E7, NONE),
|
||||
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // SATA_LED#
|
||||
PAD_CFG_GPI(GPP_E9, NONE, DEEP), // USB_OC0#
|
||||
PAD_CFG_GPI(GPP_E10, NONE, DEEP), // USB_OC1#
|
||||
PAD_CFG_GPI(GPP_E11, NONE, DEEP), // USB_OC2#
|
||||
PAD_CFG_GPI(GPP_E12, NONE, DEEP), // USB_OC3#
|
||||
|
||||
/* ------- GPIO Group GPP_F ------- */
|
||||
PAD_NC(GPP_F0, NONE),
|
||||
PAD_NC(GPP_F1, NONE),
|
||||
PAD_CFG_GPO(GPP_F2, 1, PLTRST), // GPIO_LANRTD3
|
||||
PAD_CFG_GPO(GPP_F3, 1, DEEP), // LAN_PLT_RST#
|
||||
PAD_CFG_GPO(GPP_F4, 1, DEEP), // SATA_PWR_EN
|
||||
PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), // 1P05_CTRL
|
||||
PAD_NC(GPP_F6, NONE),
|
||||
PAD_CFG_GPI(GPP_F7, NONE, DEEP), // GPIO4_GC6_NVDD_EN_R
|
||||
//PAD_CFG_GPO(GPP_F8, 1, DEEP), // DGPU_RST#_PCH
|
||||
//PAD_CFG_GPO(GPP_F9, 1, DEEP), // DGPU_PWR_EN
|
||||
PAD_CFG_GPI(GPP_F10, NONE, DEEP), // BIOS_REC
|
||||
PAD_CFG_GPI(GPP_F11, NONE, DEEP), // PCH_RSVD
|
||||
PAD_CFG_GPI(GPP_F12, NONE, DEEP), // WLAN_EN
|
||||
PAD_CFG_GPI(GPP_F13, NONE, DEEP), // GP39_GFX_CRB_DETECT
|
||||
PAD_NC(GPP_F14, NONE),
|
||||
PAD_CFG_GPI(GPP_F15, NONE, DEEP), // H_SKTOCC_N
|
||||
PAD_NC(GPP_F16, NONE),
|
||||
PAD_CFG_GPO(GPP_F17, 1, DEEP), // SB_BLON
|
||||
PAD_NC(GPP_F18, NONE),
|
||||
//PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
|
||||
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON
|
||||
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS
|
||||
PAD_NC(GPP_F22, NONE), // VNN_CTRL
|
||||
PAD_NC(GPP_F23, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_G ------- */
|
||||
PAD_NC(GPP_G0, NONE),
|
||||
PAD_CFG_GPI(GPP_G1, NONE, DEEP), // CNVI_DET#
|
||||
PAD_NC(GPP_G2, DN_20K), // GSYNC_ID
|
||||
PAD_NC(GPP_G3, NONE),
|
||||
PAD_NC(GPP_G4, NONE),
|
||||
PAD_NC(GPP_G5, NONE),
|
||||
PAD_NC(GPP_G6, NONE),
|
||||
PAD_NC(GPP_G7, NONE),
|
||||
PAD_NC(GPP_G8, NONE),
|
||||
PAD_CFG_GPI(GPP_G9, NONE, DEEP), // GPP_G9
|
||||
PAD_NC(GPP_G10, NONE),
|
||||
PAD_CFG_GPI(GPP_G11, NONE, DEEP), // GPP_G11
|
||||
PAD_NC(GPP_G12, NATIVE),
|
||||
PAD_CFG_GPI(GPP_G13, NONE, DEEP), // GPP_G13
|
||||
PAD_CFG_GPI(GPP_G14, NATIVE, DEEP), // PCH_MDP_CLK
|
||||
PAD_CFG_GPI(GPP_G15, NONE, DEEP), // PCH_MDP_DATA
|
||||
|
||||
/* ------- GPIO Group GPP_H ------- */
|
||||
PAD_NC(GPP_H0, NONE),
|
||||
PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1), // SDD_CLKREQ#
|
||||
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // LAN_CLKREQ#
|
||||
PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), // PEG_CLKREQ#
|
||||
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // SDD2_CLKREQ#
|
||||
PAD_NC(GPP_H5, NONE),
|
||||
PAD_CFG_GPI(GPP_H6, NONE, DEEP), // SB_KBCRST#
|
||||
PAD_NC(GPP_H7, NONE),
|
||||
PAD_NC(GPP_H8, NONE),
|
||||
PAD_NC(GPP_H9, NONE),
|
||||
PAD_NC(GPP_H10, NONE),
|
||||
PAD_NC(GPP_H11, NONE),
|
||||
PAD_NC(GPP_H12, NONE),
|
||||
PAD_NC(GPP_H13, NONE),
|
||||
PAD_NC(GPP_H14, NONE),
|
||||
PAD_NC(GPP_H15, NONE),
|
||||
PAD_NC(GPP_H16, NONE),
|
||||
PAD_CFG_GPO(GPP_H17, 1, DEEP), // SATA_M2_PWR_EN2
|
||||
PAD_NC(GPP_H18, NONE),
|
||||
PAD_NC(GPP_H19, NONE), // GSYNC_DET
|
||||
PAD_NC(GPP_H20, NONE),
|
||||
PAD_NC(GPP_H21, NONE),
|
||||
PAD_NC(GPP_H22, NONE),
|
||||
PAD_CFG_GPO(GPP_H23, 1, DEEP), // GPP_H23_SDD_RST#
|
||||
|
||||
/* ------- GPIO Group GPP_I ------- */
|
||||
PAD_NC(GPP_I0, NONE),
|
||||
_PAD_CFG_STRUCT(GPP_I1, 0x46880100, 0x0000), // MDP_E_HPD_PCH
|
||||
_PAD_CFG_STRUCT(GPP_I2, 0x46880100, 0x0000), // DP_F_HPD
|
||||
PAD_NC(GPP_I3, NONE),
|
||||
PAD_NC(GPP_I4, NONE),
|
||||
PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), // HDMI_CTRLCLK
|
||||
PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), // HDMI_CTRLDATA
|
||||
PAD_NC(GPP_I7, NONE),
|
||||
PAD_NC(GPP_I8, NONE),
|
||||
PAD_CFG_GPO(GPP_I9, 1, DEEP), // GGPP_I9_SDD2_RST#
|
||||
PAD_CFG_TERM_GPO(GPP_I10, 0, DN_20K, DEEP), // GPP_I10_TEST_R
|
||||
PAD_CFG_NF(GPP_I11, NONE, DEEP, NF2), // SMD_7411
|
||||
PAD_CFG_NF(GPP_I12, NONE, DEEP, NF2), // SMC_7411
|
||||
PAD_CFG_GPI(GPP_I13, NONE, PLTRST), // USB_OC6#
|
||||
PAD_CFG_GPI(GPP_I14, NONE, PLTRST), // USB_OC7#
|
||||
|
||||
/* ------- GPIO Group GPP_J ------- */
|
||||
PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
|
||||
PAD_CFG_NF(GPP_J1, NONE, DEEP, NF1), // CPU_C10_GATE#
|
||||
PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1), // CNVI_BRI_DT / crystal select
|
||||
PAD_CFG_NF(GPP_J3, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
|
||||
PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // CNVI_RGI_DT / M.2 CNVi strap
|
||||
PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
|
||||
PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
|
||||
PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1), // CNVI_MFUART2_TXD
|
||||
PAD_CFG_GPI(GPP_J8, NONE, PLTRST), // GPIO4_GC6_NVDD_EN_R
|
||||
PAD_NC(GPP_J9, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_K ------- */
|
||||
PAD_CFG_GPO(GPP_K0, 0, DEEP), // DGPU_OVRM
|
||||
PAD_NC(GPP_K1, NONE),
|
||||
PAD_CFG_GPI(GPP_K2, NONE, DEEP), // DGPU_PWRGD_R
|
||||
PAD_NC(GPP_K3, NONE),
|
||||
PAD_NC(GPP_K4, NONE),
|
||||
PAD_NC(GPP_K5, NONE),
|
||||
PAD_CFG_NF(GPP_K6, NONE, DEEP, NF1), // EDP_HPD
|
||||
PAD_CFG_NF(GPP_K7, NONE, DEEP, NF1), // HDMI_HPD
|
||||
PAD_CFG_NF(GPP_K8, NONE, DEEP, NF1), // CORE_VID0
|
||||
PAD_CFG_NF(GPP_K9, NONE, DEEP, NF1), // CORE_VID1
|
||||
PAD_NC(GPP_K10, NONE),
|
||||
PAD_CFG_GPI(GPP_K11, NONE, PLTRST), // GC6_FB_EN_PCH
|
||||
|
||||
/* ------- GPIO Group GPP_R ------- */
|
||||
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK
|
||||
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC
|
||||
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT
|
||||
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0
|
||||
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // HDA_RST#
|
||||
PAD_NC(GPP_R5, NONE),
|
||||
PAD_NC(GPP_R6, NONE),
|
||||
PAD_NC(GPP_R7, NONE),
|
||||
PAD_NC(GPP_R8, NONE),
|
||||
PAD_NC(GPP_R9, NONE),
|
||||
PAD_NC(GPP_R10, NONE),
|
||||
PAD_NC(GPP_R11, NONE),
|
||||
PAD_CFG_GPI_INT(GPP_R12, NONE, PLTRST, LEVEL), // TP_ATTN#
|
||||
PAD_NC(GPP_R13, NONE),
|
||||
PAD_NC(GPP_R14, NONE),
|
||||
PAD_NC(GPP_R15, NONE),
|
||||
PAD_NC(GPP_R16, NONE),
|
||||
PAD_NC(GPP_R17, NONE),
|
||||
PAD_NC(GPP_R18, NONE),
|
||||
PAD_NC(GPP_R19, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_S ------- */
|
||||
PAD_NC(GPP_S0, NONE),
|
||||
PAD_NC(GPP_S1, NONE),
|
||||
PAD_NC(GPP_S2, NONE),
|
||||
PAD_NC(GPP_S3, NONE), // 100k pull-down
|
||||
PAD_NC(GPP_S4, NONE),
|
||||
PAD_NC(GPP_S5, NONE),
|
||||
PAD_CFG_GPI(GPP_S6, NONE, DEEP), // MIC_CLK_PCH
|
||||
PAD_CFG_GPI(GPP_S7, NONE, DEEP), // MIC_DATA_PCH
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
75
src/mainboard/system76/gaze16/variants/3060/overridetree.cb
Normal file
75
src/mainboard/system76/gaze16/variants/3060/overridetree.cb
Normal file
@ -0,0 +1,75 @@
|
||||
chip soc/intel/tigerlake
|
||||
device domain 0 on
|
||||
device ref peg1 on
|
||||
# PCIe PEG1 x16, Clock 9 (DGPU)
|
||||
register "PcieClkSrcUsage[9]" = "0x41"
|
||||
register "PcieClkSrcClkReq[9]" = "9"
|
||||
chip soc/intel/common/block/pcie/rtd3
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # DGPU_PWR_EN
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F8)" # DGPU_RST#_PCH
|
||||
register "enable_delay_ms" = "16"
|
||||
register "enable_off_delay_ms" = "4"
|
||||
register "reset_delay_ms" = "10"
|
||||
register "reset_off_delay_ms" = "4"
|
||||
#TODO: Support disable/enable CPU RP clock
|
||||
register "srcclk_pin" = "-1" # PEG_CLKREQ#
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref peg0 on
|
||||
# PCIe PEG0 x4, Clock 7 (SSD1)
|
||||
register "PcieClkSrcUsage[7]" = "0x40"
|
||||
register "PcieClkSrcClkReq[7]" = "7"
|
||||
|
||||
#TODO: Hybrid storage mode?
|
||||
register "HybridStorageMode" = "0"
|
||||
end
|
||||
device ref south_xhci on
|
||||
# USB2
|
||||
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 2 (Right)
|
||||
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 1 (Left)
|
||||
register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.2 Gen 2 Type C (Back)
|
||||
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB 2.0 (Left)
|
||||
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
|
||||
register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Per-Key
|
||||
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
|
||||
register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
|
||||
# USB3
|
||||
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 2 (Right)
|
||||
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 1 (Left)
|
||||
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 2 Type C (Back)
|
||||
end
|
||||
device ref sata on
|
||||
register "SataPortsEnable[0]" = "1" # HDD (SATA0B)
|
||||
register "SataPortsEnable[1]" = "1" # SSD2 (SATA1A)
|
||||
end
|
||||
device ref pcie_rp5 on
|
||||
# PCIe root port #5 x1, Clock 8 (GLAN)
|
||||
register "PcieRpEnable[4]" = "1"
|
||||
register "PcieRpLtrEnable[4]" = "1"
|
||||
register "PcieClkSrcUsage[8]" = "4"
|
||||
register "PcieClkSrcClkReq[8]" = "8"
|
||||
end
|
||||
device ref pcie_rp7 on
|
||||
# PCIe root port #7 x1, Clock 3 (CARD)
|
||||
register "PcieRpEnable[6]" = "1"
|
||||
register "PcieRpLtrEnable[6]" = "1"
|
||||
register "PcieClkSrcUsage[3]" = "6"
|
||||
register "PcieClkSrcClkReq[3]" = "3"
|
||||
end
|
||||
device ref pcie_rp8 on
|
||||
# PCIe root port #8 x1, Clock 2 (WLAN)
|
||||
register "PcieRpEnable[7]" = "1"
|
||||
register "PcieRpLtrEnable[7]" = "1"
|
||||
register "PcieClkSrcUsage[2]" = "7"
|
||||
register "PcieClkSrcClkReq[2]" = "2"
|
||||
end
|
||||
device ref pcie_rp9 on
|
||||
# PCIe root port #9 x4, Clock 10 (SSD2)
|
||||
register "PcieRpEnable[8]" = "1"
|
||||
register "PcieRpLtrEnable[8]" = "1"
|
||||
register "PcieClkSrcUsage[10]" = "8"
|
||||
register "PcieClkSrcClkReq[10]" = "10"
|
||||
end
|
||||
end
|
||||
end
|
||||
16
src/mainboard/system76/gaze16/variants/3060/ramstage.c
Normal file
16
src/mainboard/system76/gaze16/variants/3060/ramstage.c
Normal file
@ -0,0 +1,16 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include "../../variant.h"
|
||||
|
||||
void variant_silicon_init_params(FSP_S_CONFIG *params)
|
||||
{
|
||||
// PEG0 Config
|
||||
params->CpuPcieRpAdvancedErrorReporting[0] = 0;
|
||||
params->CpuPcieRpLtrEnable[0] = 1;
|
||||
params->CpuPcieRpPtmEnabled[0] = 0;
|
||||
|
||||
// PEG1 Config
|
||||
params->CpuPcieRpAdvancedErrorReporting[1] = 0;
|
||||
params->CpuPcieRpLtrEnable[1] = 1;
|
||||
params->CpuPcieRpPtmEnabled[1] = 0;
|
||||
}
|
||||
9
src/mainboard/system76/gaze16/variants/3060/romstage.c
Normal file
9
src/mainboard/system76/gaze16/variants/3060/romstage.c
Normal file
@ -0,0 +1,9 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include "../../variant.h"
|
||||
|
||||
void variant_memory_init_params(FSPM_UPD *mupd)
|
||||
{
|
||||
// Enable M.2 PCIE 4.0 and PEG1
|
||||
mupd->FspmConfig.CpuPcieRpEnableMask = 0b11;
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user