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nb/intel/x4x: Use new fixed BAR accessors

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Some cases break reproducibility if refactored, and are left as-is.

Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical.

Change-Id: I163995c0b107860449c2f36ad63e4e4ca52decb2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51878
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons
2021-03-27 09:35:57 +01:00
committed by Nico Huber
parent 93aab51ec1
commit a5146f3239
6 changed files with 483 additions and 499 deletions
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48
src/northbridge/intel/x4x/dq_dqs.c
View File

@@ -167,7 +167,7 @@ static u8 test_dq_aligned(const struct sysinfo *s, const u8 channel)
for (count = 0; count < WT_PATTERN_SIZE; count++) { for (count = 0; count < WT_PATTERN_SIZE; count++) {
for (count1 = 0; count1 < WT_PATTERN_SIZE; count1++) { for (count1 = 0; count1 < WT_PATTERN_SIZE; count1++) {
if ((count1 % 16) == 0) if ((count1 % 16) == 0)
MCHBAR32(0xf90) = 1; mchbar_write32(0xf90, 1);
const u32 pattern = write_training_schedule[count1]; const u32 pattern = write_training_schedule[count1];
write32((u32 *)address + 8 * count1, pattern); write32((u32 *)address + 8 * count1, pattern);
write32((u32 *)address + 8 * count1 + 4, pattern); write32((u32 *)address + 8 * count1 + 4, pattern);
@@ -620,7 +620,7 @@ static void sample_dq(const struct sysinfo *s, u8 channel, u8 rank,
write32((u32 *)address + 4, 0x12341234); write32((u32 *)address + 4, 0x12341234);
udelay(5); udelay(5);
FOR_EACH_BYTELANE(lane) { FOR_EACH_BYTELANE(lane) {
u8 dq_high = (MCHBAR8(0x561 + 0x400 * channel u8 dq_high = (mchbar_read8(0x561 + 0x400 * channel
+ (lane * 4)) >> 7) & 1; + (lane * 4)) >> 7) & 1;
high_found[lane] += dq_high; high_found[lane] += dq_high;
} }
@@ -639,7 +639,7 @@ static enum cb_err increment_to_dqs_edge(struct sysinfo *s, u8 channel, u8 rank)
FOR_EACH_BYTELANE(lane) FOR_EACH_BYTELANE(lane)
dqsset(channel, lane, &dqs_setting[lane]); dqsset(channel, lane, &dqs_setting[lane]);
saved_24d = MCHBAR8(0x24d + 0x400 * channel); saved_24d = mchbar_read8(0x24d + 0x400 * channel);
/* Loop 0: Find DQ sample low, by decreasing */ /* Loop 0: Find DQ sample low, by decreasing */
while (bytelane_ok != 0xff) { while (bytelane_ok != 0xff) {
@@ -715,7 +715,7 @@ static enum cb_err increment_to_dqs_edge(struct sysinfo *s, u8 channel, u8 rank)
s->dqs_settings[channel][lane] = dqs_setting[lane]; s->dqs_settings[channel][lane] = dqs_setting[lane];
} }
MCHBAR8(0x24d + 0x400 * channel) = saved_24d; mchbar_write8(0x24d + 0x400 * channel, saved_24d);
return CB_SUCCESS; return CB_SUCCESS;
} }
@@ -762,11 +762,9 @@ void search_write_leveling(struct sysinfo *s)
printk(BIOS_DEBUG, "\tCH%d\n", ch); printk(BIOS_DEBUG, "\tCH%d\n", ch);
config = chanconfig_lut[s->dimm_config[ch]]; config = chanconfig_lut[s->dimm_config[ch]];
MCHBAR8(0x5d8 + 0x400 * ch) = MCHBAR8(0x5d8 + 0x400 * ch) & ~0x0e; mchbar_clrbits8(0x5d8 + 0x400 * ch, 0x0e);
MCHBAR16(0x5c4 + 0x400 * ch) = (MCHBAR16(0x5c4 + 0x400 * ch) & mchbar_clrsetbits16(0x5c4 + 0x400 * ch, 0x3fff, 0x3fff);
~0x3fff) | 0x3fff; mchbar_clrbits8(0x265 + 0x400 * ch, 0x1f);
MCHBAR8(0x265 + 0x400 * ch) =
MCHBAR8(0x265 + 0x400 * ch) & ~0x1f;
/* find the first populated rank */ /* find the first populated rank */
FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, ch, rank0) FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, ch, rank0)
break; break;
@@ -776,41 +774,33 @@ void search_write_leveling(struct sysinfo *s)
FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, ch, rank1) FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, ch, rank1)
set_rank_write_level(s, ch, config, rank1, rank0, 1); set_rank_write_level(s, ch, config, rank1, rank0, 1);
MCHBAR8(0x298 + 2 + 0x400 * ch) = mchbar_clrsetbits8(0x298 + 2 + 0x400 * ch, 0x0f, odt_force[config][rank0]);
(MCHBAR8(0x298 + 2 + 0x400 * ch) & ~0x0f) mchbar_clrsetbits8(0x271 + 0x400 * ch, 0x7e, 0x4e);
| odt_force[config][rank0]; mchbar_setbits8(0x5d9 + 0x400 * ch, 1 << 2);
MCHBAR8(0x271 + 0x400 * ch) = (MCHBAR8(0x271 + 0x400 * ch) & ~0x7e) | 0x4e; mchbar_clrsetbits32(0x1a0, 0x07ffffff, 0x00014000);
MCHBAR8(0x5d9 + 0x400 * ch) = (MCHBAR8(0x5d9 + 0x400 * ch) & ~0x04) | 0x04;
MCHBAR32(0x1a0) = (MCHBAR32(0x1a0) & ~0x07ffffff) | 0x00014000;
if (increment_to_dqs_edge(s, ch, rank0)) if (increment_to_dqs_edge(s, ch, rank0))
die("Write Leveling failed!"); die("Write Leveling failed!");
MCHBAR8(0x298 + 2 + 0x400 * ch) = mchbar_clrbits8(0x298 + 2 + 0x400 * ch, 0x0f);
MCHBAR8(0x298 + 2 + 0x400 * ch) & ~0x0f; mchbar_clrsetbits8(0x271 + 0x400 * ch, 0x7e, 0x0e);
MCHBAR8(0x271 + 0x400 * ch) = mchbar_clrbits8(0x5d9 + 0x400 * ch, 1 << 2);
(MCHBAR8(0x271 + 0x400 * ch) & ~0x7e) mchbar_clrsetbits32(0x1a0, 0x07ffffff, 0x00555801);
| 0x0e;
MCHBAR8(0x5d9 + 0x400 * ch) =
(MCHBAR8(0x5d9 + 0x400 * ch) & ~0x04);
MCHBAR32(0x1a0) = (MCHBAR32(0x1a0)
& ~0x07ffffff) | 0x00555801;
/* Disable WL on the trained rank */ /* Disable WL on the trained rank */
set_rank_write_level(s, ch, config, rank0, rank0, 0); set_rank_write_level(s, ch, config, rank0, rank0, 0);
send_jedec_cmd(s, rank0, ch, NORMALOP_CMD, 1 << 12); send_jedec_cmd(s, rank0, ch, NORMALOP_CMD, 1 << 12);
MCHBAR8(0x5d8 + 0x400 * ch) = (MCHBAR8(0x5d8 + 0x400 * ch) & ~0x0e) | 0x0e; mchbar_setbits8(0x5d8 + 0x400 * ch, 0x0e);
MCHBAR16(0x5c4 + 0x400 * ch) = (MCHBAR16(0x5c4 + 0x400 * ch) mchbar_clrsetbits16(0x5c4 + 0x400 * ch, 0x3fff, 0x1807);
& ~0x3fff) | 0x1807; mchbar_clrbits8(0x265 + 0x400 * ch, 0x1f);
MCHBAR8(0x265 + 0x400 * ch) = MCHBAR8(0x265 + 0x400 * ch) & ~0x1f;
/* Disable write level mode for all ranks */ /* Disable write level mode for all ranks */
FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, ch, rank0) FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, ch, rank0)
set_rank_write_level(s, ch, config, rank0, rank0, 0); set_rank_write_level(s, ch, config, rank0, rank0, 0);
} }
MCHBAR8(0x5dc) = (MCHBAR8(0x5dc) & ~0x80) | 0x80; mchbar_setbits8(0x5dc, 1 << 7);
/* Increment DQ (rx) dll setting by a standard amount past DQS, /* Increment DQ (rx) dll setting by a standard amount past DQS,
This is further trained in write training. */ This is further trained in write training. */

76
src/northbridge/intel/x4x/early_init.c
View File

@@ -59,59 +59,59 @@ static void init_egress(void)
u32 reg32; u32 reg32;
/* VC0: TC0 only */ /* VC0: TC0 only */
EPBAR8(EPVC0RCTL) = 1; epbar_write8(EPVC0RCTL, 1);
EPBAR8(EPPVCCAP1) = 1; epbar_write8(EPPVCCAP1, 1);
switch (MCHBAR32(CLKCFG_MCHBAR) & CLKCFG_FSBCLK_MASK) { switch (mchbar_read32(CLKCFG_MCHBAR) & CLKCFG_FSBCLK_MASK) {
case 0x0: case 0x0:
/* FSB 1066 */ /* FSB 1066 */
EPBAR32(EPVC1ITC) = 0x0001a6db; epbar_write32(EPVC1ITC, 0x0001a6db);
break; break;
case 0x2: case 0x2:
/* FSB 800 */ /* FSB 800 */
EPBAR32(EPVC1ITC) = 0x00014514; epbar_write32(EPVC1ITC, 0x00014514);
break; break;
default: default:
case 0x4: case 0x4:
/* FSB 1333 */ /* FSB 1333 */
EPBAR32(EPVC1ITC) = 0x00022861; epbar_write32(EPVC1ITC, 0x00022861);
break; break;
} }
EPBAR32(EPVC1MTS) = 0x0a0a0a0a; epbar_write32(EPVC1MTS, 0x0a0a0a0a);
EPBAR8(EPPVCCTL) = (EPBAR8(EPPVCCTL) & ~0xe) | 2; epbar_clrsetbits8(EPPVCCTL, 7 << 1, 1 << 1);
EPBAR32(EPVC1RCAP) = (EPBAR32(EPVC1RCAP) & ~0x7f0000) | 0x0a0000; epbar_clrsetbits32(EPVC1RCAP, 0x7f << 16, 0x0a << 16);
MCHBAR8(0x3c) = MCHBAR8(0x3c) | 0x7; mchbar_setbits8(0x3c, 7);
/* VC1: ID1, TC7 */ /* VC1: ID1, TC7 */
reg32 = (EPBAR32(EPVC1RCTL) & ~(7 << 24)) | (1 << 24); reg32 = (epbar_read32(EPVC1RCTL) & ~(7 << 24)) | (1 << 24);
reg32 = (reg32 & ~0xfe) | (1 << 7); reg32 = (reg32 & ~0xfe) | (1 << 7);
EPBAR32(EPVC1RCTL) = reg32; epbar_write32(EPVC1RCTL, reg32);
/* Init VC1 port arbitration table */ /* Init VC1 port arbitration table */
EPBAR32(EP_PORTARB(0)) = 0x001000001; epbar_write32(EP_PORTARB(0), 0x001000001);
EPBAR32(EP_PORTARB(1)) = 0x000040000; epbar_write32(EP_PORTARB(1), 0x000040000);
EPBAR32(EP_PORTARB(2)) = 0x000001000; epbar_write32(EP_PORTARB(2), 0x000001000);
EPBAR32(EP_PORTARB(3)) = 0x000000040; epbar_write32(EP_PORTARB(3), 0x000000040);
EPBAR32(EP_PORTARB(4)) = 0x001000001; epbar_write32(EP_PORTARB(4), 0x001000001);
EPBAR32(EP_PORTARB(5)) = 0x000040000; epbar_write32(EP_PORTARB(5), 0x000040000);
EPBAR32(EP_PORTARB(6)) = 0x000001000; epbar_write32(EP_PORTARB(6), 0x000001000);
EPBAR32(EP_PORTARB(7)) = 0x000000040; epbar_write32(EP_PORTARB(7), 0x000000040);
/* Load table */ /* Load table */
reg32 = EPBAR32(EPVC1RCTL) | (1 << 16); reg32 = epbar_read32(EPVC1RCTL) | (1 << 16);
EPBAR32(EPVC1RCTL) = reg32; epbar_write32(EPVC1RCTL, reg32);
asm("nop"); asm("nop");
EPBAR32(EPVC1RCTL) = reg32; epbar_write32(EPVC1RCTL, reg32);
/* Wait for table load */ /* Wait for table load */
while ((EPBAR8(EPVC1RSTS) & (1 << 0)) != 0) while ((epbar_read8(EPVC1RSTS) & (1 << 0)) != 0)
; ;
/* VC1: enable */ /* VC1: enable */
EPBAR32(EPVC1RCTL) |= 1 << 31; epbar_setbits32(EPVC1RCTL, 1 << 31);
/* Wait for VC1 */ /* Wait for VC1 */
while ((EPBAR8(EPVC1RSTS) & (1 << 1)) != 0) while ((epbar_read8(EPVC1RSTS) & (1 << 1)) != 0)
; ;
printk(BIOS_DEBUG, "Done Egress Port\n"); printk(BIOS_DEBUG, "Done Egress Port\n");
@@ -124,22 +124,22 @@ static void init_dmi(void)
/* Assume IGD present */ /* Assume IGD present */
/* Clear error status */ /* Clear error status */
DMIBAR32(DMIUESTS) = 0xffffffff; dmibar_write32(DMIUESTS, 0xffffffff);
DMIBAR32(DMICESTS) = 0xffffffff; dmibar_write32(DMICESTS, 0xffffffff);
/* VC0: TC0 only */ /* VC0: TC0 only */
DMIBAR8(DMIVC0RCTL) = 1; dmibar_write8(DMIVC0RCTL, 1);
DMIBAR8(DMIPVCCAP1) = 1; dmibar_write8(DMIPVCCAP1, 1);
/* VC1: ID1, TC7 */ /* VC1: ID1, TC7 */
reg32 = (DMIBAR32(DMIVC1RCTL) & ~(7 << 24)) | (1 << 24); reg32 = (dmibar_read32(DMIVC1RCTL) & ~(7 << 24)) | (1 << 24);
reg32 = (reg32 & ~0xff) | 1 << 7; reg32 = (reg32 & ~0xff) | 1 << 7;
/* VC1: enable */ /* VC1: enable */
reg32 |= 1 << 31; reg32 |= 1 << 31;
reg32 = (reg32 & ~(0x7 << 17)) | (0x4 << 17); reg32 = (reg32 & ~(0x7 << 17)) | (0x4 << 17);
DMIBAR32(DMIVC1RCTL) = reg32; dmibar_write32(DMIVC1RCTL, reg32);
/* Set up VCs in southbridge RCBA */ /* Set up VCs in southbridge RCBA */
RCBA8(0x3022) &= ~1; RCBA8(0x3022) &= ~1;
@@ -202,17 +202,17 @@ static void init_dmi(void)
/* Set up VC1 max time */ /* Set up VC1 max time */
RCBA32(0x1c) = (RCBA32(0x1c) & ~0x7f0000) | 0x120000; RCBA32(0x1c) = (RCBA32(0x1c) & ~0x7f0000) | 0x120000;
while ((DMIBAR32(DMIVC1RSTS) & VC1NP) != 0) while ((dmibar_read32(DMIVC1RSTS) & VC1NP) != 0)
; ;
printk(BIOS_DEBUG, "Done DMI setup\n"); printk(BIOS_DEBUG, "Done DMI setup\n");
/* ASPM on DMI */ /* ASPM on DMI */
DMIBAR32(0x200) &= ~(0x3 << 26); dmibar_clrbits32(0x200, 3 << 26);
DMIBAR16(0x210) = (DMIBAR16(0x210) & ~(0xff7)) | 0x101; dmibar_clrsetbits16(0x210, 0xff7, 0x101);
DMIBAR32(DMILCTL) &= ~0x3; dmibar_clrbits32(DMILCTL, 3);
DMIBAR32(DMILCTL) |= 0x3; dmibar_setbits32(DMILCTL, 3);
/* FIXME: Do we need to read RCBA16(DMILCTL)? Probably not. */ /* FIXME: Do we need to read RCBA16(DMILCTL)? Probably not. */
DMIBAR16(DMILCTL); dmibar_read16(DMILCTL);
} }
void x4x_late_init(void) void x4x_late_init(void)

4
src/northbridge/intel/x4x/raminit.c
View File

@@ -412,7 +412,7 @@ static void print_selected_timings(struct sysinfo *s)
static void find_fsb_speed(struct sysinfo *s) static void find_fsb_speed(struct sysinfo *s)
{ {
switch ((MCHBAR32(CLKCFG_MCHBAR) & CLKCFG_FSBCLK_MASK) >> CLKCFG_FSBCLK_SHIFT) { switch ((mchbar_read32(CLKCFG_MCHBAR) & CLKCFG_FSBCLK_MASK) >> CLKCFG_FSBCLK_SHIFT) {
case 0x0: case 0x0:
s->max_fsb = FSB_CLOCK_1066MHz; s->max_fsb = FSB_CLOCK_1066MHz;
break; break;
@@ -532,7 +532,7 @@ static void checkreset_ddr2(int boot_path)
u32 pmsts; u32 pmsts;
if (boot_path >= 1) { if (boot_path >= 1) {
pmsts = MCHBAR32(PMSTS_MCHBAR); pmsts = mchbar_read32(PMSTS_MCHBAR);
if (!(pmsts & 1)) if (!(pmsts & 1))
printk(BIOS_DEBUG, "Channel 0 possibly not in self refresh\n"); printk(BIOS_DEBUG, "Channel 0 possibly not in self refresh\n");
if (!(pmsts & 2)) if (!(pmsts & 2))

817
src/northbridge/intel/x4x/raminit_ddr23.c
View File

File diff suppressed because it is too large Load Diff

35
src/northbridge/intel/x4x/rcven.c
View File

@@ -30,16 +30,16 @@ static u8 sampledqs(u32 addr, u8 lane, u8 channel)
/* Reset the DQS probe, on both channels? */ /* Reset the DQS probe, on both channels? */
for (u8 i = 0; i < TOTAL_CHANNELS; i++) { for (u8 i = 0; i < TOTAL_CHANNELS; i++) {
MCHBAR8(RESET_CNTL(i)) &= ~0x2; mchbar_clrbits8(RESET_CNTL(i), 1 << 1);
udelay(1); udelay(1);
MCHBAR8(RESET_CNTL(i)) |= 0x2; mchbar_setbits8(RESET_CNTL(i), 1 << 1);
udelay(1); udelay(1);
} }
mfence(); mfence();
/* Read strobe */ /* Read strobe */
read32((u32 *)addr); read32((u32 *)addr);
mfence(); mfence();
return (MCHBAR8(sample_offset) >> 6) & 1; return mchbar_read8(sample_offset) >> 6 & 1;
} }
static void program_timing(const struct rec_timing *timing, u8 channel, u8 lane) static void program_timing(const struct rec_timing *timing, u8 channel, u8 lane)
@@ -51,21 +51,21 @@ static void program_timing(const struct rec_timing *timing, u8 channel, u8 lane)
printk(RAM_SPEW, " Programming timings:Coarse: %d, Medium: %d, TAP: %d, PI: %d\n", printk(RAM_SPEW, " Programming timings:Coarse: %d, Medium: %d, TAP: %d, PI: %d\n",
timing->coarse, timing->medium, timing->tap, timing->pi); timing->coarse, timing->medium, timing->tap, timing->pi);
reg32 = MCHBAR32(0x400 * channel + 0x248); reg32 = mchbar_read32(0x400 * channel + 0x248);
reg32 &= ~0xf0000; reg32 &= ~0xf0000;
reg32 |= timing->coarse << 16; reg32 |= timing->coarse << 16;
MCHBAR32(0x400 * channel + 0x248) = reg32; mchbar_write32(0x400 * channel + 0x248, reg32);
reg16 = MCHBAR16(0x400 * channel + 0x58c); reg16 = mchbar_read16(0x400 * channel + 0x58c);
reg16 &= ~(3 << (lane * 2)); reg16 &= ~(3 << (lane * 2));
reg16 |= timing->medium << (lane * 2); reg16 |= timing->medium << (lane * 2);
MCHBAR16(0x400 * channel + 0x58c) = reg16; mchbar_write16(0x400 * channel + 0x58c, reg16);
reg8 = MCHBAR8(0x400 * channel + 0x560 + lane * 4); reg8 = mchbar_read8(0x400 * channel + 0x560 + lane * 4);
reg8 &= ~0x7f; reg8 &= ~0x7f;
reg8 |= timing->tap; reg8 |= timing->tap;
reg8 |= timing->pi << 4; reg8 |= timing->pi << 4;
MCHBAR8(0x400 * channel + 0x560 + lane * 4) = reg8; mchbar_write8(0x400 * channel + 0x560 + lane * 4, reg8);
} }
static int increase_medium(struct rec_timing *timing) static int increase_medium(struct rec_timing *timing)
@@ -241,8 +241,7 @@ static int calibrate_receive_enable(u8 channel, u8 lane,
{ {
program_timing(timing, channel, lane); program_timing(timing, channel, lane);
/* Set receive enable bit */ /* Set receive enable bit */
MCHBAR16(0x400 * channel + 0x588) = (MCHBAR16(0x400 * channel + 0x588) mchbar_clrsetbits16(0x400 * channel + 0x588, 3 << (lane * 2), 1 << (lane * 2));
& ~(3 << (lane * 2))) | (1 << (lane * 2));
if (find_dqs_low(channel, lane, addr, timing)) if (find_dqs_low(channel, lane, addr, timing))
return -1; return -1;
@@ -275,8 +274,7 @@ static int calibrate_receive_enable(u8 channel, u8 lane,
program_timing(timing, channel, lane); program_timing(timing, channel, lane);
/* Unset receive enable bit */ /* Unset receive enable bit */
MCHBAR16(0x400 * channel + 0x588) = MCHBAR16(0x400 * channel + 0x588) & mchbar_clrbits16(0x400 * channel + 0x588, 3 << (lane * 2));
~(3 << (lane * 2));
return 0; return 0;
} }
@@ -294,9 +292,9 @@ void rcven(struct sysinfo *s)
printk(BIOS_DEBUG, "Starting DQS receiver enable calibration\n"); printk(BIOS_DEBUG, "Starting DQS receiver enable calibration\n");
MCHBAR8(0x5d8) = MCHBAR8(0x5d8) & ~0xc; mchbar_clrbits8(0x5d8, 3 << 2);
MCHBAR8(0x9d8) = MCHBAR8(0x9d8) & ~0xc; mchbar_clrbits8(0x9d8, 3 << 2);
MCHBAR8(0x5dc) = MCHBAR8(0x5dc) & ~0x80; mchbar_clrbits8(0x5dc, 1 << 7);
FOR_EACH_POPULATED_CHANNEL(s->dimms, channel) { FOR_EACH_POPULATED_CHANNEL(s->dimms, channel) {
mincoarse = 0xff; mincoarse = 0xff;
/* /*
@@ -355,9 +353,8 @@ void rcven(struct sysinfo *s)
s->rcven_t[channel].medium[lane] = timing[lane].medium; s->rcven_t[channel].medium[lane] = timing[lane].medium;
s->rcven_t[channel].tap[lane] = timing[lane].tap; s->rcven_t[channel].tap[lane] = timing[lane].tap;
s->rcven_t[channel].pi[lane] = timing[lane].pi; s->rcven_t[channel].pi[lane] = timing[lane].pi;
MCHBAR16(0x400 * channel + 0x5fa) = mchbar_clrsetbits16(0x400 * channel + 0x5fa, 3 << (lane * 2),
(MCHBAR16(0x400 * channel + 0x5fa) & reg8 << (lane * 2));
~(3 << (lane * 2))) | (reg8 << (lane * 2));
} }
/* simply use timing[0] to program mincoarse */ /* simply use timing[0] to program mincoarse */
timing[0].coarse = mincoarse; timing[0].coarse = mincoarse;

2
src/northbridge/intel/x4x/romstage.c
View File

@@ -37,7 +37,7 @@ void mainboard_romstage_entry(void)
if (s3_resume) if (s3_resume)
boot_path = BOOT_PATH_RESUME; boot_path = BOOT_PATH_RESUME;
if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) if (mchbar_read32(PMSTS_MCHBAR) & PMSTS_WARM_RESET)
boot_path = BOOT_PATH_WARM_RESET; boot_path = BOOT_PATH_WARM_RESET;
mb_get_spd_map(spd_addr_map); mb_get_spd_map(spd_addr_map);